2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
9 * This code is derived from software contributed to Berkeley by
10 * the Systems Programming Group of the University of Utah Computer
11 * Science Department and William Jolitz of UUNET Technologies Inc.
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 * 4. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
40 #include <sys/cdefs.h>
41 __FBSDID("$FreeBSD$");
44 * Manages physical address maps.
46 * In addition to hardware address maps, this module is called upon to
47 * provide software-use-only maps which may or may not be stored in the
48 * same form as hardware maps. These pseudo-maps are used to store
49 * intermediate results from copy operations to and from address spaces.
51 * Since the information managed by this module is also stored by the
52 * logical address mapping module, this module may throw away valid virtual
53 * to physical mappings at almost any time. However, invalidations of
54 * mappings must be done as requested.
56 * In order to cope with hardware architectures which make virtual to
57 * physical map invalidates expensive, this module may delay invalidate
58 * reduced protection operations until such time as they are actually
59 * necessary. This module is given full information as to which processors
60 * are currently using which maps, and to when physical maps must be made
64 #include "opt_kstack_pages.h"
67 #include <sys/param.h>
68 #include <sys/kernel.h>
71 #include <sys/msgbuf.h>
72 #include <sys/mutex.h>
74 #include <sys/rwlock.h>
76 #include <sys/sysctl.h>
77 #include <sys/systm.h>
78 #include <sys/vmmeter.h>
80 #include <dev/ofw/openfirm.h>
83 #include <vm/vm_param.h>
84 #include <vm/vm_kern.h>
85 #include <vm/vm_page.h>
86 #include <vm/vm_map.h>
87 #include <vm/vm_object.h>
88 #include <vm/vm_extern.h>
89 #include <vm/vm_pageout.h>
90 #include <vm/vm_pager.h>
92 #include <machine/cache.h>
93 #include <machine/frame.h>
94 #include <machine/instr.h>
95 #include <machine/md_var.h>
96 #include <machine/metadata.h>
97 #include <machine/ofw_mem.h>
98 #include <machine/smp.h>
99 #include <machine/tlb.h>
100 #include <machine/tte.h>
101 #include <machine/tsb.h>
102 #include <machine/ver.h>
105 * Virtual address of message buffer
107 struct msgbuf *msgbufp;
110 * Map of physical memory reagions
112 vm_paddr_t phys_avail[128];
113 static struct ofw_mem_region mra[128];
114 struct ofw_mem_region sparc64_memreg[128];
116 static struct ofw_map translations[128];
117 static int translations_size;
119 static vm_offset_t pmap_idle_map;
120 static vm_offset_t pmap_temp_map_1;
121 static vm_offset_t pmap_temp_map_2;
124 * First and last available kernel virtual addresses
126 vm_offset_t virtual_avail;
127 vm_offset_t virtual_end;
128 vm_offset_t kernel_vm_end;
130 vm_offset_t vm_max_kernel_address;
135 struct pmap kernel_pmap_store;
138 * Isolate the global TTE list lock from data and other locks to prevent
139 * false sharing within the cache (see also the declaration of struct
142 struct tte_list_lock tte_list_global __aligned(CACHE_LINE_SIZE);
145 * Allocate physical memory for use in pmap_bootstrap.
147 static vm_paddr_t pmap_bootstrap_alloc(vm_size_t size, uint32_t colors);
149 static void pmap_bootstrap_set_tte(struct tte *tp, u_long vpn, u_long data);
150 static void pmap_cache_remove(vm_page_t m, vm_offset_t va);
151 static int pmap_protect_tte(struct pmap *pm1, struct pmap *pm2,
152 struct tte *tp, vm_offset_t va);
155 * Map the given physical page at the specified virtual address in the
156 * target pmap with the protection requested. If specified the page
157 * will be wired down.
159 * The page queues and pmap must be locked.
161 static void pmap_enter_locked(pmap_t pm, vm_offset_t va, vm_page_t m,
162 vm_prot_t prot, boolean_t wired);
164 extern int tl1_dmmu_miss_direct_patch_tsb_phys_1[];
165 extern int tl1_dmmu_miss_direct_patch_tsb_phys_end_1[];
166 extern int tl1_dmmu_miss_patch_asi_1[];
167 extern int tl1_dmmu_miss_patch_quad_ldd_1[];
168 extern int tl1_dmmu_miss_patch_tsb_1[];
169 extern int tl1_dmmu_miss_patch_tsb_2[];
170 extern int tl1_dmmu_miss_patch_tsb_mask_1[];
171 extern int tl1_dmmu_miss_patch_tsb_mask_2[];
172 extern int tl1_dmmu_prot_patch_asi_1[];
173 extern int tl1_dmmu_prot_patch_quad_ldd_1[];
174 extern int tl1_dmmu_prot_patch_tsb_1[];
175 extern int tl1_dmmu_prot_patch_tsb_2[];
176 extern int tl1_dmmu_prot_patch_tsb_mask_1[];
177 extern int tl1_dmmu_prot_patch_tsb_mask_2[];
178 extern int tl1_immu_miss_patch_asi_1[];
179 extern int tl1_immu_miss_patch_quad_ldd_1[];
180 extern int tl1_immu_miss_patch_tsb_1[];
181 extern int tl1_immu_miss_patch_tsb_2[];
182 extern int tl1_immu_miss_patch_tsb_mask_1[];
183 extern int tl1_immu_miss_patch_tsb_mask_2[];
186 * If user pmap is processed with pmap_remove and with pmap_remove and the
187 * resident count drops to 0, there are no more pages to remove, so we
190 #define PMAP_REMOVE_DONE(pm) \
191 ((pm) != kernel_pmap && (pm)->pm_stats.resident_count == 0)
194 * The threshold (in bytes) above which tsb_foreach() is used in pmap_remove()
195 * and pmap_protect() instead of trying each virtual address.
197 #define PMAP_TSB_THRESH ((TSB_SIZE / 2) * PAGE_SIZE)
199 SYSCTL_NODE(_debug, OID_AUTO, pmap_stats, CTLFLAG_RD, 0, "");
201 PMAP_STATS_VAR(pmap_nenter);
202 PMAP_STATS_VAR(pmap_nenter_update);
203 PMAP_STATS_VAR(pmap_nenter_replace);
204 PMAP_STATS_VAR(pmap_nenter_new);
205 PMAP_STATS_VAR(pmap_nkenter);
206 PMAP_STATS_VAR(pmap_nkenter_oc);
207 PMAP_STATS_VAR(pmap_nkenter_stupid);
208 PMAP_STATS_VAR(pmap_nkremove);
209 PMAP_STATS_VAR(pmap_nqenter);
210 PMAP_STATS_VAR(pmap_nqremove);
211 PMAP_STATS_VAR(pmap_ncache_enter);
212 PMAP_STATS_VAR(pmap_ncache_enter_c);
213 PMAP_STATS_VAR(pmap_ncache_enter_oc);
214 PMAP_STATS_VAR(pmap_ncache_enter_cc);
215 PMAP_STATS_VAR(pmap_ncache_enter_coc);
216 PMAP_STATS_VAR(pmap_ncache_enter_nc);
217 PMAP_STATS_VAR(pmap_ncache_enter_cnc);
218 PMAP_STATS_VAR(pmap_ncache_remove);
219 PMAP_STATS_VAR(pmap_ncache_remove_c);
220 PMAP_STATS_VAR(pmap_ncache_remove_oc);
221 PMAP_STATS_VAR(pmap_ncache_remove_cc);
222 PMAP_STATS_VAR(pmap_ncache_remove_coc);
223 PMAP_STATS_VAR(pmap_ncache_remove_nc);
224 PMAP_STATS_VAR(pmap_nzero_page);
225 PMAP_STATS_VAR(pmap_nzero_page_c);
226 PMAP_STATS_VAR(pmap_nzero_page_oc);
227 PMAP_STATS_VAR(pmap_nzero_page_nc);
228 PMAP_STATS_VAR(pmap_nzero_page_area);
229 PMAP_STATS_VAR(pmap_nzero_page_area_c);
230 PMAP_STATS_VAR(pmap_nzero_page_area_oc);
231 PMAP_STATS_VAR(pmap_nzero_page_area_nc);
232 PMAP_STATS_VAR(pmap_nzero_page_idle);
233 PMAP_STATS_VAR(pmap_nzero_page_idle_c);
234 PMAP_STATS_VAR(pmap_nzero_page_idle_oc);
235 PMAP_STATS_VAR(pmap_nzero_page_idle_nc);
236 PMAP_STATS_VAR(pmap_ncopy_page);
237 PMAP_STATS_VAR(pmap_ncopy_page_c);
238 PMAP_STATS_VAR(pmap_ncopy_page_oc);
239 PMAP_STATS_VAR(pmap_ncopy_page_nc);
240 PMAP_STATS_VAR(pmap_ncopy_page_dc);
241 PMAP_STATS_VAR(pmap_ncopy_page_doc);
242 PMAP_STATS_VAR(pmap_ncopy_page_sc);
243 PMAP_STATS_VAR(pmap_ncopy_page_soc);
245 PMAP_STATS_VAR(pmap_nnew_thread);
246 PMAP_STATS_VAR(pmap_nnew_thread_oc);
248 static inline u_long dtlb_get_data(u_int tlb, u_int slot);
251 * Quick sort callout for comparing memory regions
253 static int mr_cmp(const void *a, const void *b);
254 static int om_cmp(const void *a, const void *b);
257 mr_cmp(const void *a, const void *b)
259 const struct ofw_mem_region *mra;
260 const struct ofw_mem_region *mrb;
264 if (mra->mr_start < mrb->mr_start)
266 else if (mra->mr_start > mrb->mr_start)
273 om_cmp(const void *a, const void *b)
275 const struct ofw_map *oma;
276 const struct ofw_map *omb;
280 if (oma->om_start < omb->om_start)
282 else if (oma->om_start > omb->om_start)
289 dtlb_get_data(u_int tlb, u_int slot)
294 slot = TLB_DAR_SLOT(tlb, slot);
296 * We read ASI_DTLB_DATA_ACCESS_REG twice back-to-back in order to
297 * work around errata of USIII and beyond.
300 (void)ldxa(slot, ASI_DTLB_DATA_ACCESS_REG);
301 data = ldxa(slot, ASI_DTLB_DATA_ACCESS_REG);
307 * Bootstrap the system enough to run with virtual memory.
310 pmap_bootstrap(u_int cpu_impl)
323 u_int dtlb_slots_avail;
332 * Set the kernel context.
336 colors = dcache_color_ignore != 0 ? 1 : DCACHE_COLORS;
339 * Find out what physical memory is available from the PROM and
340 * initialize the phys_avail array. This must be done before
341 * pmap_bootstrap_alloc is called.
343 if ((pmem = OF_finddevice("/memory")) == -1)
344 OF_panic("%s: finddevice /memory", __func__);
345 if ((sz = OF_getproplen(pmem, "available")) == -1)
346 OF_panic("%s: getproplen /memory/available", __func__);
347 if (sizeof(phys_avail) < sz)
348 OF_panic("%s: phys_avail too small", __func__);
349 if (sizeof(mra) < sz)
350 OF_panic("%s: mra too small", __func__);
352 if (OF_getprop(pmem, "available", mra, sz) == -1)
353 OF_panic("%s: getprop /memory/available", __func__);
355 CTR0(KTR_PMAP, "pmap_bootstrap: physical memory");
356 qsort(mra, sz, sizeof (*mra), mr_cmp);
358 getenv_quad("hw.physmem", &physmem);
359 physmem = btoc(physmem);
360 for (i = 0, j = 0; i < sz; i++, j += 2) {
361 CTR2(KTR_PMAP, "start=%#lx size=%#lx", mra[i].mr_start,
363 if (physmem != 0 && btoc(physsz + mra[i].mr_size) >= physmem) {
364 if (btoc(physsz) < physmem) {
365 phys_avail[j] = mra[i].mr_start;
366 phys_avail[j + 1] = mra[i].mr_start +
367 (ctob(physmem) - physsz);
368 physsz = ctob(physmem);
372 phys_avail[j] = mra[i].mr_start;
373 phys_avail[j + 1] = mra[i].mr_start + mra[i].mr_size;
374 physsz += mra[i].mr_size;
376 physmem = btoc(physsz);
379 * Calculate the size of kernel virtual memory, and the size and mask
380 * for the kernel TSB based on the phsyical memory size but limited
381 * by the amount of dTLB slots available for locked entries if we have
382 * to lock the TSB in the TLB (given that for spitfire-class CPUs all
383 * of the dt64 slots can hold locked entries but there is no large
384 * dTLB for unlocked ones, we don't use more than half of it for the
386 * Note that for reasons unknown OpenSolaris doesn't take advantage of
387 * ASI_ATOMIC_QUAD_LDD_PHYS on UltraSPARC-III. However, given that no
388 * public documentation is available for these, the latter just might
389 * not support it, yet.
391 if (cpu_impl == CPU_IMPL_SPARC64V ||
392 cpu_impl >= CPU_IMPL_ULTRASPARCIIIp) {
393 tsb_kernel_ldd_phys = 1;
394 virtsz = roundup(5 / 3 * physsz, PAGE_SIZE_4M <<
395 (PAGE_SHIFT - TTE_SHIFT));
397 dtlb_slots_avail = 0;
398 for (i = 0; i < dtlb_slots; i++) {
399 data = dtlb_get_data(cpu_impl ==
400 CPU_IMPL_ULTRASPARCIII ? TLB_DAR_T16 :
402 if ((data & (TD_V | TD_L)) != (TD_V | TD_L))
406 dtlb_slots_avail -= PCPU_PAGES;
408 if (cpu_impl >= CPU_IMPL_ULTRASPARCI &&
409 cpu_impl < CPU_IMPL_ULTRASPARCIII)
410 dtlb_slots_avail /= 2;
411 virtsz = roundup(physsz, PAGE_SIZE_4M <<
412 (PAGE_SHIFT - TTE_SHIFT));
413 virtsz = MIN(virtsz, (dtlb_slots_avail * PAGE_SIZE_4M) <<
414 (PAGE_SHIFT - TTE_SHIFT));
416 vm_max_kernel_address = VM_MIN_KERNEL_ADDRESS + virtsz;
417 tsb_kernel_size = virtsz >> (PAGE_SHIFT - TTE_SHIFT);
418 tsb_kernel_mask = (tsb_kernel_size >> TTE_SHIFT) - 1;
421 * Allocate the kernel TSB and lock it in the TLB if necessary.
423 pa = pmap_bootstrap_alloc(tsb_kernel_size, colors);
424 if (pa & PAGE_MASK_4M)
425 OF_panic("%s: TSB unaligned", __func__);
426 tsb_kernel_phys = pa;
427 if (tsb_kernel_ldd_phys == 0) {
429 (struct tte *)(VM_MIN_KERNEL_ADDRESS - tsb_kernel_size);
431 bzero(tsb_kernel, tsb_kernel_size);
434 (struct tte *)TLB_PHYS_TO_DIRECT(tsb_kernel_phys);
435 aszero(ASI_PHYS_USE_EC, tsb_kernel_phys, tsb_kernel_size);
439 * Allocate and map the dynamic per-CPU area for the BSP.
441 pa = pmap_bootstrap_alloc(DPCPU_SIZE, colors);
442 dpcpu0 = (void *)TLB_PHYS_TO_DIRECT(pa);
445 * Allocate and map the message buffer.
447 pa = pmap_bootstrap_alloc(msgbufsize, colors);
448 msgbufp = (struct msgbuf *)TLB_PHYS_TO_DIRECT(pa);
451 * Patch the TSB addresses and mask as well as the ASIs used to load
452 * it into the trap table.
455 #define LDDA_R_I_R(rd, imm_asi, rs1, rs2) \
456 (EIF_OP(IOP_LDST) | EIF_F3_RD(rd) | EIF_F3_OP3(INS3_LDDA) | \
457 EIF_F3_RS1(rs1) | EIF_F3_I(0) | EIF_F3_IMM_ASI(imm_asi) | \
459 #define OR_R_I_R(rd, imm13, rs1) \
460 (EIF_OP(IOP_MISC) | EIF_F3_RD(rd) | EIF_F3_OP3(INS2_OR) | \
461 EIF_F3_RS1(rs1) | EIF_F3_I(1) | EIF_IMM(imm13, 13))
462 #define SETHI(rd, imm22) \
463 (EIF_OP(IOP_FORM2) | EIF_F2_RD(rd) | EIF_F2_OP2(INS0_SETHI) | \
464 EIF_IMM((imm22) >> 10, 22))
465 #define WR_R_I(rd, imm13, rs1) \
466 (EIF_OP(IOP_MISC) | EIF_F3_RD(rd) | EIF_F3_OP3(INS2_WR) | \
467 EIF_F3_RS1(rs1) | EIF_F3_I(1) | EIF_IMM(imm13, 13))
469 #define PATCH_ASI(addr, asi) do { \
470 if (addr[0] != WR_R_I(IF_F3_RD(addr[0]), 0x0, \
471 IF_F3_RS1(addr[0]))) \
472 OF_panic("%s: patched instructions have changed", \
474 addr[0] |= EIF_IMM((asi), 13); \
478 #define PATCH_LDD(addr, asi) do { \
479 if (addr[0] != LDDA_R_I_R(IF_F3_RD(addr[0]), 0x0, \
480 IF_F3_RS1(addr[0]), IF_F3_RS2(addr[0]))) \
481 OF_panic("%s: patched instructions have changed", \
483 addr[0] |= EIF_F3_IMM_ASI(asi); \
487 #define PATCH_TSB(addr, val) do { \
488 if (addr[0] != SETHI(IF_F2_RD(addr[0]), 0x0) || \
489 addr[1] != OR_R_I_R(IF_F3_RD(addr[1]), 0x0, \
490 IF_F3_RS1(addr[1])) || \
491 addr[3] != SETHI(IF_F2_RD(addr[3]), 0x0)) \
492 OF_panic("%s: patched instructions have changed", \
494 addr[0] |= EIF_IMM((val) >> 42, 22); \
495 addr[1] |= EIF_IMM((val) >> 32, 10); \
496 addr[3] |= EIF_IMM((val) >> 10, 22); \
502 #define PATCH_TSB_MASK(addr, val) do { \
503 if (addr[0] != SETHI(IF_F2_RD(addr[0]), 0x0) || \
504 addr[1] != OR_R_I_R(IF_F3_RD(addr[1]), 0x0, \
505 IF_F3_RS1(addr[1]))) \
506 OF_panic("%s: patched instructions have changed", \
508 addr[0] |= EIF_IMM((val) >> 10, 22); \
509 addr[1] |= EIF_IMM((val), 10); \
514 if (tsb_kernel_ldd_phys == 0) {
516 ldd = ASI_NUCLEUS_QUAD_LDD;
517 off = (vm_offset_t)tsb_kernel;
519 asi = ASI_PHYS_USE_EC;
520 ldd = ASI_ATOMIC_QUAD_LDD_PHYS;
521 off = (vm_offset_t)tsb_kernel_phys;
523 PATCH_TSB(tl1_dmmu_miss_direct_patch_tsb_phys_1, tsb_kernel_phys);
524 PATCH_TSB(tl1_dmmu_miss_direct_patch_tsb_phys_end_1,
525 tsb_kernel_phys + tsb_kernel_size - 1);
526 PATCH_ASI(tl1_dmmu_miss_patch_asi_1, asi);
527 PATCH_LDD(tl1_dmmu_miss_patch_quad_ldd_1, ldd);
528 PATCH_TSB(tl1_dmmu_miss_patch_tsb_1, off);
529 PATCH_TSB(tl1_dmmu_miss_patch_tsb_2, off);
530 PATCH_TSB_MASK(tl1_dmmu_miss_patch_tsb_mask_1, tsb_kernel_mask);
531 PATCH_TSB_MASK(tl1_dmmu_miss_patch_tsb_mask_2, tsb_kernel_mask);
532 PATCH_ASI(tl1_dmmu_prot_patch_asi_1, asi);
533 PATCH_LDD(tl1_dmmu_prot_patch_quad_ldd_1, ldd);
534 PATCH_TSB(tl1_dmmu_prot_patch_tsb_1, off);
535 PATCH_TSB(tl1_dmmu_prot_patch_tsb_2, off);
536 PATCH_TSB_MASK(tl1_dmmu_prot_patch_tsb_mask_1, tsb_kernel_mask);
537 PATCH_TSB_MASK(tl1_dmmu_prot_patch_tsb_mask_2, tsb_kernel_mask);
538 PATCH_ASI(tl1_immu_miss_patch_asi_1, asi);
539 PATCH_LDD(tl1_immu_miss_patch_quad_ldd_1, ldd);
540 PATCH_TSB(tl1_immu_miss_patch_tsb_1, off);
541 PATCH_TSB(tl1_immu_miss_patch_tsb_2, off);
542 PATCH_TSB_MASK(tl1_immu_miss_patch_tsb_mask_1, tsb_kernel_mask);
543 PATCH_TSB_MASK(tl1_immu_miss_patch_tsb_mask_2, tsb_kernel_mask);
546 * Enter fake 8k pages for the 4MB kernel pages, so that
547 * pmap_kextract() will work for them.
549 for (i = 0; i < kernel_tlb_slots; i++) {
550 pa = kernel_tlbs[i].te_pa;
551 va = kernel_tlbs[i].te_va;
552 for (off = 0; off < PAGE_SIZE_4M; off += PAGE_SIZE) {
553 tp = tsb_kvtotte(va + off);
554 vpn = TV_VPN(va + off, TS_8K);
555 data = TD_V | TD_8K | TD_PA(pa + off) | TD_REF |
556 TD_SW | TD_CP | TD_CV | TD_P | TD_W;
557 pmap_bootstrap_set_tte(tp, vpn, data);
562 * Set the start and end of KVA. The kernel is loaded starting
563 * at the first available 4MB super page, so we advance to the
564 * end of the last one used for it.
566 virtual_avail = KERNBASE + kernel_tlb_slots * PAGE_SIZE_4M;
567 virtual_end = vm_max_kernel_address;
568 kernel_vm_end = vm_max_kernel_address;
571 * Allocate kva space for temporary mappings.
573 pmap_idle_map = virtual_avail;
574 virtual_avail += PAGE_SIZE * colors;
575 pmap_temp_map_1 = virtual_avail;
576 virtual_avail += PAGE_SIZE * colors;
577 pmap_temp_map_2 = virtual_avail;
578 virtual_avail += PAGE_SIZE * colors;
581 * Allocate a kernel stack with guard page for thread0 and map it
582 * into the kernel TSB. We must ensure that the virtual address is
583 * colored properly for corresponding CPUs, since we're allocating
584 * from phys_avail so the memory won't have an associated vm_page_t.
586 pa = pmap_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, colors);
588 virtual_avail += roundup(KSTACK_GUARD_PAGES, colors) * PAGE_SIZE;
589 kstack0 = virtual_avail;
590 virtual_avail += roundup(KSTACK_PAGES, colors) * PAGE_SIZE;
591 if (dcache_color_ignore == 0)
592 KASSERT(DCACHE_COLOR(kstack0) == DCACHE_COLOR(kstack0_phys),
593 ("pmap_bootstrap: kstack0 miscolored"));
594 for (i = 0; i < KSTACK_PAGES; i++) {
595 pa = kstack0_phys + i * PAGE_SIZE;
596 va = kstack0 + i * PAGE_SIZE;
597 tp = tsb_kvtotte(va);
598 vpn = TV_VPN(va, TS_8K);
599 data = TD_V | TD_8K | TD_PA(pa) | TD_REF | TD_SW | TD_CP |
601 pmap_bootstrap_set_tte(tp, vpn, data);
605 * Calculate the last available physical address.
607 for (i = 0; phys_avail[i + 2] != 0; i += 2)
609 Maxmem = sparc64_btop(phys_avail[i + 1]);
612 * Add the PROM mappings to the kernel TSB.
614 if ((vmem = OF_finddevice("/virtual-memory")) == -1)
615 OF_panic("%s: finddevice /virtual-memory", __func__);
616 if ((sz = OF_getproplen(vmem, "translations")) == -1)
617 OF_panic("%s: getproplen translations", __func__);
618 if (sizeof(translations) < sz)
619 OF_panic("%s: translations too small", __func__);
620 bzero(translations, sz);
621 if (OF_getprop(vmem, "translations", translations, sz) == -1)
622 OF_panic("%s: getprop /virtual-memory/translations",
624 sz /= sizeof(*translations);
625 translations_size = sz;
626 CTR0(KTR_PMAP, "pmap_bootstrap: translations");
627 qsort(translations, sz, sizeof (*translations), om_cmp);
628 for (i = 0; i < sz; i++) {
630 "translation: start=%#lx size=%#lx tte=%#lx",
631 translations[i].om_start, translations[i].om_size,
632 translations[i].om_tte);
633 if ((translations[i].om_tte & TD_V) == 0)
635 if (translations[i].om_start < VM_MIN_PROM_ADDRESS ||
636 translations[i].om_start > VM_MAX_PROM_ADDRESS)
638 for (off = 0; off < translations[i].om_size;
640 va = translations[i].om_start + off;
641 tp = tsb_kvtotte(va);
642 vpn = TV_VPN(va, TS_8K);
643 data = ((translations[i].om_tte &
644 ~((TD_SOFT2_MASK << TD_SOFT2_SHIFT) |
645 (cpu_impl >= CPU_IMPL_ULTRASPARCI &&
646 cpu_impl < CPU_IMPL_ULTRASPARCIII ?
647 (TD_DIAG_SF_MASK << TD_DIAG_SF_SHIFT) :
648 (TD_RSVD_CH_MASK << TD_RSVD_CH_SHIFT)) |
649 (TD_SOFT_MASK << TD_SOFT_SHIFT))) | TD_EXEC) +
651 pmap_bootstrap_set_tte(tp, vpn, data);
656 * Get the available physical memory ranges from /memory/reg. These
657 * are only used for kernel dumps, but it may not be wise to do PROM
658 * calls in that situation.
660 if ((sz = OF_getproplen(pmem, "reg")) == -1)
661 OF_panic("%s: getproplen /memory/reg", __func__);
662 if (sizeof(sparc64_memreg) < sz)
663 OF_panic("%s: sparc64_memreg too small", __func__);
664 if (OF_getprop(pmem, "reg", sparc64_memreg, sz) == -1)
665 OF_panic("%s: getprop /memory/reg", __func__);
666 sparc64_nmemreg = sz / sizeof(*sparc64_memreg);
669 * Initialize the kernel pmap (which is statically allocated).
673 for (i = 0; i < MAXCPU; i++)
674 pm->pm_context[i] = TLB_CTX_KERNEL;
675 CPU_FILL(&pm->pm_active);
678 * Initialize the global tte list lock, which is more commonly
679 * known as the pmap pv global lock.
681 rw_init(&tte_list_global_lock, "pmap pv global");
684 * Flush all non-locked TLB entries possibly left over by the
687 tlb_flush_nonlocked();
691 * Map the 4MB kernel TSB pages.
701 for (i = 0; i < tsb_kernel_size; i += PAGE_SIZE_4M) {
702 va = (vm_offset_t)tsb_kernel + i;
703 pa = tsb_kernel_phys + i;
704 data = TD_V | TD_4M | TD_PA(pa) | TD_L | TD_CP | TD_CV |
706 stxa(AA_DMMU_TAR, ASI_DMMU, TLB_TAR_VA(va) |
707 TLB_TAR_CTX(TLB_CTX_KERNEL));
708 stxa_sync(0, ASI_DTLB_DATA_IN_REG, data);
713 * Set the secondary context to be the kernel context (needed for FP block
714 * operations in the kernel).
720 stxa(AA_DMMU_SCXR, ASI_DMMU, (ldxa(AA_DMMU_SCXR, ASI_DMMU) &
721 TLB_CXR_PGSZ_MASK) | TLB_CTX_KERNEL);
726 * Allocate a physical page of memory directly from the phys_avail map.
727 * Can only be called from pmap_bootstrap before avail start and end are
731 pmap_bootstrap_alloc(vm_size_t size, uint32_t colors)
736 size = roundup(size, PAGE_SIZE * colors);
737 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
738 if (phys_avail[i + 1] - phys_avail[i] < size)
741 phys_avail[i] += size;
744 OF_panic("%s: no suitable region found", __func__);
748 * Set a TTE. This function is intended as a helper when tsb_kernel is
749 * direct-mapped but we haven't taken over the trap table, yet, as it's the
750 * case when we are taking advantage of ASI_ATOMIC_QUAD_LDD_PHYS to access
754 pmap_bootstrap_set_tte(struct tte *tp, u_long vpn, u_long data)
757 if (tsb_kernel_ldd_phys == 0) {
761 stxa((vm_paddr_t)tp + offsetof(struct tte, tte_vpn),
762 ASI_PHYS_USE_EC, vpn);
763 stxa((vm_paddr_t)tp + offsetof(struct tte, tte_data),
764 ASI_PHYS_USE_EC, data);
769 * Initialize a vm_page's machine-dependent fields.
772 pmap_page_init(vm_page_t m)
775 TAILQ_INIT(&m->md.tte_list);
776 m->md.color = DCACHE_COLOR(VM_PAGE_TO_PHYS(m));
782 * Initialize the pmap module.
792 for (i = 0; i < translations_size; i++) {
793 addr = translations[i].om_start;
794 size = translations[i].om_size;
795 if ((translations[i].om_tte & TD_V) == 0)
797 if (addr < VM_MIN_PROM_ADDRESS || addr > VM_MAX_PROM_ADDRESS)
799 result = vm_map_find(kernel_map, NULL, 0, &addr, size,
800 VMFS_NO_SPACE, VM_PROT_ALL, VM_PROT_ALL, MAP_NOFAULT);
801 if (result != KERN_SUCCESS || addr != translations[i].om_start)
802 panic("pmap_init: vm_map_find");
807 * Extract the physical page address associated with the given
808 * map/virtual_address pair.
811 pmap_extract(pmap_t pm, vm_offset_t va)
816 if (pm == kernel_pmap)
817 return (pmap_kextract(va));
819 tp = tsb_tte_lookup(pm, va);
823 pa = TTE_GET_PA(tp) | (va & TTE_GET_PAGE_MASK(tp));
829 * Atomically extract and hold the physical page with the given
830 * pmap and virtual address pair if that mapping permits the given
834 pmap_extract_and_hold(pmap_t pm, vm_offset_t va, vm_prot_t prot)
844 if (pm == kernel_pmap) {
845 if (va >= VM_MIN_DIRECT_ADDRESS) {
847 m = PHYS_TO_VM_PAGE(TLB_DIRECT_TO_PHYS(va));
848 (void)vm_page_pa_tryrelock(pm, TLB_DIRECT_TO_PHYS(va),
852 tp = tsb_kvtotte(va);
853 if ((tp->tte_data & TD_V) == 0)
857 tp = tsb_tte_lookup(pm, va);
858 if (tp != NULL && ((tp->tte_data & TD_SW) ||
859 (prot & VM_PROT_WRITE) == 0)) {
860 if (vm_page_pa_tryrelock(pm, TTE_GET_PA(tp), &pa))
862 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
871 * Extract the physical page address associated with the given kernel virtual
875 pmap_kextract(vm_offset_t va)
879 if (va >= VM_MIN_DIRECT_ADDRESS)
880 return (TLB_DIRECT_TO_PHYS(va));
881 tp = tsb_kvtotte(va);
882 if ((tp->tte_data & TD_V) == 0)
884 return (TTE_GET_PA(tp) | (va & TTE_GET_PAGE_MASK(tp)));
888 pmap_cache_enter(vm_page_t m, vm_offset_t va)
893 rw_assert(&tte_list_global_lock, RA_WLOCKED);
894 KASSERT((m->flags & PG_FICTITIOUS) == 0,
895 ("pmap_cache_enter: fake page"));
896 PMAP_STATS_INC(pmap_ncache_enter);
898 if (dcache_color_ignore != 0)
902 * Find the color for this virtual address and note the added mapping.
904 color = DCACHE_COLOR(va);
905 m->md.colors[color]++;
908 * If all existing mappings have the same color, the mapping is
911 if (m->md.color == color) {
912 KASSERT(m->md.colors[DCACHE_OTHER_COLOR(color)] == 0,
913 ("pmap_cache_enter: cacheable, mappings of other color"));
914 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
915 PMAP_STATS_INC(pmap_ncache_enter_c);
917 PMAP_STATS_INC(pmap_ncache_enter_oc);
922 * If there are no mappings of the other color, and the page still has
923 * the wrong color, this must be a new mapping. Change the color to
924 * match the new mapping, which is cacheable. We must flush the page
925 * from the cache now.
927 if (m->md.colors[DCACHE_OTHER_COLOR(color)] == 0) {
928 KASSERT(m->md.colors[color] == 1,
929 ("pmap_cache_enter: changing color, not new mapping"));
930 dcache_page_inval(VM_PAGE_TO_PHYS(m));
932 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
933 PMAP_STATS_INC(pmap_ncache_enter_cc);
935 PMAP_STATS_INC(pmap_ncache_enter_coc);
940 * If the mapping is already non-cacheable, just return.
942 if (m->md.color == -1) {
943 PMAP_STATS_INC(pmap_ncache_enter_nc);
947 PMAP_STATS_INC(pmap_ncache_enter_cnc);
950 * Mark all mappings as uncacheable, flush any lines with the other
951 * color out of the dcache, and set the color to none (-1).
953 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
954 atomic_clear_long(&tp->tte_data, TD_CV);
955 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
957 dcache_page_inval(VM_PAGE_TO_PHYS(m));
963 pmap_cache_remove(vm_page_t m, vm_offset_t va)
968 rw_assert(&tte_list_global_lock, RA_WLOCKED);
969 CTR3(KTR_PMAP, "pmap_cache_remove: m=%p va=%#lx c=%d", m, va,
970 m->md.colors[DCACHE_COLOR(va)]);
971 KASSERT((m->flags & PG_FICTITIOUS) == 0,
972 ("pmap_cache_remove: fake page"));
973 PMAP_STATS_INC(pmap_ncache_remove);
975 if (dcache_color_ignore != 0)
978 KASSERT(m->md.colors[DCACHE_COLOR(va)] > 0,
979 ("pmap_cache_remove: no mappings %d <= 0",
980 m->md.colors[DCACHE_COLOR(va)]));
983 * Find the color for this virtual address and note the removal of
986 color = DCACHE_COLOR(va);
987 m->md.colors[color]--;
990 * If the page is cacheable, just return and keep the same color, even
991 * if there are no longer any mappings.
993 if (m->md.color != -1) {
994 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
995 PMAP_STATS_INC(pmap_ncache_remove_c);
997 PMAP_STATS_INC(pmap_ncache_remove_oc);
1001 KASSERT(m->md.colors[DCACHE_OTHER_COLOR(color)] != 0,
1002 ("pmap_cache_remove: uncacheable, no mappings of other color"));
1005 * If the page is not cacheable (color is -1), and the number of
1006 * mappings for this color is not zero, just return. There are
1007 * mappings of the other color still, so remain non-cacheable.
1009 if (m->md.colors[color] != 0) {
1010 PMAP_STATS_INC(pmap_ncache_remove_nc);
1015 * The number of mappings for this color is now zero. Recache the
1016 * other colored mappings, and change the page color to the other
1017 * color. There should be no lines in the data cache for this page,
1018 * so flushing should not be needed.
1020 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1021 atomic_set_long(&tp->tte_data, TD_CV);
1022 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
1024 m->md.color = DCACHE_OTHER_COLOR(color);
1026 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
1027 PMAP_STATS_INC(pmap_ncache_remove_cc);
1029 PMAP_STATS_INC(pmap_ncache_remove_coc);
1033 * Map a wired page into kernel virtual address space.
1036 pmap_kenter(vm_offset_t va, vm_page_t m)
1043 rw_assert(&tte_list_global_lock, RA_WLOCKED);
1044 PMAP_STATS_INC(pmap_nkenter);
1045 tp = tsb_kvtotte(va);
1046 CTR4(KTR_PMAP, "pmap_kenter: va=%#lx pa=%#lx tp=%p data=%#lx",
1047 va, VM_PAGE_TO_PHYS(m), tp, tp->tte_data);
1048 if (DCACHE_COLOR(VM_PAGE_TO_PHYS(m)) != DCACHE_COLOR(va)) {
1050 "pmap_kenter: off color va=%#lx pa=%#lx o=%p ot=%d pi=%#lx",
1051 va, VM_PAGE_TO_PHYS(m), m->object,
1052 m->object ? m->object->type : -1,
1054 PMAP_STATS_INC(pmap_nkenter_oc);
1056 if ((tp->tte_data & TD_V) != 0) {
1057 om = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
1058 ova = TTE_GET_VA(tp);
1059 if (m == om && va == ova) {
1060 PMAP_STATS_INC(pmap_nkenter_stupid);
1063 TAILQ_REMOVE(&om->md.tte_list, tp, tte_link);
1064 pmap_cache_remove(om, ova);
1066 tlb_page_demap(kernel_pmap, ova);
1068 data = TD_V | TD_8K | VM_PAGE_TO_PHYS(m) | TD_REF | TD_SW | TD_CP |
1070 if (pmap_cache_enter(m, va) != 0)
1072 tp->tte_vpn = TV_VPN(va, TS_8K);
1073 tp->tte_data = data;
1074 TAILQ_INSERT_TAIL(&m->md.tte_list, tp, tte_link);
1078 * Map a wired page into kernel virtual address space. This additionally
1079 * takes a flag argument which is or'ed to the TTE data. This is used by
1080 * sparc64_bus_mem_map().
1081 * NOTE: if the mapping is non-cacheable, it's the caller's responsibility
1082 * to flush entries that might still be in the cache, if applicable.
1085 pmap_kenter_flags(vm_offset_t va, vm_paddr_t pa, u_long flags)
1089 tp = tsb_kvtotte(va);
1090 CTR4(KTR_PMAP, "pmap_kenter_flags: va=%#lx pa=%#lx tp=%p data=%#lx",
1091 va, pa, tp, tp->tte_data);
1092 tp->tte_vpn = TV_VPN(va, TS_8K);
1093 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_REF | TD_P | flags;
1097 * Remove a wired page from kernel virtual address space.
1100 pmap_kremove(vm_offset_t va)
1105 rw_assert(&tte_list_global_lock, RA_WLOCKED);
1106 PMAP_STATS_INC(pmap_nkremove);
1107 tp = tsb_kvtotte(va);
1108 CTR3(KTR_PMAP, "pmap_kremove: va=%#lx tp=%p data=%#lx", va, tp,
1110 if ((tp->tte_data & TD_V) == 0)
1112 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
1113 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
1114 pmap_cache_remove(m, va);
1119 * Inverse of pmap_kenter_flags, used by bus_space_unmap().
1122 pmap_kremove_flags(vm_offset_t va)
1126 tp = tsb_kvtotte(va);
1127 CTR3(KTR_PMAP, "pmap_kremove_flags: va=%#lx tp=%p data=%#lx", va, tp,
1133 * Map a range of physical addresses into kernel virtual address space.
1135 * The value passed in *virt is a suggested virtual address for the mapping.
1136 * Architectures which can support a direct-mapped physical to virtual region
1137 * can return the appropriate address within that region, leaving '*virt'
1141 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1144 return (TLB_PHYS_TO_DIRECT(start));
1148 * Map a list of wired pages into kernel virtual address space. This is
1149 * intended for temporary mappings which do not need page modification or
1150 * references recorded. Existing mappings in the region are overwritten.
1153 pmap_qenter(vm_offset_t sva, vm_page_t *m, int count)
1157 PMAP_STATS_INC(pmap_nqenter);
1159 rw_wlock(&tte_list_global_lock);
1160 while (count-- > 0) {
1161 pmap_kenter(va, *m);
1165 rw_wunlock(&tte_list_global_lock);
1166 tlb_range_demap(kernel_pmap, sva, va);
1170 * Remove page mappings from kernel virtual address space. Intended for
1171 * temporary mappings entered by pmap_qenter.
1174 pmap_qremove(vm_offset_t sva, int count)
1178 PMAP_STATS_INC(pmap_nqremove);
1180 rw_wlock(&tte_list_global_lock);
1181 while (count-- > 0) {
1185 rw_wunlock(&tte_list_global_lock);
1186 tlb_range_demap(kernel_pmap, sva, va);
1190 * Initialize the pmap associated with process 0.
1193 pmap_pinit0(pmap_t pm)
1198 for (i = 0; i < MAXCPU; i++)
1199 pm->pm_context[i] = TLB_CTX_KERNEL;
1200 CPU_ZERO(&pm->pm_active);
1202 pm->pm_tsb_obj = NULL;
1203 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1207 * Initialize a preallocated and zeroed pmap structure, such as one in a
1208 * vmspace structure.
1211 pmap_pinit(pmap_t pm)
1213 vm_page_t ma[TSB_PAGES];
1220 * Allocate KVA space for the TSB.
1222 if (pm->pm_tsb == NULL) {
1223 pm->pm_tsb = (struct tte *)kmem_alloc_nofault(kernel_map,
1225 if (pm->pm_tsb == NULL) {
1226 PMAP_LOCK_DESTROY(pm);
1232 * Allocate an object for it.
1234 if (pm->pm_tsb_obj == NULL)
1235 pm->pm_tsb_obj = vm_object_allocate(OBJT_PHYS, TSB_PAGES);
1237 for (i = 0; i < MAXCPU; i++)
1238 pm->pm_context[i] = -1;
1239 CPU_ZERO(&pm->pm_active);
1241 VM_OBJECT_LOCK(pm->pm_tsb_obj);
1242 for (i = 0; i < TSB_PAGES; i++) {
1243 m = vm_page_grab(pm->pm_tsb_obj, i, VM_ALLOC_NOBUSY |
1244 VM_ALLOC_RETRY | VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1245 m->valid = VM_PAGE_BITS_ALL;
1249 VM_OBJECT_UNLOCK(pm->pm_tsb_obj);
1250 pmap_qenter((vm_offset_t)pm->pm_tsb, ma, TSB_PAGES);
1252 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1257 * Release any resources held by the given physical map.
1258 * Called when a pmap initialized by pmap_pinit is being released.
1259 * Should only be called if the map contains no valid mappings.
1262 pmap_release(pmap_t pm)
1270 CTR2(KTR_PMAP, "pmap_release: ctx=%#x tsb=%p",
1271 pm->pm_context[curcpu], pm->pm_tsb);
1272 KASSERT(pmap_resident_count(pm) == 0,
1273 ("pmap_release: resident pages %ld != 0",
1274 pmap_resident_count(pm)));
1277 * After the pmap was freed, it might be reallocated to a new process.
1278 * When switching, this might lead us to wrongly assume that we need
1279 * not switch contexts because old and new pmap pointer are equal.
1280 * Therefore, make sure that this pmap is not referenced by any PCPU
1281 * pointer any more. This could happen in two cases:
1282 * - A process that referenced the pmap is currently exiting on a CPU.
1283 * However, it is guaranteed to not switch in any more after setting
1284 * its state to PRS_ZOMBIE.
1285 * - A process that referenced this pmap ran on a CPU, but we switched
1286 * to a kernel thread, leaving the pmap pointer unchanged.
1290 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu)
1291 atomic_cmpset_rel_ptr((uintptr_t *)&pc->pc_pmap,
1292 (uintptr_t)pm, (uintptr_t)NULL);
1296 if (PCPU_GET(pmap) == pm)
1297 PCPU_SET(pmap, NULL);
1301 pmap_qremove((vm_offset_t)pm->pm_tsb, TSB_PAGES);
1302 obj = pm->pm_tsb_obj;
1303 VM_OBJECT_LOCK(obj);
1304 KASSERT(obj->ref_count == 1, ("pmap_release: tsbobj ref count != 1"));
1305 while (!TAILQ_EMPTY(&obj->memq)) {
1306 m = TAILQ_FIRST(&obj->memq);
1309 atomic_subtract_int(&cnt.v_wire_count, 1);
1310 vm_page_free_zero(m);
1312 VM_OBJECT_UNLOCK(obj);
1313 PMAP_LOCK_DESTROY(pm);
1317 * Grow the number of kernel page table entries. Unneeded.
1320 pmap_growkernel(vm_offset_t addr)
1323 panic("pmap_growkernel: can't grow kernel");
1327 pmap_remove_tte(struct pmap *pm, struct pmap *pm2, struct tte *tp,
1333 rw_assert(&tte_list_global_lock, RA_WLOCKED);
1334 data = atomic_readandclear_long(&tp->tte_data);
1335 if ((data & TD_FAKE) == 0) {
1336 m = PHYS_TO_VM_PAGE(TD_PA(data));
1337 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
1338 if ((data & TD_WIRED) != 0)
1339 pm->pm_stats.wired_count--;
1340 if ((data & TD_PV) != 0) {
1341 if ((data & TD_W) != 0)
1343 if ((data & TD_REF) != 0)
1344 vm_page_aflag_set(m, PGA_REFERENCED);
1345 if (TAILQ_EMPTY(&m->md.tte_list))
1346 vm_page_aflag_clear(m, PGA_WRITEABLE);
1347 pm->pm_stats.resident_count--;
1349 pmap_cache_remove(m, va);
1352 if (PMAP_REMOVE_DONE(pm))
1358 * Remove the given range of addresses from the specified map.
1361 pmap_remove(pmap_t pm, vm_offset_t start, vm_offset_t end)
1366 CTR3(KTR_PMAP, "pmap_remove: ctx=%#lx start=%#lx end=%#lx",
1367 pm->pm_context[curcpu], start, end);
1368 if (PMAP_REMOVE_DONE(pm))
1370 rw_wlock(&tte_list_global_lock);
1372 if (end - start > PMAP_TSB_THRESH) {
1373 tsb_foreach(pm, NULL, start, end, pmap_remove_tte);
1374 tlb_context_demap(pm);
1376 for (va = start; va < end; va += PAGE_SIZE)
1377 if ((tp = tsb_tte_lookup(pm, va)) != NULL &&
1378 !pmap_remove_tte(pm, NULL, tp, va))
1380 tlb_range_demap(pm, start, end - 1);
1383 rw_wunlock(&tte_list_global_lock);
1387 pmap_remove_all(vm_page_t m)
1394 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1395 ("pmap_remove_all: page %p is not managed", m));
1396 rw_wlock(&tte_list_global_lock);
1397 for (tp = TAILQ_FIRST(&m->md.tte_list); tp != NULL; tp = tpn) {
1398 tpn = TAILQ_NEXT(tp, tte_link);
1399 if ((tp->tte_data & TD_PV) == 0)
1401 pm = TTE_GET_PMAP(tp);
1402 va = TTE_GET_VA(tp);
1404 if ((tp->tte_data & TD_WIRED) != 0)
1405 pm->pm_stats.wired_count--;
1406 if ((tp->tte_data & TD_REF) != 0)
1407 vm_page_aflag_set(m, PGA_REFERENCED);
1408 if ((tp->tte_data & TD_W) != 0)
1410 tp->tte_data &= ~TD_V;
1411 tlb_page_demap(pm, va);
1412 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
1413 pm->pm_stats.resident_count--;
1414 pmap_cache_remove(m, va);
1418 vm_page_aflag_clear(m, PGA_WRITEABLE);
1419 rw_wunlock(&tte_list_global_lock);
1423 pmap_protect_tte(struct pmap *pm, struct pmap *pm2, struct tte *tp,
1429 PMAP_LOCK_ASSERT(pm, MA_OWNED);
1430 data = atomic_clear_long(&tp->tte_data, TD_SW | TD_W);
1431 if ((data & (TD_PV | TD_W)) == (TD_PV | TD_W)) {
1432 m = PHYS_TO_VM_PAGE(TD_PA(data));
1439 * Set the physical protection on the specified range of this map as requested.
1442 pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
1447 CTR4(KTR_PMAP, "pmap_protect: ctx=%#lx sva=%#lx eva=%#lx prot=%#lx",
1448 pm->pm_context[curcpu], sva, eva, prot);
1450 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1451 pmap_remove(pm, sva, eva);
1455 if (prot & VM_PROT_WRITE)
1459 if (eva - sva > PMAP_TSB_THRESH) {
1460 tsb_foreach(pm, NULL, sva, eva, pmap_protect_tte);
1461 tlb_context_demap(pm);
1463 for (va = sva; va < eva; va += PAGE_SIZE)
1464 if ((tp = tsb_tte_lookup(pm, va)) != NULL)
1465 pmap_protect_tte(pm, NULL, tp, va);
1466 tlb_range_demap(pm, sva, eva - 1);
1472 * Map the given physical page at the specified virtual address in the
1473 * target pmap with the protection requested. If specified the page
1474 * will be wired down.
1477 pmap_enter(pmap_t pm, vm_offset_t va, vm_prot_t access, vm_page_t m,
1478 vm_prot_t prot, boolean_t wired)
1481 rw_wlock(&tte_list_global_lock);
1483 pmap_enter_locked(pm, va, m, prot, wired);
1484 rw_wunlock(&tte_list_global_lock);
1489 * Map the given physical page at the specified virtual address in the
1490 * target pmap with the protection requested. If specified the page
1491 * will be wired down.
1493 * The page queues and pmap must be locked.
1496 pmap_enter_locked(pmap_t pm, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1504 rw_assert(&tte_list_global_lock, RA_WLOCKED);
1505 PMAP_LOCK_ASSERT(pm, MA_OWNED);
1506 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 ||
1507 VM_OBJECT_LOCKED(m->object),
1508 ("pmap_enter_locked: page %p is not busy", m));
1509 PMAP_STATS_INC(pmap_nenter);
1510 pa = VM_PAGE_TO_PHYS(m);
1513 * If this is a fake page from the device_pager, but it covers actual
1514 * physical memory, convert to the real backing page.
1516 if ((m->flags & PG_FICTITIOUS) != 0) {
1517 real = vm_phys_paddr_to_vm_page(pa);
1523 "pmap_enter_locked: ctx=%p m=%p va=%#lx pa=%#lx prot=%#x wired=%d",
1524 pm->pm_context[curcpu], m, va, pa, prot, wired);
1527 * If there is an existing mapping, and the physical address has not
1528 * changed, must be protection or wiring change.
1530 if ((tp = tsb_tte_lookup(pm, va)) != NULL && TTE_GET_PA(tp) == pa) {
1531 CTR0(KTR_PMAP, "pmap_enter_locked: update");
1532 PMAP_STATS_INC(pmap_nenter_update);
1535 * Wiring change, just update stats.
1538 if ((tp->tte_data & TD_WIRED) == 0) {
1539 tp->tte_data |= TD_WIRED;
1540 pm->pm_stats.wired_count++;
1543 if ((tp->tte_data & TD_WIRED) != 0) {
1544 tp->tte_data &= ~TD_WIRED;
1545 pm->pm_stats.wired_count--;
1550 * Save the old bits and clear the ones we're interested in.
1552 data = tp->tte_data;
1553 tp->tte_data &= ~(TD_EXEC | TD_SW | TD_W);
1556 * If we're turning off write permissions, sense modify status.
1558 if ((prot & VM_PROT_WRITE) != 0) {
1559 tp->tte_data |= TD_SW;
1561 tp->tte_data |= TD_W;
1562 if ((m->oflags & VPO_UNMANAGED) == 0)
1563 vm_page_aflag_set(m, PGA_WRITEABLE);
1564 } else if ((data & TD_W) != 0)
1568 * If we're turning on execute permissions, flush the icache.
1570 if ((prot & VM_PROT_EXECUTE) != 0) {
1571 if ((data & TD_EXEC) == 0)
1572 icache_page_inval(pa);
1573 tp->tte_data |= TD_EXEC;
1577 * Delete the old mapping.
1579 tlb_page_demap(pm, TTE_GET_VA(tp));
1582 * If there is an existing mapping, but its for a different
1583 * physical address, delete the old mapping.
1586 CTR0(KTR_PMAP, "pmap_enter_locked: replace");
1587 PMAP_STATS_INC(pmap_nenter_replace);
1588 pmap_remove_tte(pm, NULL, tp, va);
1589 tlb_page_demap(pm, va);
1591 CTR0(KTR_PMAP, "pmap_enter_locked: new");
1592 PMAP_STATS_INC(pmap_nenter_new);
1596 * Now set up the data and install the new mapping.
1598 data = TD_V | TD_8K | TD_PA(pa);
1599 if (pm == kernel_pmap)
1601 if ((prot & VM_PROT_WRITE) != 0) {
1603 if ((m->oflags & VPO_UNMANAGED) == 0)
1604 vm_page_aflag_set(m, PGA_WRITEABLE);
1606 if (prot & VM_PROT_EXECUTE) {
1608 icache_page_inval(pa);
1612 * If its wired update stats. We also don't need reference or
1613 * modify tracking for wired mappings, so set the bits now.
1616 pm->pm_stats.wired_count++;
1617 data |= TD_REF | TD_WIRED;
1618 if ((prot & VM_PROT_WRITE) != 0)
1622 tsb_tte_enter(pm, m, va, TS_8K, data);
1627 * Maps a sequence of resident pages belonging to the same object.
1628 * The sequence begins with the given page m_start. This page is
1629 * mapped at the given virtual address start. Each subsequent page is
1630 * mapped at a virtual address that is offset from start by the same
1631 * amount as the page is offset from m_start within the object. The
1632 * last page in the sequence is the page with the largest offset from
1633 * m_start that can be mapped at a virtual address less than the given
1634 * virtual address end. Not every virtual page between start and end
1635 * is mapped; only those for which a resident page exists with the
1636 * corresponding offset from m_start are mapped.
1639 pmap_enter_object(pmap_t pm, vm_offset_t start, vm_offset_t end,
1640 vm_page_t m_start, vm_prot_t prot)
1643 vm_pindex_t diff, psize;
1645 psize = atop(end - start);
1647 rw_wlock(&tte_list_global_lock);
1649 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1650 pmap_enter_locked(pm, start + ptoa(diff), m, prot &
1651 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1652 m = TAILQ_NEXT(m, listq);
1654 rw_wunlock(&tte_list_global_lock);
1659 pmap_enter_quick(pmap_t pm, vm_offset_t va, vm_page_t m, vm_prot_t prot)
1662 rw_wlock(&tte_list_global_lock);
1664 pmap_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1666 rw_wunlock(&tte_list_global_lock);
1671 pmap_object_init_pt(pmap_t pm, vm_offset_t addr, vm_object_t object,
1672 vm_pindex_t pindex, vm_size_t size)
1675 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED);
1676 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
1677 ("pmap_object_init_pt: non-device object"));
1681 * Change the wiring attribute for a map/virtual-address pair.
1682 * The mapping must already exist in the pmap.
1685 pmap_change_wiring(pmap_t pm, vm_offset_t va, boolean_t wired)
1691 if ((tp = tsb_tte_lookup(pm, va)) != NULL) {
1693 data = atomic_set_long(&tp->tte_data, TD_WIRED);
1694 if ((data & TD_WIRED) == 0)
1695 pm->pm_stats.wired_count++;
1697 data = atomic_clear_long(&tp->tte_data, TD_WIRED);
1698 if ((data & TD_WIRED) != 0)
1699 pm->pm_stats.wired_count--;
1706 pmap_copy_tte(pmap_t src_pmap, pmap_t dst_pmap, struct tte *tp,
1712 if ((tp->tte_data & TD_FAKE) != 0)
1714 if (tsb_tte_lookup(dst_pmap, va) == NULL) {
1715 data = tp->tte_data &
1716 ~(TD_PV | TD_REF | TD_SW | TD_CV | TD_W);
1717 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
1718 tsb_tte_enter(dst_pmap, m, va, TS_8K, data);
1724 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
1725 vm_size_t len, vm_offset_t src_addr)
1730 if (dst_addr != src_addr)
1732 rw_wlock(&tte_list_global_lock);
1733 if (dst_pmap < src_pmap) {
1734 PMAP_LOCK(dst_pmap);
1735 PMAP_LOCK(src_pmap);
1737 PMAP_LOCK(src_pmap);
1738 PMAP_LOCK(dst_pmap);
1740 if (len > PMAP_TSB_THRESH) {
1741 tsb_foreach(src_pmap, dst_pmap, src_addr, src_addr + len,
1743 tlb_context_demap(dst_pmap);
1745 for (va = src_addr; va < src_addr + len; va += PAGE_SIZE)
1746 if ((tp = tsb_tte_lookup(src_pmap, va)) != NULL)
1747 pmap_copy_tte(src_pmap, dst_pmap, tp, va);
1748 tlb_range_demap(dst_pmap, src_addr, src_addr + len - 1);
1750 rw_wunlock(&tte_list_global_lock);
1751 PMAP_UNLOCK(src_pmap);
1752 PMAP_UNLOCK(dst_pmap);
1756 pmap_zero_page(vm_page_t m)
1762 KASSERT((m->flags & PG_FICTITIOUS) == 0,
1763 ("pmap_zero_page: fake page"));
1764 PMAP_STATS_INC(pmap_nzero_page);
1765 pa = VM_PAGE_TO_PHYS(m);
1766 if (dcache_color_ignore != 0 || m->md.color == DCACHE_COLOR(pa)) {
1767 PMAP_STATS_INC(pmap_nzero_page_c);
1768 va = TLB_PHYS_TO_DIRECT(pa);
1769 cpu_block_zero((void *)va, PAGE_SIZE);
1770 } else if (m->md.color == -1) {
1771 PMAP_STATS_INC(pmap_nzero_page_nc);
1772 aszero(ASI_PHYS_USE_EC, pa, PAGE_SIZE);
1774 PMAP_STATS_INC(pmap_nzero_page_oc);
1775 PMAP_LOCK(kernel_pmap);
1776 va = pmap_temp_map_1 + (m->md.color * PAGE_SIZE);
1777 tp = tsb_kvtotte(va);
1778 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_CP | TD_CV | TD_W;
1779 tp->tte_vpn = TV_VPN(va, TS_8K);
1780 cpu_block_zero((void *)va, PAGE_SIZE);
1781 tlb_page_demap(kernel_pmap, va);
1782 PMAP_UNLOCK(kernel_pmap);
1787 pmap_zero_page_area(vm_page_t m, int off, int size)
1793 KASSERT((m->flags & PG_FICTITIOUS) == 0,
1794 ("pmap_zero_page_area: fake page"));
1795 KASSERT(off + size <= PAGE_SIZE, ("pmap_zero_page_area: bad off/size"));
1796 PMAP_STATS_INC(pmap_nzero_page_area);
1797 pa = VM_PAGE_TO_PHYS(m);
1798 if (dcache_color_ignore != 0 || m->md.color == DCACHE_COLOR(pa)) {
1799 PMAP_STATS_INC(pmap_nzero_page_area_c);
1800 va = TLB_PHYS_TO_DIRECT(pa);
1801 bzero((void *)(va + off), size);
1802 } else if (m->md.color == -1) {
1803 PMAP_STATS_INC(pmap_nzero_page_area_nc);
1804 aszero(ASI_PHYS_USE_EC, pa + off, size);
1806 PMAP_STATS_INC(pmap_nzero_page_area_oc);
1807 PMAP_LOCK(kernel_pmap);
1808 va = pmap_temp_map_1 + (m->md.color * PAGE_SIZE);
1809 tp = tsb_kvtotte(va);
1810 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_CP | TD_CV | TD_W;
1811 tp->tte_vpn = TV_VPN(va, TS_8K);
1812 bzero((void *)(va + off), size);
1813 tlb_page_demap(kernel_pmap, va);
1814 PMAP_UNLOCK(kernel_pmap);
1819 pmap_zero_page_idle(vm_page_t m)
1825 KASSERT((m->flags & PG_FICTITIOUS) == 0,
1826 ("pmap_zero_page_idle: fake page"));
1827 PMAP_STATS_INC(pmap_nzero_page_idle);
1828 pa = VM_PAGE_TO_PHYS(m);
1829 if (dcache_color_ignore != 0 || m->md.color == DCACHE_COLOR(pa)) {
1830 PMAP_STATS_INC(pmap_nzero_page_idle_c);
1831 va = TLB_PHYS_TO_DIRECT(pa);
1832 cpu_block_zero((void *)va, PAGE_SIZE);
1833 } else if (m->md.color == -1) {
1834 PMAP_STATS_INC(pmap_nzero_page_idle_nc);
1835 aszero(ASI_PHYS_USE_EC, pa, PAGE_SIZE);
1837 PMAP_STATS_INC(pmap_nzero_page_idle_oc);
1838 va = pmap_idle_map + (m->md.color * PAGE_SIZE);
1839 tp = tsb_kvtotte(va);
1840 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_CP | TD_CV | TD_W;
1841 tp->tte_vpn = TV_VPN(va, TS_8K);
1842 cpu_block_zero((void *)va, PAGE_SIZE);
1843 tlb_page_demap(kernel_pmap, va);
1848 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
1856 KASSERT((mdst->flags & PG_FICTITIOUS) == 0,
1857 ("pmap_copy_page: fake dst page"));
1858 KASSERT((msrc->flags & PG_FICTITIOUS) == 0,
1859 ("pmap_copy_page: fake src page"));
1860 PMAP_STATS_INC(pmap_ncopy_page);
1861 pdst = VM_PAGE_TO_PHYS(mdst);
1862 psrc = VM_PAGE_TO_PHYS(msrc);
1863 if (dcache_color_ignore != 0 ||
1864 (msrc->md.color == DCACHE_COLOR(psrc) &&
1865 mdst->md.color == DCACHE_COLOR(pdst))) {
1866 PMAP_STATS_INC(pmap_ncopy_page_c);
1867 vdst = TLB_PHYS_TO_DIRECT(pdst);
1868 vsrc = TLB_PHYS_TO_DIRECT(psrc);
1869 cpu_block_copy((void *)vsrc, (void *)vdst, PAGE_SIZE);
1870 } else if (msrc->md.color == -1 && mdst->md.color == -1) {
1871 PMAP_STATS_INC(pmap_ncopy_page_nc);
1872 ascopy(ASI_PHYS_USE_EC, psrc, pdst, PAGE_SIZE);
1873 } else if (msrc->md.color == -1) {
1874 if (mdst->md.color == DCACHE_COLOR(pdst)) {
1875 PMAP_STATS_INC(pmap_ncopy_page_dc);
1876 vdst = TLB_PHYS_TO_DIRECT(pdst);
1877 ascopyfrom(ASI_PHYS_USE_EC, psrc, (void *)vdst,
1880 PMAP_STATS_INC(pmap_ncopy_page_doc);
1881 PMAP_LOCK(kernel_pmap);
1882 vdst = pmap_temp_map_1 + (mdst->md.color * PAGE_SIZE);
1883 tp = tsb_kvtotte(vdst);
1885 TD_V | TD_8K | TD_PA(pdst) | TD_CP | TD_CV | TD_W;
1886 tp->tte_vpn = TV_VPN(vdst, TS_8K);
1887 ascopyfrom(ASI_PHYS_USE_EC, psrc, (void *)vdst,
1889 tlb_page_demap(kernel_pmap, vdst);
1890 PMAP_UNLOCK(kernel_pmap);
1892 } else if (mdst->md.color == -1) {
1893 if (msrc->md.color == DCACHE_COLOR(psrc)) {
1894 PMAP_STATS_INC(pmap_ncopy_page_sc);
1895 vsrc = TLB_PHYS_TO_DIRECT(psrc);
1896 ascopyto((void *)vsrc, ASI_PHYS_USE_EC, pdst,
1899 PMAP_STATS_INC(pmap_ncopy_page_soc);
1900 PMAP_LOCK(kernel_pmap);
1901 vsrc = pmap_temp_map_1 + (msrc->md.color * PAGE_SIZE);
1902 tp = tsb_kvtotte(vsrc);
1904 TD_V | TD_8K | TD_PA(psrc) | TD_CP | TD_CV | TD_W;
1905 tp->tte_vpn = TV_VPN(vsrc, TS_8K);
1906 ascopyto((void *)vsrc, ASI_PHYS_USE_EC, pdst,
1908 tlb_page_demap(kernel_pmap, vsrc);
1909 PMAP_UNLOCK(kernel_pmap);
1912 PMAP_STATS_INC(pmap_ncopy_page_oc);
1913 PMAP_LOCK(kernel_pmap);
1914 vdst = pmap_temp_map_1 + (mdst->md.color * PAGE_SIZE);
1915 tp = tsb_kvtotte(vdst);
1917 TD_V | TD_8K | TD_PA(pdst) | TD_CP | TD_CV | TD_W;
1918 tp->tte_vpn = TV_VPN(vdst, TS_8K);
1919 vsrc = pmap_temp_map_2 + (msrc->md.color * PAGE_SIZE);
1920 tp = tsb_kvtotte(vsrc);
1922 TD_V | TD_8K | TD_PA(psrc) | TD_CP | TD_CV | TD_W;
1923 tp->tte_vpn = TV_VPN(vsrc, TS_8K);
1924 cpu_block_copy((void *)vsrc, (void *)vdst, PAGE_SIZE);
1925 tlb_page_demap(kernel_pmap, vdst);
1926 tlb_page_demap(kernel_pmap, vsrc);
1927 PMAP_UNLOCK(kernel_pmap);
1931 int unmapped_buf_allowed;
1934 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
1935 vm_offset_t b_offset, int xfersize)
1938 panic("pmap_copy_pages: not implemented");
1942 * Returns true if the pmap's pv is one of the first
1943 * 16 pvs linked to from this page. This count may
1944 * be changed upwards or downwards in the future; it
1945 * is only necessary that true be returned for a small
1946 * subset of pmaps for proper page aging.
1949 pmap_page_exists_quick(pmap_t pm, vm_page_t m)
1955 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1956 ("pmap_page_exists_quick: page %p is not managed", m));
1959 rw_wlock(&tte_list_global_lock);
1960 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1961 if ((tp->tte_data & TD_PV) == 0)
1963 if (TTE_GET_PMAP(tp) == pm) {
1970 rw_wunlock(&tte_list_global_lock);
1975 * Return the number of managed mappings to the given physical page
1979 pmap_page_wired_mappings(vm_page_t m)
1985 if ((m->oflags & VPO_UNMANAGED) != 0)
1987 rw_wlock(&tte_list_global_lock);
1988 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link)
1989 if ((tp->tte_data & (TD_PV | TD_WIRED)) == (TD_PV | TD_WIRED))
1991 rw_wunlock(&tte_list_global_lock);
1996 * Remove all pages from specified address space, this aids process exit
1997 * speeds. This is much faster than pmap_remove in the case of running down
1998 * an entire address space. Only works for the current pmap.
2001 pmap_remove_pages(pmap_t pm)
2007 * Returns TRUE if the given page has a managed mapping.
2010 pmap_page_is_mapped(vm_page_t m)
2016 if ((m->oflags & VPO_UNMANAGED) != 0)
2018 rw_wlock(&tte_list_global_lock);
2019 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link)
2020 if ((tp->tte_data & TD_PV) != 0) {
2024 rw_wunlock(&tte_list_global_lock);
2029 * Return a count of reference bits for a page, clearing those bits.
2030 * It is not necessary for every reference bit to be cleared, but it
2031 * is necessary that 0 only be returned when there are truly no
2032 * reference bits set.
2034 * XXX: The exact number of bits to check and clear is a matter that
2035 * should be tested and standardized at some point in the future for
2036 * optimal aging of shared pages.
2039 pmap_ts_referenced(vm_page_t m)
2047 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2048 ("pmap_ts_referenced: page %p is not managed", m));
2050 rw_wlock(&tte_list_global_lock);
2051 if ((tp = TAILQ_FIRST(&m->md.tte_list)) != NULL) {
2054 tpn = TAILQ_NEXT(tp, tte_link);
2055 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
2056 TAILQ_INSERT_TAIL(&m->md.tte_list, tp, tte_link);
2057 if ((tp->tte_data & TD_PV) == 0)
2059 data = atomic_clear_long(&tp->tte_data, TD_REF);
2060 if ((data & TD_REF) != 0 && ++count > 4)
2062 } while ((tp = tpn) != NULL && tp != tpf);
2064 rw_wunlock(&tte_list_global_lock);
2069 pmap_is_modified(vm_page_t m)
2074 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2075 ("pmap_is_modified: page %p is not managed", m));
2079 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be
2080 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
2081 * is clear, no TTEs can have TD_W set.
2083 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
2084 if ((m->oflags & VPO_BUSY) == 0 &&
2085 (m->aflags & PGA_WRITEABLE) == 0)
2087 rw_wlock(&tte_list_global_lock);
2088 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
2089 if ((tp->tte_data & TD_PV) == 0)
2091 if ((tp->tte_data & TD_W) != 0) {
2096 rw_wunlock(&tte_list_global_lock);
2101 * pmap_is_prefaultable:
2103 * Return whether or not the specified virtual address is elgible
2107 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
2112 rv = tsb_tte_lookup(pmap, addr) == NULL;
2118 * Return whether or not the specified physical page was referenced
2119 * in any physical maps.
2122 pmap_is_referenced(vm_page_t m)
2127 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2128 ("pmap_is_referenced: page %p is not managed", m));
2130 rw_wlock(&tte_list_global_lock);
2131 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
2132 if ((tp->tte_data & TD_PV) == 0)
2134 if ((tp->tte_data & TD_REF) != 0) {
2139 rw_wunlock(&tte_list_global_lock);
2144 pmap_clear_modify(vm_page_t m)
2149 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2150 ("pmap_clear_modify: page %p is not managed", m));
2151 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
2152 KASSERT((m->oflags & VPO_BUSY) == 0,
2153 ("pmap_clear_modify: page %p is busy", m));
2156 * If the page is not PGA_WRITEABLE, then no TTEs can have TD_W set.
2157 * If the object containing the page is locked and the page is not
2158 * VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set.
2160 if ((m->aflags & PGA_WRITEABLE) == 0)
2162 rw_wlock(&tte_list_global_lock);
2163 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
2164 if ((tp->tte_data & TD_PV) == 0)
2166 data = atomic_clear_long(&tp->tte_data, TD_W);
2167 if ((data & TD_W) != 0)
2168 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
2170 rw_wunlock(&tte_list_global_lock);
2174 pmap_clear_reference(vm_page_t m)
2179 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2180 ("pmap_clear_reference: page %p is not managed", m));
2181 rw_wlock(&tte_list_global_lock);
2182 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
2183 if ((tp->tte_data & TD_PV) == 0)
2185 data = atomic_clear_long(&tp->tte_data, TD_REF);
2186 if ((data & TD_REF) != 0)
2187 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
2189 rw_wunlock(&tte_list_global_lock);
2193 pmap_remove_write(vm_page_t m)
2198 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2199 ("pmap_remove_write: page %p is not managed", m));
2202 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by
2203 * another thread while the object is locked. Thus, if PGA_WRITEABLE
2204 * is clear, no page table entries need updating.
2206 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
2207 if ((m->oflags & VPO_BUSY) == 0 &&
2208 (m->aflags & PGA_WRITEABLE) == 0)
2210 rw_wlock(&tte_list_global_lock);
2211 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
2212 if ((tp->tte_data & TD_PV) == 0)
2214 data = atomic_clear_long(&tp->tte_data, TD_SW | TD_W);
2215 if ((data & TD_W) != 0) {
2217 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
2220 vm_page_aflag_clear(m, PGA_WRITEABLE);
2221 rw_wunlock(&tte_list_global_lock);
2225 pmap_mincore(pmap_t pm, vm_offset_t addr, vm_paddr_t *locked_pa)
2233 * Activate a user pmap. The pmap must be activated before its address space
2234 * can be accessed in any way.
2237 pmap_activate(struct thread *td)
2244 vm = td->td_proc->p_vmspace;
2245 pm = vmspace_pmap(vm);
2247 context = PCPU_GET(tlb_ctx);
2248 if (context == PCPU_GET(tlb_ctx_max)) {
2250 context = PCPU_GET(tlb_ctx_min);
2252 PCPU_SET(tlb_ctx, context + 1);
2254 pm->pm_context[curcpu] = context;
2256 CPU_SET_ATOMIC(PCPU_GET(cpuid), &pm->pm_active);
2257 atomic_store_acq_ptr((uintptr_t *)PCPU_PTR(pmap), (uintptr_t)pm);
2259 CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
2263 stxa(AA_DMMU_TSB, ASI_DMMU, pm->pm_tsb);
2264 stxa(AA_IMMU_TSB, ASI_IMMU, pm->pm_tsb);
2265 stxa(AA_DMMU_PCXR, ASI_DMMU, (ldxa(AA_DMMU_PCXR, ASI_DMMU) &
2266 TLB_CXR_PGSZ_MASK) | context);
2272 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
2278 * Increase the starting virtual address of the given mapping if a
2279 * different alignment might result in more superpage mappings.
2282 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
2283 vm_offset_t *addr, vm_size_t size)