2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
9 * This code is derived from software contributed to Berkeley by
10 * the Systems Programming Group of the University of Utah Computer
11 * Science Department and William Jolitz of UUNET Technologies Inc.
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 * 4. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
40 #include <sys/cdefs.h>
41 __FBSDID("$FreeBSD$");
44 * Manages physical address maps.
46 * In addition to hardware address maps, this module is called upon to
47 * provide software-use-only maps which may or may not be stored in the
48 * same form as hardware maps. These pseudo-maps are used to store
49 * intermediate results from copy operations to and from address spaces.
51 * Since the information managed by this module is also stored by the
52 * logical address mapping module, this module may throw away valid virtual
53 * to physical mappings at almost any time. However, invalidations of
54 * mappings must be done as requested.
56 * In order to cope with hardware architectures which make virtual to
57 * physical map invalidates expensive, this module may delay invalidate
58 * reduced protection operations until such time as they are actually
59 * necessary. This module is given full information as to which processors
60 * are currently using which maps, and to when physical maps must be made
64 #include "opt_kstack_pages.h"
67 #include <sys/param.h>
68 #include <sys/kernel.h>
71 #include <sys/msgbuf.h>
72 #include <sys/mutex.h>
75 #include <sys/sysctl.h>
76 #include <sys/systm.h>
77 #include <sys/vmmeter.h>
79 #include <dev/ofw/openfirm.h>
82 #include <vm/vm_param.h>
83 #include <vm/vm_kern.h>
84 #include <vm/vm_page.h>
85 #include <vm/vm_map.h>
86 #include <vm/vm_object.h>
87 #include <vm/vm_extern.h>
88 #include <vm/vm_pageout.h>
89 #include <vm/vm_pager.h>
91 #include <machine/cache.h>
92 #include <machine/frame.h>
93 #include <machine/instr.h>
94 #include <machine/md_var.h>
95 #include <machine/metadata.h>
96 #include <machine/ofw_mem.h>
97 #include <machine/smp.h>
98 #include <machine/tlb.h>
99 #include <machine/tte.h>
100 #include <machine/tsb.h>
101 #include <machine/ver.h>
105 #ifndef PMAP_SHPGPERPROC
106 #define PMAP_SHPGPERPROC 200
110 #include "opt_sched.h"
112 #error "sparc64 only works with SCHED_4BSD which uses a global scheduler lock."
114 extern struct mtx sched_lock;
117 * Virtual address of message buffer
119 struct msgbuf *msgbufp;
122 * Map of physical memory reagions
124 vm_paddr_t phys_avail[128];
125 static struct ofw_mem_region mra[128];
126 struct ofw_mem_region sparc64_memreg[128];
128 static struct ofw_map translations[128];
129 static int translations_size;
131 static vm_offset_t pmap_idle_map;
132 static vm_offset_t pmap_temp_map_1;
133 static vm_offset_t pmap_temp_map_2;
136 * First and last available kernel virtual addresses
138 vm_offset_t virtual_avail;
139 vm_offset_t virtual_end;
140 vm_offset_t kernel_vm_end;
142 vm_offset_t vm_max_kernel_address;
147 struct pmap kernel_pmap_store;
150 * Allocate physical memory for use in pmap_bootstrap.
152 static vm_paddr_t pmap_bootstrap_alloc(vm_size_t size, uint32_t colors);
155 * Map the given physical page at the specified virtual address in the
156 * target pmap with the protection requested. If specified the page
157 * will be wired down.
159 * The page queues and pmap must be locked.
161 static void pmap_enter_locked(pmap_t pm, vm_offset_t va, vm_page_t m,
162 vm_prot_t prot, boolean_t wired);
164 extern int tl1_immu_miss_patch_1[];
165 extern int tl1_immu_miss_patch_2[];
166 extern int tl1_dmmu_miss_patch_1[];
167 extern int tl1_dmmu_miss_patch_2[];
168 extern int tl1_dmmu_prot_patch_1[];
169 extern int tl1_dmmu_prot_patch_2[];
172 * If user pmap is processed with pmap_remove and with pmap_remove and the
173 * resident count drops to 0, there are no more pages to remove, so we
176 #define PMAP_REMOVE_DONE(pm) \
177 ((pm) != kernel_pmap && (pm)->pm_stats.resident_count == 0)
180 * The threshold (in bytes) above which tsb_foreach() is used in pmap_remove()
181 * and pmap_protect() instead of trying each virtual address.
183 #define PMAP_TSB_THRESH ((TSB_SIZE / 2) * PAGE_SIZE)
185 SYSCTL_NODE(_debug, OID_AUTO, pmap_stats, CTLFLAG_RD, 0, "");
187 PMAP_STATS_VAR(pmap_nenter);
188 PMAP_STATS_VAR(pmap_nenter_update);
189 PMAP_STATS_VAR(pmap_nenter_replace);
190 PMAP_STATS_VAR(pmap_nenter_new);
191 PMAP_STATS_VAR(pmap_nkenter);
192 PMAP_STATS_VAR(pmap_nkenter_oc);
193 PMAP_STATS_VAR(pmap_nkenter_stupid);
194 PMAP_STATS_VAR(pmap_nkremove);
195 PMAP_STATS_VAR(pmap_nqenter);
196 PMAP_STATS_VAR(pmap_nqremove);
197 PMAP_STATS_VAR(pmap_ncache_enter);
198 PMAP_STATS_VAR(pmap_ncache_enter_c);
199 PMAP_STATS_VAR(pmap_ncache_enter_oc);
200 PMAP_STATS_VAR(pmap_ncache_enter_cc);
201 PMAP_STATS_VAR(pmap_ncache_enter_coc);
202 PMAP_STATS_VAR(pmap_ncache_enter_nc);
203 PMAP_STATS_VAR(pmap_ncache_enter_cnc);
204 PMAP_STATS_VAR(pmap_ncache_remove);
205 PMAP_STATS_VAR(pmap_ncache_remove_c);
206 PMAP_STATS_VAR(pmap_ncache_remove_oc);
207 PMAP_STATS_VAR(pmap_ncache_remove_cc);
208 PMAP_STATS_VAR(pmap_ncache_remove_coc);
209 PMAP_STATS_VAR(pmap_ncache_remove_nc);
210 PMAP_STATS_VAR(pmap_nzero_page);
211 PMAP_STATS_VAR(pmap_nzero_page_c);
212 PMAP_STATS_VAR(pmap_nzero_page_oc);
213 PMAP_STATS_VAR(pmap_nzero_page_nc);
214 PMAP_STATS_VAR(pmap_nzero_page_area);
215 PMAP_STATS_VAR(pmap_nzero_page_area_c);
216 PMAP_STATS_VAR(pmap_nzero_page_area_oc);
217 PMAP_STATS_VAR(pmap_nzero_page_area_nc);
218 PMAP_STATS_VAR(pmap_nzero_page_idle);
219 PMAP_STATS_VAR(pmap_nzero_page_idle_c);
220 PMAP_STATS_VAR(pmap_nzero_page_idle_oc);
221 PMAP_STATS_VAR(pmap_nzero_page_idle_nc);
222 PMAP_STATS_VAR(pmap_ncopy_page);
223 PMAP_STATS_VAR(pmap_ncopy_page_c);
224 PMAP_STATS_VAR(pmap_ncopy_page_oc);
225 PMAP_STATS_VAR(pmap_ncopy_page_nc);
226 PMAP_STATS_VAR(pmap_ncopy_page_dc);
227 PMAP_STATS_VAR(pmap_ncopy_page_doc);
228 PMAP_STATS_VAR(pmap_ncopy_page_sc);
229 PMAP_STATS_VAR(pmap_ncopy_page_soc);
231 PMAP_STATS_VAR(pmap_nnew_thread);
232 PMAP_STATS_VAR(pmap_nnew_thread_oc);
234 static inline u_long dtlb_get_data(u_int slot);
237 * Quick sort callout for comparing memory regions
239 static int mr_cmp(const void *a, const void *b);
240 static int om_cmp(const void *a, const void *b);
243 mr_cmp(const void *a, const void *b)
245 const struct ofw_mem_region *mra;
246 const struct ofw_mem_region *mrb;
250 if (mra->mr_start < mrb->mr_start)
252 else if (mra->mr_start > mrb->mr_start)
259 om_cmp(const void *a, const void *b)
261 const struct ofw_map *oma;
262 const struct ofw_map *omb;
266 if (oma->om_start < omb->om_start)
268 else if (oma->om_start > omb->om_start)
275 dtlb_get_data(u_int slot)
279 * We read ASI_DTLB_DATA_ACCESS_REG twice in order to work
280 * around errata of USIII and beyond.
282 (void)ldxa(TLB_DAR_SLOT(slot), ASI_DTLB_DATA_ACCESS_REG);
283 return (ldxa(TLB_DAR_SLOT(slot), ASI_DTLB_DATA_ACCESS_REG));
287 * Bootstrap the system enough to run with virtual memory.
290 pmap_bootstrap(u_int cpu_impl)
302 u_int dtlb_slots_avail;
308 colors = dcache_color_ignore != 0 ? 1 : DCACHE_COLORS;
311 * Find out what physical memory is available from the PROM and
312 * initialize the phys_avail array. This must be done before
313 * pmap_bootstrap_alloc is called.
315 if ((pmem = OF_finddevice("/memory")) == -1)
316 panic("pmap_bootstrap: finddevice /memory");
317 if ((sz = OF_getproplen(pmem, "available")) == -1)
318 panic("pmap_bootstrap: getproplen /memory/available");
319 if (sizeof(phys_avail) < sz)
320 panic("pmap_bootstrap: phys_avail too small");
321 if (sizeof(mra) < sz)
322 panic("pmap_bootstrap: mra too small");
324 if (OF_getprop(pmem, "available", mra, sz) == -1)
325 panic("pmap_bootstrap: getprop /memory/available");
327 CTR0(KTR_PMAP, "pmap_bootstrap: physical memory");
328 qsort(mra, sz, sizeof (*mra), mr_cmp);
330 getenv_quad("hw.physmem", &physmem);
331 physmem = btoc(physmem);
332 for (i = 0, j = 0; i < sz; i++, j += 2) {
333 CTR2(KTR_PMAP, "start=%#lx size=%#lx", mra[i].mr_start,
335 if (physmem != 0 && btoc(physsz + mra[i].mr_size) >= physmem) {
336 if (btoc(physsz) < physmem) {
337 phys_avail[j] = mra[i].mr_start;
338 phys_avail[j + 1] = mra[i].mr_start +
339 (ctob(physmem) - physsz);
340 physsz = ctob(physmem);
344 phys_avail[j] = mra[i].mr_start;
345 phys_avail[j + 1] = mra[i].mr_start + mra[i].mr_size;
346 physsz += mra[i].mr_size;
348 physmem = btoc(physsz);
351 * Calculate the size of kernel virtual memory, and the size and mask
352 * for the kernel TSB based on the phsyical memory size but limited
353 * by the amount of dTLB slots available for locked entries (given
354 * that for spitfire-class CPUs all of the dt64 slots can hold locked
355 * entries but there is no large dTLB for unlocked ones, we don't use
356 * more than half of it for locked entries).
358 dtlb_slots_avail = 0;
359 for (i = 0; i < dtlb_slots; i++) {
360 data = dtlb_get_data(i);
361 if ((data & (TD_V | TD_L)) != (TD_V | TD_L))
365 dtlb_slots_avail -= PCPU_PAGES;
367 if (cpu_impl >= CPU_IMPL_ULTRASPARCI &&
368 cpu_impl < CPU_IMPL_ULTRASPARCIII)
369 dtlb_slots_avail /= 2;
370 virtsz = roundup(physsz, PAGE_SIZE_4M << (PAGE_SHIFT - TTE_SHIFT));
372 (dtlb_slots_avail * PAGE_SIZE_4M) << (PAGE_SHIFT - TTE_SHIFT));
373 vm_max_kernel_address = VM_MIN_KERNEL_ADDRESS + virtsz;
374 tsb_kernel_size = virtsz >> (PAGE_SHIFT - TTE_SHIFT);
375 tsb_kernel_mask = (tsb_kernel_size >> TTE_SHIFT) - 1;
378 * Allocate the kernel TSB and lock it in the TLB.
380 pa = pmap_bootstrap_alloc(tsb_kernel_size, colors);
381 if (pa & PAGE_MASK_4M)
382 panic("pmap_bootstrap: tsb unaligned\n");
383 tsb_kernel_phys = pa;
384 tsb_kernel = (struct tte *)(VM_MIN_KERNEL_ADDRESS - tsb_kernel_size);
386 bzero(tsb_kernel, tsb_kernel_size);
389 * Allocate and map the dynamic per-CPU area for the BSP.
391 pa = pmap_bootstrap_alloc(DPCPU_SIZE, colors);
392 dpcpu0 = (void *)TLB_PHYS_TO_DIRECT(pa);
395 * Allocate and map the message buffer.
397 pa = pmap_bootstrap_alloc(msgbufsize, colors);
398 msgbufp = (struct msgbuf *)TLB_PHYS_TO_DIRECT(pa);
401 * Patch the virtual address and the tsb mask into the trap table.
404 #define SETHI(rd, imm22) \
405 (EIF_OP(IOP_FORM2) | EIF_F2_RD(rd) | EIF_F2_OP2(INS0_SETHI) | \
406 EIF_IMM((imm22) >> 10, 22))
407 #define OR_R_I_R(rd, imm13, rs1) \
408 (EIF_OP(IOP_MISC) | EIF_F3_RD(rd) | EIF_F3_OP3(INS2_OR) | \
409 EIF_F3_RS1(rs1) | EIF_F3_I(1) | EIF_IMM(imm13, 13))
411 #define PATCH(addr) do { \
412 if (addr[0] != SETHI(IF_F2_RD(addr[0]), 0x0) || \
413 addr[1] != OR_R_I_R(IF_F3_RD(addr[1]), 0x0, IF_F3_RS1(addr[1])) || \
414 addr[2] != SETHI(IF_F2_RD(addr[2]), 0x0)) \
415 panic("pmap_boostrap: patched instructions have changed"); \
416 addr[0] |= EIF_IMM((tsb_kernel_mask) >> 10, 22); \
417 addr[1] |= EIF_IMM(tsb_kernel_mask, 10); \
418 addr[2] |= EIF_IMM(((vm_offset_t)tsb_kernel) >> 10, 22); \
424 PATCH(tl1_immu_miss_patch_1);
425 PATCH(tl1_immu_miss_patch_2);
426 PATCH(tl1_dmmu_miss_patch_1);
427 PATCH(tl1_dmmu_miss_patch_2);
428 PATCH(tl1_dmmu_prot_patch_1);
429 PATCH(tl1_dmmu_prot_patch_2);
432 * Enter fake 8k pages for the 4MB kernel pages, so that
433 * pmap_kextract() will work for them.
435 for (i = 0; i < kernel_tlb_slots; i++) {
436 pa = kernel_tlbs[i].te_pa;
437 va = kernel_tlbs[i].te_va;
438 for (off = 0; off < PAGE_SIZE_4M; off += PAGE_SIZE) {
439 tp = tsb_kvtotte(va + off);
440 tp->tte_vpn = TV_VPN(va + off, TS_8K);
441 tp->tte_data = TD_V | TD_8K | TD_PA(pa + off) |
442 TD_REF | TD_SW | TD_CP | TD_CV | TD_P | TD_W;
447 * Set the start and end of KVA. The kernel is loaded starting
448 * at the first available 4MB super page, so we advance to the
449 * end of the last one used for it.
451 virtual_avail = KERNBASE + kernel_tlb_slots * PAGE_SIZE_4M;
452 virtual_end = vm_max_kernel_address;
453 kernel_vm_end = vm_max_kernel_address;
456 * Allocate kva space for temporary mappings.
458 pmap_idle_map = virtual_avail;
459 virtual_avail += PAGE_SIZE * colors;
460 pmap_temp_map_1 = virtual_avail;
461 virtual_avail += PAGE_SIZE * colors;
462 pmap_temp_map_2 = virtual_avail;
463 virtual_avail += PAGE_SIZE * colors;
466 * Allocate a kernel stack with guard page for thread0 and map it
467 * into the kernel TSB. We must ensure that the virtual address is
468 * colored properly for corresponding CPUs, since we're allocating
469 * from phys_avail so the memory won't have an associated vm_page_t.
471 pa = pmap_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, colors);
473 virtual_avail += roundup(KSTACK_GUARD_PAGES, colors) * PAGE_SIZE;
474 kstack0 = virtual_avail;
475 virtual_avail += roundup(KSTACK_PAGES, colors) * PAGE_SIZE;
476 if (dcache_color_ignore == 0)
477 KASSERT(DCACHE_COLOR(kstack0) == DCACHE_COLOR(kstack0_phys),
478 ("pmap_bootstrap: kstack0 miscolored"));
479 for (i = 0; i < KSTACK_PAGES; i++) {
480 pa = kstack0_phys + i * PAGE_SIZE;
481 va = kstack0 + i * PAGE_SIZE;
482 tp = tsb_kvtotte(va);
483 tp->tte_vpn = TV_VPN(va, TS_8K);
484 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_REF | TD_SW |
485 TD_CP | TD_CV | TD_P | TD_W;
489 * Calculate the last available physical address.
491 for (i = 0; phys_avail[i + 2] != 0; i += 2)
493 Maxmem = sparc64_btop(phys_avail[i + 1]);
496 * Add the PROM mappings to the kernel TSB.
498 if ((vmem = OF_finddevice("/virtual-memory")) == -1)
499 panic("pmap_bootstrap: finddevice /virtual-memory");
500 if ((sz = OF_getproplen(vmem, "translations")) == -1)
501 panic("pmap_bootstrap: getproplen translations");
502 if (sizeof(translations) < sz)
503 panic("pmap_bootstrap: translations too small");
504 bzero(translations, sz);
505 if (OF_getprop(vmem, "translations", translations, sz) == -1)
506 panic("pmap_bootstrap: getprop /virtual-memory/translations");
507 sz /= sizeof(*translations);
508 translations_size = sz;
509 CTR0(KTR_PMAP, "pmap_bootstrap: translations");
510 qsort(translations, sz, sizeof (*translations), om_cmp);
511 for (i = 0; i < sz; i++) {
513 "translation: start=%#lx size=%#lx tte=%#lx",
514 translations[i].om_start, translations[i].om_size,
515 translations[i].om_tte);
516 if ((translations[i].om_tte & TD_V) == 0)
518 if (translations[i].om_start < VM_MIN_PROM_ADDRESS ||
519 translations[i].om_start > VM_MAX_PROM_ADDRESS)
521 for (off = 0; off < translations[i].om_size;
523 va = translations[i].om_start + off;
524 tp = tsb_kvtotte(va);
525 tp->tte_vpn = TV_VPN(va, TS_8K);
527 ((translations[i].om_tte &
528 ~((TD_SOFT2_MASK << TD_SOFT2_SHIFT) |
529 (cpu_impl >= CPU_IMPL_ULTRASPARCI &&
530 cpu_impl < CPU_IMPL_ULTRASPARCIII ?
531 (TD_DIAG_SF_MASK << TD_DIAG_SF_SHIFT) :
532 (TD_RSVD_CH_MASK << TD_RSVD_CH_SHIFT)) |
533 (TD_SOFT_MASK << TD_SOFT_SHIFT))) | TD_EXEC) +
539 * Get the available physical memory ranges from /memory/reg. These
540 * are only used for kernel dumps, but it may not be wise to do PROM
541 * calls in that situation.
543 if ((sz = OF_getproplen(pmem, "reg")) == -1)
544 panic("pmap_bootstrap: getproplen /memory/reg");
545 if (sizeof(sparc64_memreg) < sz)
546 panic("pmap_bootstrap: sparc64_memreg too small");
547 if (OF_getprop(pmem, "reg", sparc64_memreg, sz) == -1)
548 panic("pmap_bootstrap: getprop /memory/reg");
549 sparc64_nmemreg = sz / sizeof(*sparc64_memreg);
552 * Initialize the kernel pmap (which is statically allocated).
553 * NOTE: PMAP_LOCK_INIT() is needed as part of the initialization
554 * but sparc64 start up is not ready to initialize mutexes yet.
555 * It is called in machdep.c.
558 for (i = 0; i < MAXCPU; i++)
559 pm->pm_context[i] = TLB_CTX_KERNEL;
563 * Flush all non-locked TLB entries possibly left over by the
566 tlb_flush_nonlocked();
581 * Map the 4MB TSB pages.
583 for (i = 0; i < tsb_kernel_size; i += PAGE_SIZE_4M) {
584 va = (vm_offset_t)tsb_kernel + i;
585 pa = tsb_kernel_phys + i;
586 data = TD_V | TD_4M | TD_PA(pa) | TD_L | TD_CP | TD_CV |
588 stxa(AA_DMMU_TAR, ASI_DMMU, TLB_TAR_VA(va) |
589 TLB_TAR_CTX(TLB_CTX_KERNEL));
590 stxa_sync(0, ASI_DTLB_DATA_IN_REG, data);
594 * Set the secondary context to be the kernel context (needed for
595 * FP block operations in the kernel).
597 stxa(AA_DMMU_SCXR, ASI_DMMU, (ldxa(AA_DMMU_SCXR, ASI_DMMU) &
598 TLB_CXR_PGSZ_MASK) | TLB_CTX_KERNEL);
605 * Allocate a physical page of memory directly from the phys_avail map.
606 * Can only be called from pmap_bootstrap before avail start and end are
610 pmap_bootstrap_alloc(vm_size_t size, uint32_t colors)
615 size = roundup(size, PAGE_SIZE * colors);
616 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
617 if (phys_avail[i + 1] - phys_avail[i] < size)
620 phys_avail[i] += size;
623 panic("pmap_bootstrap_alloc");
627 * Initialize a vm_page's machine-dependent fields.
630 pmap_page_init(vm_page_t m)
633 TAILQ_INIT(&m->md.tte_list);
634 m->md.color = DCACHE_COLOR(VM_PAGE_TO_PHYS(m));
640 * Initialize the pmap module.
650 for (i = 0; i < translations_size; i++) {
651 addr = translations[i].om_start;
652 size = translations[i].om_size;
653 if ((translations[i].om_tte & TD_V) == 0)
655 if (addr < VM_MIN_PROM_ADDRESS || addr > VM_MAX_PROM_ADDRESS)
657 result = vm_map_find(kernel_map, NULL, 0, &addr, size,
658 VMFS_NO_SPACE, VM_PROT_ALL, VM_PROT_ALL, MAP_NOFAULT);
659 if (result != KERN_SUCCESS || addr != translations[i].om_start)
660 panic("pmap_init: vm_map_find");
665 * Extract the physical page address associated with the given
666 * map/virtual_address pair.
669 pmap_extract(pmap_t pm, vm_offset_t va)
674 if (pm == kernel_pmap)
675 return (pmap_kextract(va));
677 tp = tsb_tte_lookup(pm, va);
681 pa = TTE_GET_PA(tp) | (va & TTE_GET_PAGE_MASK(tp));
687 * Atomically extract and hold the physical page with the given
688 * pmap and virtual address pair if that mapping permits the given
692 pmap_extract_and_hold(pmap_t pm, vm_offset_t va, vm_prot_t prot)
698 vm_page_lock_queues();
699 if (pm == kernel_pmap) {
700 if (va >= VM_MIN_DIRECT_ADDRESS) {
702 m = PHYS_TO_VM_PAGE(TLB_DIRECT_TO_PHYS(va));
705 tp = tsb_kvtotte(va);
706 if ((tp->tte_data & TD_V) == 0)
711 tp = tsb_tte_lookup(pm, va);
713 if (tp != NULL && ((tp->tte_data & TD_SW) ||
714 (prot & VM_PROT_WRITE) == 0)) {
715 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
718 vm_page_unlock_queues();
719 if (pm != kernel_pmap)
725 * Extract the physical page address associated with the given kernel virtual
729 pmap_kextract(vm_offset_t va)
733 if (va >= VM_MIN_DIRECT_ADDRESS)
734 return (TLB_DIRECT_TO_PHYS(va));
735 tp = tsb_kvtotte(va);
736 if ((tp->tte_data & TD_V) == 0)
738 return (TTE_GET_PA(tp) | (va & TTE_GET_PAGE_MASK(tp)));
742 pmap_cache_enter(vm_page_t m, vm_offset_t va)
747 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
748 KASSERT((m->flags & PG_FICTITIOUS) == 0,
749 ("pmap_cache_enter: fake page"));
750 PMAP_STATS_INC(pmap_ncache_enter);
752 if (dcache_color_ignore != 0)
756 * Find the color for this virtual address and note the added mapping.
758 color = DCACHE_COLOR(va);
759 m->md.colors[color]++;
762 * If all existing mappings have the same color, the mapping is
765 if (m->md.color == color) {
766 KASSERT(m->md.colors[DCACHE_OTHER_COLOR(color)] == 0,
767 ("pmap_cache_enter: cacheable, mappings of other color"));
768 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
769 PMAP_STATS_INC(pmap_ncache_enter_c);
771 PMAP_STATS_INC(pmap_ncache_enter_oc);
776 * If there are no mappings of the other color, and the page still has
777 * the wrong color, this must be a new mapping. Change the color to
778 * match the new mapping, which is cacheable. We must flush the page
779 * from the cache now.
781 if (m->md.colors[DCACHE_OTHER_COLOR(color)] == 0) {
782 KASSERT(m->md.colors[color] == 1,
783 ("pmap_cache_enter: changing color, not new mapping"));
784 dcache_page_inval(VM_PAGE_TO_PHYS(m));
786 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
787 PMAP_STATS_INC(pmap_ncache_enter_cc);
789 PMAP_STATS_INC(pmap_ncache_enter_coc);
794 * If the mapping is already non-cacheable, just return.
796 if (m->md.color == -1) {
797 PMAP_STATS_INC(pmap_ncache_enter_nc);
801 PMAP_STATS_INC(pmap_ncache_enter_cnc);
804 * Mark all mappings as uncacheable, flush any lines with the other
805 * color out of the dcache, and set the color to none (-1).
807 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
808 atomic_clear_long(&tp->tte_data, TD_CV);
809 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
811 dcache_page_inval(VM_PAGE_TO_PHYS(m));
817 pmap_cache_remove(vm_page_t m, vm_offset_t va)
822 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
823 CTR3(KTR_PMAP, "pmap_cache_remove: m=%p va=%#lx c=%d", m, va,
824 m->md.colors[DCACHE_COLOR(va)]);
825 KASSERT((m->flags & PG_FICTITIOUS) == 0,
826 ("pmap_cache_remove: fake page"));
827 PMAP_STATS_INC(pmap_ncache_remove);
829 if (dcache_color_ignore != 0)
832 KASSERT(m->md.colors[DCACHE_COLOR(va)] > 0,
833 ("pmap_cache_remove: no mappings %d <= 0",
834 m->md.colors[DCACHE_COLOR(va)]));
837 * Find the color for this virtual address and note the removal of
840 color = DCACHE_COLOR(va);
841 m->md.colors[color]--;
844 * If the page is cacheable, just return and keep the same color, even
845 * if there are no longer any mappings.
847 if (m->md.color != -1) {
848 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
849 PMAP_STATS_INC(pmap_ncache_remove_c);
851 PMAP_STATS_INC(pmap_ncache_remove_oc);
855 KASSERT(m->md.colors[DCACHE_OTHER_COLOR(color)] != 0,
856 ("pmap_cache_remove: uncacheable, no mappings of other color"));
859 * If the page is not cacheable (color is -1), and the number of
860 * mappings for this color is not zero, just return. There are
861 * mappings of the other color still, so remain non-cacheable.
863 if (m->md.colors[color] != 0) {
864 PMAP_STATS_INC(pmap_ncache_remove_nc);
869 * The number of mappings for this color is now zero. Recache the
870 * other colored mappings, and change the page color to the other
871 * color. There should be no lines in the data cache for this page,
872 * so flushing should not be needed.
874 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
875 atomic_set_long(&tp->tte_data, TD_CV);
876 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
878 m->md.color = DCACHE_OTHER_COLOR(color);
880 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m)))
881 PMAP_STATS_INC(pmap_ncache_remove_cc);
883 PMAP_STATS_INC(pmap_ncache_remove_coc);
887 * Map a wired page into kernel virtual address space.
890 pmap_kenter(vm_offset_t va, vm_page_t m)
897 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
898 PMAP_STATS_INC(pmap_nkenter);
899 tp = tsb_kvtotte(va);
900 CTR4(KTR_PMAP, "pmap_kenter: va=%#lx pa=%#lx tp=%p data=%#lx",
901 va, VM_PAGE_TO_PHYS(m), tp, tp->tte_data);
902 if (DCACHE_COLOR(VM_PAGE_TO_PHYS(m)) != DCACHE_COLOR(va)) {
904 "pmap_kenter: off color va=%#lx pa=%#lx o=%p ot=%d pi=%#lx",
905 va, VM_PAGE_TO_PHYS(m), m->object,
906 m->object ? m->object->type : -1,
908 PMAP_STATS_INC(pmap_nkenter_oc);
910 if ((tp->tte_data & TD_V) != 0) {
911 om = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
912 ova = TTE_GET_VA(tp);
913 if (m == om && va == ova) {
914 PMAP_STATS_INC(pmap_nkenter_stupid);
917 TAILQ_REMOVE(&om->md.tte_list, tp, tte_link);
918 pmap_cache_remove(om, ova);
920 tlb_page_demap(kernel_pmap, ova);
922 data = TD_V | TD_8K | VM_PAGE_TO_PHYS(m) | TD_REF | TD_SW | TD_CP |
924 if (pmap_cache_enter(m, va) != 0)
926 tp->tte_vpn = TV_VPN(va, TS_8K);
928 TAILQ_INSERT_TAIL(&m->md.tte_list, tp, tte_link);
932 * Map a wired page into kernel virtual address space. This additionally
933 * takes a flag argument wich is or'ed to the TTE data. This is used by
934 * sparc64_bus_mem_map().
935 * NOTE: if the mapping is non-cacheable, it's the caller's responsibility
936 * to flush entries that might still be in the cache, if applicable.
939 pmap_kenter_flags(vm_offset_t va, vm_paddr_t pa, u_long flags)
943 tp = tsb_kvtotte(va);
944 CTR4(KTR_PMAP, "pmap_kenter_flags: va=%#lx pa=%#lx tp=%p data=%#lx",
945 va, pa, tp, tp->tte_data);
946 tp->tte_vpn = TV_VPN(va, TS_8K);
947 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_REF | TD_P | flags;
951 * Remove a wired page from kernel virtual address space.
954 pmap_kremove(vm_offset_t va)
959 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
960 PMAP_STATS_INC(pmap_nkremove);
961 tp = tsb_kvtotte(va);
962 CTR3(KTR_PMAP, "pmap_kremove: va=%#lx tp=%p data=%#lx", va, tp,
964 if ((tp->tte_data & TD_V) == 0)
966 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
967 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
968 pmap_cache_remove(m, va);
973 * Inverse of pmap_kenter_flags, used by bus_space_unmap().
976 pmap_kremove_flags(vm_offset_t va)
980 tp = tsb_kvtotte(va);
981 CTR3(KTR_PMAP, "pmap_kremove_flags: va=%#lx tp=%p data=%#lx", va, tp,
987 * Map a range of physical addresses into kernel virtual address space.
989 * The value passed in *virt is a suggested virtual address for the mapping.
990 * Architectures which can support a direct-mapped physical to virtual region
991 * can return the appropriate address within that region, leaving '*virt'
995 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
998 return (TLB_PHYS_TO_DIRECT(start));
1002 * Map a list of wired pages into kernel virtual address space. This is
1003 * intended for temporary mappings which do not need page modification or
1004 * references recorded. Existing mappings in the region are overwritten.
1007 pmap_qenter(vm_offset_t sva, vm_page_t *m, int count)
1012 PMAP_STATS_INC(pmap_nqenter);
1014 if (!(locked = mtx_owned(&vm_page_queue_mtx)))
1015 vm_page_lock_queues();
1016 while (count-- > 0) {
1017 pmap_kenter(va, *m);
1022 vm_page_unlock_queues();
1023 tlb_range_demap(kernel_pmap, sva, va);
1027 * Remove page mappings from kernel virtual address space. Intended for
1028 * temporary mappings entered by pmap_qenter.
1031 pmap_qremove(vm_offset_t sva, int count)
1036 PMAP_STATS_INC(pmap_nqremove);
1038 if (!(locked = mtx_owned(&vm_page_queue_mtx)))
1039 vm_page_lock_queues();
1040 while (count-- > 0) {
1045 vm_page_unlock_queues();
1046 tlb_range_demap(kernel_pmap, sva, va);
1050 * Initialize the pmap associated with process 0.
1053 pmap_pinit0(pmap_t pm)
1058 for (i = 0; i < MAXCPU; i++)
1059 pm->pm_context[i] = TLB_CTX_KERNEL;
1062 pm->pm_tsb_obj = NULL;
1063 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1067 * Initialize a preallocated and zeroed pmap structure, such as one in a
1068 * vmspace structure.
1071 pmap_pinit(pmap_t pm)
1073 vm_page_t ma[TSB_PAGES];
1080 * Allocate KVA space for the TSB.
1082 if (pm->pm_tsb == NULL) {
1083 pm->pm_tsb = (struct tte *)kmem_alloc_nofault(kernel_map,
1085 if (pm->pm_tsb == NULL) {
1086 PMAP_LOCK_DESTROY(pm);
1092 * Allocate an object for it.
1094 if (pm->pm_tsb_obj == NULL)
1095 pm->pm_tsb_obj = vm_object_allocate(OBJT_DEFAULT, TSB_PAGES);
1097 mtx_lock_spin(&sched_lock);
1098 for (i = 0; i < MAXCPU; i++)
1099 pm->pm_context[i] = -1;
1101 mtx_unlock_spin(&sched_lock);
1103 VM_OBJECT_LOCK(pm->pm_tsb_obj);
1104 for (i = 0; i < TSB_PAGES; i++) {
1105 m = vm_page_grab(pm->pm_tsb_obj, i, VM_ALLOC_NOBUSY |
1106 VM_ALLOC_RETRY | VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1107 m->valid = VM_PAGE_BITS_ALL;
1111 VM_OBJECT_UNLOCK(pm->pm_tsb_obj);
1112 pmap_qenter((vm_offset_t)pm->pm_tsb, ma, TSB_PAGES);
1114 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1119 * Release any resources held by the given physical map.
1120 * Called when a pmap initialized by pmap_pinit is being released.
1121 * Should only be called if the map contains no valid mappings.
1124 pmap_release(pmap_t pm)
1130 CTR2(KTR_PMAP, "pmap_release: ctx=%#x tsb=%p",
1131 pm->pm_context[curcpu], pm->pm_tsb);
1132 KASSERT(pmap_resident_count(pm) == 0,
1133 ("pmap_release: resident pages %ld != 0",
1134 pmap_resident_count(pm)));
1137 * After the pmap was freed, it might be reallocated to a new process.
1138 * When switching, this might lead us to wrongly assume that we need
1139 * not switch contexts because old and new pmap pointer are equal.
1140 * Therefore, make sure that this pmap is not referenced by any PCPU
1141 * pointer any more. This could happen in two cases:
1142 * - A process that referenced the pmap is currently exiting on a CPU.
1143 * However, it is guaranteed to not switch in any more after setting
1144 * its state to PRS_ZOMBIE.
1145 * - A process that referenced this pmap ran on a CPU, but we switched
1146 * to a kernel thread, leaving the pmap pointer unchanged.
1148 mtx_lock_spin(&sched_lock);
1149 SLIST_FOREACH(pc, &cpuhead, pc_allcpu)
1150 if (pc->pc_pmap == pm)
1152 mtx_unlock_spin(&sched_lock);
1154 obj = pm->pm_tsb_obj;
1155 VM_OBJECT_LOCK(obj);
1156 KASSERT(obj->ref_count == 1, ("pmap_release: tsbobj ref count != 1"));
1157 while (!TAILQ_EMPTY(&obj->memq)) {
1158 m = TAILQ_FIRST(&obj->memq);
1159 vm_page_lock_queues();
1160 if (vm_page_sleep_if_busy(m, FALSE, "pmaprl"))
1162 KASSERT(m->hold_count == 0,
1163 ("pmap_release: freeing held tsb page"));
1166 atomic_subtract_int(&cnt.v_wire_count, 1);
1167 vm_page_free_zero(m);
1168 vm_page_unlock_queues();
1170 VM_OBJECT_UNLOCK(obj);
1171 pmap_qremove((vm_offset_t)pm->pm_tsb, TSB_PAGES);
1172 PMAP_LOCK_DESTROY(pm);
1176 * Grow the number of kernel page table entries. Unneeded.
1179 pmap_growkernel(vm_offset_t addr)
1182 panic("pmap_growkernel: can't grow kernel");
1186 pmap_remove_tte(struct pmap *pm, struct pmap *pm2, struct tte *tp,
1192 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1193 data = atomic_readandclear_long(&tp->tte_data);
1194 if ((data & TD_FAKE) == 0) {
1195 m = PHYS_TO_VM_PAGE(TD_PA(data));
1196 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
1197 if ((data & TD_WIRED) != 0)
1198 pm->pm_stats.wired_count--;
1199 if ((data & TD_PV) != 0) {
1200 if ((data & TD_W) != 0)
1202 if ((data & TD_REF) != 0)
1203 vm_page_flag_set(m, PG_REFERENCED);
1204 if (TAILQ_EMPTY(&m->md.tte_list))
1205 vm_page_flag_clear(m, PG_WRITEABLE);
1206 pm->pm_stats.resident_count--;
1208 pmap_cache_remove(m, va);
1211 if (PMAP_REMOVE_DONE(pm))
1217 * Remove the given range of addresses from the specified map.
1220 pmap_remove(pmap_t pm, vm_offset_t start, vm_offset_t end)
1225 CTR3(KTR_PMAP, "pmap_remove: ctx=%#lx start=%#lx end=%#lx",
1226 pm->pm_context[curcpu], start, end);
1227 if (PMAP_REMOVE_DONE(pm))
1229 vm_page_lock_queues();
1231 if (end - start > PMAP_TSB_THRESH) {
1232 tsb_foreach(pm, NULL, start, end, pmap_remove_tte);
1233 tlb_context_demap(pm);
1235 for (va = start; va < end; va += PAGE_SIZE)
1236 if ((tp = tsb_tte_lookup(pm, va)) != NULL &&
1237 !pmap_remove_tte(pm, NULL, tp, va))
1239 tlb_range_demap(pm, start, end - 1);
1242 vm_page_unlock_queues();
1246 pmap_remove_all(vm_page_t m)
1253 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1254 for (tp = TAILQ_FIRST(&m->md.tte_list); tp != NULL; tp = tpn) {
1255 tpn = TAILQ_NEXT(tp, tte_link);
1256 if ((tp->tte_data & TD_PV) == 0)
1258 pm = TTE_GET_PMAP(tp);
1259 va = TTE_GET_VA(tp);
1261 if ((tp->tte_data & TD_WIRED) != 0)
1262 pm->pm_stats.wired_count--;
1263 if ((tp->tte_data & TD_REF) != 0)
1264 vm_page_flag_set(m, PG_REFERENCED);
1265 if ((tp->tte_data & TD_W) != 0)
1267 tp->tte_data &= ~TD_V;
1268 tlb_page_demap(pm, va);
1269 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
1270 pm->pm_stats.resident_count--;
1271 pmap_cache_remove(m, va);
1275 vm_page_flag_clear(m, PG_WRITEABLE);
1279 pmap_protect_tte(struct pmap *pm, struct pmap *pm2, struct tte *tp,
1285 data = atomic_clear_long(&tp->tte_data, TD_REF | TD_SW | TD_W);
1286 if ((data & TD_PV) != 0) {
1287 m = PHYS_TO_VM_PAGE(TD_PA(data));
1288 if ((data & TD_REF) != 0)
1289 vm_page_flag_set(m, PG_REFERENCED);
1290 if ((data & TD_W) != 0)
1297 * Set the physical protection on the specified range of this map as requested.
1300 pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
1305 CTR4(KTR_PMAP, "pmap_protect: ctx=%#lx sva=%#lx eva=%#lx prot=%#lx",
1306 pm->pm_context[curcpu], sva, eva, prot);
1308 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1309 pmap_remove(pm, sva, eva);
1313 if (prot & VM_PROT_WRITE)
1316 vm_page_lock_queues();
1318 if (eva - sva > PMAP_TSB_THRESH) {
1319 tsb_foreach(pm, NULL, sva, eva, pmap_protect_tte);
1320 tlb_context_demap(pm);
1322 for (va = sva; va < eva; va += PAGE_SIZE)
1323 if ((tp = tsb_tte_lookup(pm, va)) != NULL)
1324 pmap_protect_tte(pm, NULL, tp, va);
1325 tlb_range_demap(pm, sva, eva - 1);
1328 vm_page_unlock_queues();
1332 * Map the given physical page at the specified virtual address in the
1333 * target pmap with the protection requested. If specified the page
1334 * will be wired down.
1337 pmap_enter(pmap_t pm, vm_offset_t va, vm_prot_t access, vm_page_t m,
1338 vm_prot_t prot, boolean_t wired)
1341 vm_page_lock_queues();
1343 pmap_enter_locked(pm, va, m, prot, wired);
1344 vm_page_unlock_queues();
1349 * Map the given physical page at the specified virtual address in the
1350 * target pmap with the protection requested. If specified the page
1351 * will be wired down.
1353 * The page queues and pmap must be locked.
1356 pmap_enter_locked(pmap_t pm, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1364 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1365 PMAP_LOCK_ASSERT(pm, MA_OWNED);
1366 PMAP_STATS_INC(pmap_nenter);
1367 pa = VM_PAGE_TO_PHYS(m);
1370 * If this is a fake page from the device_pager, but it covers actual
1371 * physical memory, convert to the real backing page.
1373 if ((m->flags & PG_FICTITIOUS) != 0) {
1374 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
1375 if (pa >= phys_avail[i] && pa <= phys_avail[i + 1]) {
1376 m = PHYS_TO_VM_PAGE(pa);
1383 "pmap_enter_locked: ctx=%p m=%p va=%#lx pa=%#lx prot=%#x wired=%d",
1384 pm->pm_context[curcpu], m, va, pa, prot, wired);
1387 * If there is an existing mapping, and the physical address has not
1388 * changed, must be protection or wiring change.
1390 if ((tp = tsb_tte_lookup(pm, va)) != NULL && TTE_GET_PA(tp) == pa) {
1391 CTR0(KTR_PMAP, "pmap_enter_locked: update");
1392 PMAP_STATS_INC(pmap_nenter_update);
1395 * Wiring change, just update stats.
1398 if ((tp->tte_data & TD_WIRED) == 0) {
1399 tp->tte_data |= TD_WIRED;
1400 pm->pm_stats.wired_count++;
1403 if ((tp->tte_data & TD_WIRED) != 0) {
1404 tp->tte_data &= ~TD_WIRED;
1405 pm->pm_stats.wired_count--;
1410 * Save the old bits and clear the ones we're interested in.
1412 data = tp->tte_data;
1413 tp->tte_data &= ~(TD_EXEC | TD_SW | TD_W);
1416 * If we're turning off write permissions, sense modify status.
1418 if ((prot & VM_PROT_WRITE) != 0) {
1419 tp->tte_data |= TD_SW;
1421 tp->tte_data |= TD_W;
1422 vm_page_flag_set(m, PG_WRITEABLE);
1423 } else if ((data & TD_W) != 0)
1427 * If we're turning on execute permissions, flush the icache.
1429 if ((prot & VM_PROT_EXECUTE) != 0) {
1430 if ((data & TD_EXEC) == 0)
1431 icache_page_inval(pa);
1432 tp->tte_data |= TD_EXEC;
1436 * Delete the old mapping.
1438 tlb_page_demap(pm, TTE_GET_VA(tp));
1441 * If there is an existing mapping, but its for a different
1442 * phsyical address, delete the old mapping.
1445 CTR0(KTR_PMAP, "pmap_enter_locked: replace");
1446 PMAP_STATS_INC(pmap_nenter_replace);
1447 pmap_remove_tte(pm, NULL, tp, va);
1448 tlb_page_demap(pm, va);
1450 CTR0(KTR_PMAP, "pmap_enter_locked: new");
1451 PMAP_STATS_INC(pmap_nenter_new);
1455 * Now set up the data and install the new mapping.
1457 data = TD_V | TD_8K | TD_PA(pa);
1458 if (pm == kernel_pmap)
1460 if ((prot & VM_PROT_WRITE) != 0) {
1462 vm_page_flag_set(m, PG_WRITEABLE);
1464 if (prot & VM_PROT_EXECUTE) {
1466 icache_page_inval(pa);
1470 * If its wired update stats. We also don't need reference or
1471 * modify tracking for wired mappings, so set the bits now.
1474 pm->pm_stats.wired_count++;
1475 data |= TD_REF | TD_WIRED;
1476 if ((prot & VM_PROT_WRITE) != 0)
1480 tsb_tte_enter(pm, m, va, TS_8K, data);
1485 * Maps a sequence of resident pages belonging to the same object.
1486 * The sequence begins with the given page m_start. This page is
1487 * mapped at the given virtual address start. Each subsequent page is
1488 * mapped at a virtual address that is offset from start by the same
1489 * amount as the page is offset from m_start within the object. The
1490 * last page in the sequence is the page with the largest offset from
1491 * m_start that can be mapped at a virtual address less than the given
1492 * virtual address end. Not every virtual page between start and end
1493 * is mapped; only those for which a resident page exists with the
1494 * corresponding offset from m_start are mapped.
1497 pmap_enter_object(pmap_t pm, vm_offset_t start, vm_offset_t end,
1498 vm_page_t m_start, vm_prot_t prot)
1501 vm_pindex_t diff, psize;
1503 psize = atop(end - start);
1506 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1507 pmap_enter_locked(pm, start + ptoa(diff), m, prot &
1508 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1509 m = TAILQ_NEXT(m, listq);
1515 pmap_enter_quick(pmap_t pm, vm_offset_t va, vm_page_t m, vm_prot_t prot)
1519 pmap_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1525 pmap_object_init_pt(pmap_t pm, vm_offset_t addr, vm_object_t object,
1526 vm_pindex_t pindex, vm_size_t size)
1529 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED);
1530 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
1531 ("pmap_object_init_pt: non-device object"));
1535 * Change the wiring attribute for a map/virtual-address pair.
1536 * The mapping must already exist in the pmap.
1539 pmap_change_wiring(pmap_t pm, vm_offset_t va, boolean_t wired)
1545 if ((tp = tsb_tte_lookup(pm, va)) != NULL) {
1547 data = atomic_set_long(&tp->tte_data, TD_WIRED);
1548 if ((data & TD_WIRED) == 0)
1549 pm->pm_stats.wired_count++;
1551 data = atomic_clear_long(&tp->tte_data, TD_WIRED);
1552 if ((data & TD_WIRED) != 0)
1553 pm->pm_stats.wired_count--;
1560 pmap_copy_tte(pmap_t src_pmap, pmap_t dst_pmap, struct tte *tp,
1566 if ((tp->tte_data & TD_FAKE) != 0)
1568 if (tsb_tte_lookup(dst_pmap, va) == NULL) {
1569 data = tp->tte_data &
1570 ~(TD_PV | TD_REF | TD_SW | TD_CV | TD_W);
1571 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp));
1572 tsb_tte_enter(dst_pmap, m, va, TS_8K, data);
1578 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
1579 vm_size_t len, vm_offset_t src_addr)
1584 if (dst_addr != src_addr)
1586 vm_page_lock_queues();
1587 if (dst_pmap < src_pmap) {
1588 PMAP_LOCK(dst_pmap);
1589 PMAP_LOCK(src_pmap);
1591 PMAP_LOCK(src_pmap);
1592 PMAP_LOCK(dst_pmap);
1594 if (len > PMAP_TSB_THRESH) {
1595 tsb_foreach(src_pmap, dst_pmap, src_addr, src_addr + len,
1597 tlb_context_demap(dst_pmap);
1599 for (va = src_addr; va < src_addr + len; va += PAGE_SIZE)
1600 if ((tp = tsb_tte_lookup(src_pmap, va)) != NULL)
1601 pmap_copy_tte(src_pmap, dst_pmap, tp, va);
1602 tlb_range_demap(dst_pmap, src_addr, src_addr + len - 1);
1604 vm_page_unlock_queues();
1605 PMAP_UNLOCK(src_pmap);
1606 PMAP_UNLOCK(dst_pmap);
1610 pmap_zero_page(vm_page_t m)
1616 KASSERT((m->flags & PG_FICTITIOUS) == 0,
1617 ("pmap_zero_page: fake page"));
1618 PMAP_STATS_INC(pmap_nzero_page);
1619 pa = VM_PAGE_TO_PHYS(m);
1620 if (dcache_color_ignore != 0 || m->md.color == DCACHE_COLOR(pa)) {
1621 PMAP_STATS_INC(pmap_nzero_page_c);
1622 va = TLB_PHYS_TO_DIRECT(pa);
1623 cpu_block_zero((void *)va, PAGE_SIZE);
1624 } else if (m->md.color == -1) {
1625 PMAP_STATS_INC(pmap_nzero_page_nc);
1626 aszero(ASI_PHYS_USE_EC, pa, PAGE_SIZE);
1628 PMAP_STATS_INC(pmap_nzero_page_oc);
1629 PMAP_LOCK(kernel_pmap);
1630 va = pmap_temp_map_1 + (m->md.color * PAGE_SIZE);
1631 tp = tsb_kvtotte(va);
1632 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_CP | TD_CV | TD_W;
1633 tp->tte_vpn = TV_VPN(va, TS_8K);
1634 cpu_block_zero((void *)va, PAGE_SIZE);
1635 tlb_page_demap(kernel_pmap, va);
1636 PMAP_UNLOCK(kernel_pmap);
1641 pmap_zero_page_area(vm_page_t m, int off, int size)
1647 KASSERT((m->flags & PG_FICTITIOUS) == 0,
1648 ("pmap_zero_page_area: fake page"));
1649 KASSERT(off + size <= PAGE_SIZE, ("pmap_zero_page_area: bad off/size"));
1650 PMAP_STATS_INC(pmap_nzero_page_area);
1651 pa = VM_PAGE_TO_PHYS(m);
1652 if (dcache_color_ignore != 0 || m->md.color == DCACHE_COLOR(pa)) {
1653 PMAP_STATS_INC(pmap_nzero_page_area_c);
1654 va = TLB_PHYS_TO_DIRECT(pa);
1655 bzero((void *)(va + off), size);
1656 } else if (m->md.color == -1) {
1657 PMAP_STATS_INC(pmap_nzero_page_area_nc);
1658 aszero(ASI_PHYS_USE_EC, pa + off, size);
1660 PMAP_STATS_INC(pmap_nzero_page_area_oc);
1661 PMAP_LOCK(kernel_pmap);
1662 va = pmap_temp_map_1 + (m->md.color * PAGE_SIZE);
1663 tp = tsb_kvtotte(va);
1664 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_CP | TD_CV | TD_W;
1665 tp->tte_vpn = TV_VPN(va, TS_8K);
1666 bzero((void *)(va + off), size);
1667 tlb_page_demap(kernel_pmap, va);
1668 PMAP_UNLOCK(kernel_pmap);
1673 pmap_zero_page_idle(vm_page_t m)
1679 KASSERT((m->flags & PG_FICTITIOUS) == 0,
1680 ("pmap_zero_page_idle: fake page"));
1681 PMAP_STATS_INC(pmap_nzero_page_idle);
1682 pa = VM_PAGE_TO_PHYS(m);
1683 if (dcache_color_ignore != 0 || m->md.color == DCACHE_COLOR(pa)) {
1684 PMAP_STATS_INC(pmap_nzero_page_idle_c);
1685 va = TLB_PHYS_TO_DIRECT(pa);
1686 cpu_block_zero((void *)va, PAGE_SIZE);
1687 } else if (m->md.color == -1) {
1688 PMAP_STATS_INC(pmap_nzero_page_idle_nc);
1689 aszero(ASI_PHYS_USE_EC, pa, PAGE_SIZE);
1691 PMAP_STATS_INC(pmap_nzero_page_idle_oc);
1692 va = pmap_idle_map + (m->md.color * PAGE_SIZE);
1693 tp = tsb_kvtotte(va);
1694 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_CP | TD_CV | TD_W;
1695 tp->tte_vpn = TV_VPN(va, TS_8K);
1696 cpu_block_zero((void *)va, PAGE_SIZE);
1697 tlb_page_demap(kernel_pmap, va);
1702 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
1710 KASSERT((mdst->flags & PG_FICTITIOUS) == 0,
1711 ("pmap_copy_page: fake dst page"));
1712 KASSERT((msrc->flags & PG_FICTITIOUS) == 0,
1713 ("pmap_copy_page: fake src page"));
1714 PMAP_STATS_INC(pmap_ncopy_page);
1715 pdst = VM_PAGE_TO_PHYS(mdst);
1716 psrc = VM_PAGE_TO_PHYS(msrc);
1717 if (dcache_color_ignore != 0 ||
1718 (msrc->md.color == DCACHE_COLOR(psrc) &&
1719 mdst->md.color == DCACHE_COLOR(pdst))) {
1720 PMAP_STATS_INC(pmap_ncopy_page_c);
1721 vdst = TLB_PHYS_TO_DIRECT(pdst);
1722 vsrc = TLB_PHYS_TO_DIRECT(psrc);
1723 cpu_block_copy((void *)vsrc, (void *)vdst, PAGE_SIZE);
1724 } else if (msrc->md.color == -1 && mdst->md.color == -1) {
1725 PMAP_STATS_INC(pmap_ncopy_page_nc);
1726 ascopy(ASI_PHYS_USE_EC, psrc, pdst, PAGE_SIZE);
1727 } else if (msrc->md.color == -1) {
1728 if (mdst->md.color == DCACHE_COLOR(pdst)) {
1729 PMAP_STATS_INC(pmap_ncopy_page_dc);
1730 vdst = TLB_PHYS_TO_DIRECT(pdst);
1731 ascopyfrom(ASI_PHYS_USE_EC, psrc, (void *)vdst,
1734 PMAP_STATS_INC(pmap_ncopy_page_doc);
1735 PMAP_LOCK(kernel_pmap);
1736 vdst = pmap_temp_map_1 + (mdst->md.color * PAGE_SIZE);
1737 tp = tsb_kvtotte(vdst);
1739 TD_V | TD_8K | TD_PA(pdst) | TD_CP | TD_CV | TD_W;
1740 tp->tte_vpn = TV_VPN(vdst, TS_8K);
1741 ascopyfrom(ASI_PHYS_USE_EC, psrc, (void *)vdst,
1743 tlb_page_demap(kernel_pmap, vdst);
1744 PMAP_UNLOCK(kernel_pmap);
1746 } else if (mdst->md.color == -1) {
1747 if (msrc->md.color == DCACHE_COLOR(psrc)) {
1748 PMAP_STATS_INC(pmap_ncopy_page_sc);
1749 vsrc = TLB_PHYS_TO_DIRECT(psrc);
1750 ascopyto((void *)vsrc, ASI_PHYS_USE_EC, pdst,
1753 PMAP_STATS_INC(pmap_ncopy_page_soc);
1754 PMAP_LOCK(kernel_pmap);
1755 vsrc = pmap_temp_map_1 + (msrc->md.color * PAGE_SIZE);
1756 tp = tsb_kvtotte(vsrc);
1758 TD_V | TD_8K | TD_PA(psrc) | TD_CP | TD_CV | TD_W;
1759 tp->tte_vpn = TV_VPN(vsrc, TS_8K);
1760 ascopyto((void *)vsrc, ASI_PHYS_USE_EC, pdst,
1762 tlb_page_demap(kernel_pmap, vsrc);
1763 PMAP_UNLOCK(kernel_pmap);
1766 PMAP_STATS_INC(pmap_ncopy_page_oc);
1767 PMAP_LOCK(kernel_pmap);
1768 vdst = pmap_temp_map_1 + (mdst->md.color * PAGE_SIZE);
1769 tp = tsb_kvtotte(vdst);
1771 TD_V | TD_8K | TD_PA(pdst) | TD_CP | TD_CV | TD_W;
1772 tp->tte_vpn = TV_VPN(vdst, TS_8K);
1773 vsrc = pmap_temp_map_2 + (msrc->md.color * PAGE_SIZE);
1774 tp = tsb_kvtotte(vsrc);
1776 TD_V | TD_8K | TD_PA(psrc) | TD_CP | TD_CV | TD_W;
1777 tp->tte_vpn = TV_VPN(vsrc, TS_8K);
1778 cpu_block_copy((void *)vsrc, (void *)vdst, PAGE_SIZE);
1779 tlb_page_demap(kernel_pmap, vdst);
1780 tlb_page_demap(kernel_pmap, vsrc);
1781 PMAP_UNLOCK(kernel_pmap);
1786 * Returns true if the pmap's pv is one of the first
1787 * 16 pvs linked to from this page. This count may
1788 * be changed upwards or downwards in the future; it
1789 * is only necessary that true be returned for a small
1790 * subset of pmaps for proper page aging.
1793 pmap_page_exists_quick(pmap_t pm, vm_page_t m)
1798 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1799 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1802 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1803 if ((tp->tte_data & TD_PV) == 0)
1805 if (TTE_GET_PMAP(tp) == pm)
1814 * Return the number of managed mappings to the given physical page
1818 pmap_page_wired_mappings(vm_page_t m)
1824 if ((m->flags & PG_FICTITIOUS) != 0)
1826 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1827 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link)
1828 if ((tp->tte_data & (TD_PV | TD_WIRED)) == (TD_PV | TD_WIRED))
1834 * Remove all pages from specified address space, this aids process exit
1835 * speeds. This is much faster than pmap_remove n the case of running down
1836 * an entire address space. Only works for the current pmap.
1839 pmap_remove_pages(pmap_t pm)
1845 * Returns TRUE if the given page has a managed mapping.
1848 pmap_page_is_mapped(vm_page_t m)
1852 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1854 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1855 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link)
1856 if ((tp->tte_data & TD_PV) != 0)
1862 * Return a count of reference bits for a page, clearing those bits.
1863 * It is not necessary for every reference bit to be cleared, but it
1864 * is necessary that 0 only be returned when there are truly no
1865 * reference bits set.
1867 * XXX: The exact number of bits to check and clear is a matter that
1868 * should be tested and standardized at some point in the future for
1869 * optimal aging of shared pages.
1872 pmap_ts_referenced(vm_page_t m)
1880 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1881 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1884 if ((tp = TAILQ_FIRST(&m->md.tte_list)) != NULL) {
1887 tpn = TAILQ_NEXT(tp, tte_link);
1888 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link);
1889 TAILQ_INSERT_TAIL(&m->md.tte_list, tp, tte_link);
1890 if ((tp->tte_data & TD_PV) == 0)
1892 data = atomic_clear_long(&tp->tte_data, TD_REF);
1893 if ((data & TD_REF) != 0 && ++count > 4)
1895 } while ((tp = tpn) != NULL && tp != tpf);
1901 pmap_is_modified(vm_page_t m)
1905 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1906 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1908 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1909 if ((tp->tte_data & TD_PV) == 0)
1911 if ((tp->tte_data & TD_W) != 0)
1918 * pmap_is_prefaultable:
1920 * Return whether or not the specified virtual address is elgible
1924 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
1929 rv = tsb_tte_lookup(pmap, addr) == NULL;
1935 pmap_clear_modify(vm_page_t m)
1940 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1941 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1943 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1944 if ((tp->tte_data & TD_PV) == 0)
1946 data = atomic_clear_long(&tp->tte_data, TD_W);
1947 if ((data & TD_W) != 0)
1948 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
1953 pmap_clear_reference(vm_page_t m)
1958 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1959 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1961 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1962 if ((tp->tte_data & TD_PV) == 0)
1964 data = atomic_clear_long(&tp->tte_data, TD_REF);
1965 if ((data & TD_REF) != 0)
1966 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
1971 pmap_remove_write(vm_page_t m)
1976 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1977 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 ||
1978 (m->flags & PG_WRITEABLE) == 0)
1980 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) {
1981 if ((tp->tte_data & TD_PV) == 0)
1983 data = atomic_clear_long(&tp->tte_data, TD_SW | TD_W);
1984 if ((data & TD_W) != 0) {
1986 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp));
1989 vm_page_flag_clear(m, PG_WRITEABLE);
1993 pmap_mincore(pmap_t pm, vm_offset_t addr)
2001 * Activate a user pmap. The pmap must be activated before its address space
2002 * can be accessed in any way.
2005 pmap_activate(struct thread *td)
2011 vm = td->td_proc->p_vmspace;
2012 pm = vmspace_pmap(vm);
2014 mtx_lock_spin(&sched_lock);
2016 context = PCPU_GET(tlb_ctx);
2017 if (context == PCPU_GET(tlb_ctx_max)) {
2019 context = PCPU_GET(tlb_ctx_min);
2021 PCPU_SET(tlb_ctx, context + 1);
2023 pm->pm_context[curcpu] = context;
2024 pm->pm_active |= PCPU_GET(cpumask);
2027 stxa(AA_DMMU_TSB, ASI_DMMU, pm->pm_tsb);
2028 stxa(AA_IMMU_TSB, ASI_IMMU, pm->pm_tsb);
2029 stxa(AA_DMMU_PCXR, ASI_DMMU, (ldxa(AA_DMMU_PCXR, ASI_DMMU) &
2030 TLB_CXR_PGSZ_MASK) | context);
2033 mtx_unlock_spin(&sched_lock);
2037 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
2043 * Increase the starting virtual address of the given mapping if a
2044 * different alignment might result in more superpage mappings.
2047 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
2048 vm_offset_t *addr, vm_size_t size)