2 * Copyright (c) 2006 Kip Macy
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef _MACHINE_HV_API_H
30 #define _MACHINE_HV_API_H
32 typedef uint64_t devhandle_t;
33 typedef uint64_t pci_device_t;
34 typedef uint32_t pci_config_offset_t;
35 typedef uint8_t pci_config_size_t;
37 typedef uint64_t tsbid_t;
38 typedef uint32_t pages_t;
39 typedef enum io_attributes {
40 PCI_MAP_ATTR_READ = (uint32_t)0x01,
41 PCI_MAP_ATTR_WRITE = (uint32_t)0x02,
43 typedef enum io_sync_direction {
44 IO_SYNC_DEVICE = (uint32_t)0x01,
45 IO_SYNC_CPU = (uint32_t)0x02,
46 } io_sync_direction_t;
47 typedef uint64_t io_page_list_t;
48 typedef uint64_t r_addr_t;
49 typedef uint64_t io_addr_t;
52 * Section 10 Domain Services
55 extern void hv_mach_sir(void) __dead2;
56 extern void hv_mach_exit(uint64_t exit_code) __dead2;
57 extern uint64_t hv_mach_desc(uint64_t buffer_ra, uint64_t *buffer_sizep);
58 extern uint64_t hv_mach_watchdog(uint64_t timeout, uint64_t *time_remaining);
61 * Section 11 CPU Services
64 extern uint64_t hv_cpu_yield(void);
65 extern uint64_t hv_cpu_state(uint64_t cpuid, uint64_t *state);
66 extern uint64_t hv_cpu_mondo_send(int ncpu, vm_paddr_t cpulist_ra);
67 extern uint64_t hv_cpu_qconf(int queue, vm_paddr_t ra, int nentries);
70 * Section 12 MMU Services
73 * TSB description structure for MMU_TSB_CTX0 and MMU_TSB_CTXNON0.
75 typedef struct hv_tsb_info {
76 uint16_t hti_idxpgsz; /* page size used for index shift in TSB */
77 uint16_t hti_assoc; /* associativity of TSB */
78 uint32_t hti_ntte; /* size of TSB in TTEs */
79 uint32_t hti_ctx_index; /* context index */
80 uint32_t hti_pgszs; /* page size bitmask */
81 uint64_t hti_ra; /* real address of TSB base */
82 uint64_t hti_rsvd; /* reserved */
86 extern uint64_t hv_mmu_tsb_ctx0(uint64_t, uint64_t);
87 extern uint64_t hv_mmu_tsb_ctxnon0(uint64_t, uint64_t);
88 extern uint64_t hv_mmu_map_perm_addr(vm_offset_t va, uint64_t, tte_t tte, uint64_t flags);
91 * Section 13 Cache and Memory Services
94 extern uint64_t hv_mem_scrub(vm_paddr_t ra, uint64_t length, uint64_t *scrubbed);
97 * Section 14 Device Interrupt Services
99 extern uint64_t hv_intr_devino_to_sysino(devhandle_t dev_hdl, uint32_t devino, uint64_t *sysino);
100 extern uint64_t hv_intr_getenabled(uint64_t sysino, int *enabled);
101 extern uint64_t hv_intr_setenabled(uint64_t sysino, int enabled);
102 extern uint64_t hv_intr_getstate(uint64_t sysino, int *state);
103 extern uint64_t hv_intr_setstate(uint64_t sysino, int state);
104 extern uint64_t hv_intr_gettarget(uint64_t sysino, int *cpuid);
105 extern uint64_t hv_intr_settarget(uint64_t sysino, int cpuid);
107 extern uint64_t hv_vintr_getcookie(devhandle_t dh, uint64_t devino, uint64_t *cookie);
108 extern uint64_t hv_vintr_setcookie(devhandle_t dh, uint64_t devino, uint64_t cookie);
109 extern uint64_t hv_vintr_getenabled(devhandle_t dh, uint64_t devino, int *enabled);
110 extern uint64_t hv_vintr_setenabled(devhandle_t dh, uint64_t devino, int enabled);
111 extern uint64_t hv_vintr_getstate(devhandle_t dh, uint64_t devino, int *state);
112 extern uint64_t hv_vintr_setstate(devhandle_t dh, uint64_t devino, int state);
113 extern uint64_t hv_vintr_gettarget(devhandle_t dh, uint64_t devino, int *cpuid);
114 extern uint64_t hv_vintr_settarget(devhandle_t dh, uint64_t devino, int cpuid);
118 * Section 15 Time of Day Services
121 extern uint64_t hv_tod_get(uint64_t *seconds);
122 extern uint64_t hv_tod_set(uint64_t);
125 * Section 16 Console Services
128 extern int64_t hv_cons_putchar(uint8_t);
129 extern int64_t hv_cons_getchar(uint8_t *);
130 extern int64_t hv_cons_write(uint64_t buf_raddr, uint64_t size, uint64_t *nwritten);
131 extern int64_t hv_cons_read(uint64_t buf_raddr, uint64_t size, uint64_t *nread);
133 extern void hv_cnputs(char *);
136 * Section 17 Core Dump Services
139 extern uint64_t hv_dump_buf_update(uint64_t, uint64_t, uint64_t *);
143 * Section 18 Trap Trace Services
146 typedef struct trap_trace_entry {
147 uint8_t tte_type; /* Hypervisor or guest entry. */
148 uint8_t tte_hpstat; /* Hyper-privileged state. */
149 uint8_t tte_tl; /* Trap level. */
150 uint8_t tte_gl; /* Global register level. */
151 uint16_t tte_tt; /* Trap type.*/
152 uint16_t tte_tag; /* Extended trap identifier. */
153 uint64_t tte_tstate; /* Trap state. */
154 uint64_t tte_tick; /* Tick. */
155 uint64_t tte_tpc; /* Trap PC. */
156 uint64_t tte_f1; /* Entry specific. */
157 uint64_t tte_f2; /* Entry specific. */
158 uint64_t tte_f3; /* Entry specific. */
159 uint64_t tte_f4; /* Entry specific. */
160 } trap_trace_entry_t;
162 extern uint64_t hv_ttrace_buf_info(uint64_t *, uint64_t *);
163 extern uint64_t hv_ttrace_buf_conf(uint64_t, uint64_t, uint64_t *);
164 extern uint64_t hv_ttrace_enable(uint64_t, uint64_t *);
165 extern uint64_t hv_ttrace_freeze(uint64_t, uint64_t *);
166 extern uint64_t hv_ttrace_addentry(uint64_t, uint64_t, uint64_t, uint64_t, uint64_t);
169 * Section 19 Logical Domain Channel Services
172 typedef struct ldc_state_info {
173 uint64_t lsi_head_offset;
174 uint64_t lsi_tail_offset;
175 uint64_t lsi_channel_state;
178 #define LDC_CHANNEL_DOWN 0
179 #define LDC_CHANNEL_UP 1
181 extern uint64_t hv_ldc_tx_qconf(uint64_t ldc_id, uint64_t base_raddr, uint64_t nentries);
182 extern uint64_t hv_ldc_tx_qinfo(uint64_t ldc_id, uint64_t *base_raddr, uint64_t *nentries);
183 extern uint64_t hv_ldc_tx_get_state(uint64_t ldc_id, ldc_state_info_t *info);
184 extern uint64_t hv_ldc_tx_set_qtail(uint64_t ldc_id, uint64_t tail_offset);
185 extern uint64_t hv_ldc_rx_get_state(uint64_t ldc_id, ldc_state_info_t *info);
186 extern uint64_t hv_ldc_rx_qconf(uint64_t ldc_id, uint64_t base_raddr, uint64_t nentries);
187 extern uint64_t hv_ldc_rx_qinfo(uint64_t ldc_id, uint64_t *base_raddr, uint64_t *nentries);
188 extern uint64_t hv_ldc_rx_set_qhead(uint64_t ldc_id, uint64_t head_offset);
192 * Section 20 PCI I/O Services
196 typedef union pci_cfg_data {
203 extern uint64_t hv_pci_iommu_map(devhandle_t dh, uint64_t tsbid, uint64_t nttes, io_attributes_t io_attributes,
204 io_page_list_t io_page_list, pages_t *nttes_mapped);
205 extern uint64_t hv_pci_iommu_demap(devhandle_t dh, uint64_t tsbid, uint64_t nttes, pages_t *nttes_demapped);
206 extern uint64_t hv_pci_iommu_getmap(devhandle_t dh, uint64_t tsbid, io_attributes_t *io_attributes,
208 extern uint64_t hv_pci_iommu_getbypass(devhandle_t dh, vm_paddr_t ra, uint64_t io_attributes, uint64_t *io_addr);
209 extern uint64_t hv_pci_config_get(devhandle_t dh, uint64_t pci_device, uint64_t pci_config_offset, uint64_t size,
210 pci_cfg_data_t *data);
211 extern uint64_t hv_pci_config_put(devhandle_t dh, uint64_t pci_device, uint64_t pci_config_offset, uint64_t size,
212 pci_cfg_data_t data);
213 extern uint64_t hv_pci_peek(devhandle_t dh, vm_paddr_t ra, uint64_t size, uint32_t *error_flag, uint64_t *data);
214 extern uint64_t hv_pci_poke(devhandle_t dh, vm_paddr_t ra, uint64_t size, uint64_t data, uint64_t pci_device,
215 uint32_t *error_flag);
216 extern uint64_t hv_pci_dma_sync(devhandle_t dh, vm_paddr_t ra, uint64_t size, uint64_t io_sync_direction,
221 * Section 21 MSI Services
226 * Section 22 UltraSPARC T1 Performance Counters
231 * Section 23 UltraSPARC T1 MMU Statistics Counters
238 extern void hv_magic_trap_on(void);
239 extern void hv_magic_trap_off(void);
240 extern int hv_sim_read(uint64_t offset, vm_paddr_t buffer_ra, uint64_t size);
241 extern int hv_sim_write(uint64_t offset, vm_paddr_t buffer_ra, uint64_t size);
243 #endif /* _MACHINE_HV_API_H */