2 * Copyright (c) 2005 Bruno Ducrot
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * This driver is based upon information found by examining speedstep-0.5
27 * from Marc Lehman, which includes all the reverse engineering effort of
28 * Malik Martin (function 1 and 2 of the GSI).
30 * The correct way for the OS to take ownership from the BIOS was found by
31 * Hiroshi Miura (function 0 of the GSI).
33 * Finally, the int 15h call interface was (partially) documented by Intel.
35 * Many thanks to Jon Noack for testing and debugging this driver.
38 #include <sys/cdefs.h>
39 __FBSDID("$FreeBSD$");
41 #include <sys/param.h>
44 #include <sys/kernel.h>
45 #include <sys/module.h>
46 #include <sys/systm.h>
48 #include <machine/bus.h>
49 #include <machine/cputypes.h>
50 #include <machine/md_var.h>
51 #include <machine/vm86.h>
53 #include <dev/pci/pcivar.h>
54 #include <dev/pci/pcireg.h>
59 #include "cpufreq_if.h"
62 #define DPRINT(dev, x...) device_printf(dev, x)
64 #define DPRINT(dev, x...)
73 struct cf_setting sets[2]; /* Only two settings. */
76 static char smist_magic[] = "Copyright (c) 1999 Intel Corporation";
78 static void smist_identify(driver_t *driver, device_t parent);
79 static int smist_probe(device_t dev);
80 static int smist_attach(device_t dev);
81 static int smist_detach(device_t dev);
82 static int smist_settings(device_t dev, struct cf_setting *sets,
84 static int smist_set(device_t dev, const struct cf_setting *set);
85 static int smist_get(device_t dev, struct cf_setting *set);
86 static int smist_type(device_t dev, int *type);
88 static device_method_t smist_methods[] = {
89 /* Device interface */
90 DEVMETHOD(device_identify, smist_identify),
91 DEVMETHOD(device_probe, smist_probe),
92 DEVMETHOD(device_attach, smist_attach),
93 DEVMETHOD(device_detach, smist_detach),
95 /* cpufreq interface */
96 DEVMETHOD(cpufreq_drv_set, smist_set),
97 DEVMETHOD(cpufreq_drv_get, smist_get),
98 DEVMETHOD(cpufreq_drv_type, smist_type),
99 DEVMETHOD(cpufreq_drv_settings, smist_settings),
104 static driver_t smist_driver = {
105 "smist", smist_methods, sizeof(struct smist_softc)
107 static devclass_t smist_devclass;
108 DRIVER_MODULE(smist, cpu, smist_driver, smist_devclass, 0, 0);
110 struct piix4_pci_device {
116 static struct piix4_pci_device piix4_pci_devices[] = {
117 {0x8086, 0x7113, "Intel PIIX4 ISA bridge"},
118 {0x8086, 0x719b, "Intel PIIX4 ISA bridge (embedded in MX440 chipset)"},
123 #define SET_OWNERSHIP 0
128 int15_gsic_call(int *sig, int *smi_cmd, int *command, int *smi_data, int *flags)
130 struct vm86frame vmf;
132 bzero(&vmf, sizeof(vmf));
133 vmf.vmf_eax = 0x0000E980; /* IST support */
134 vmf.vmf_edx = 0x47534943; /* 'GSIC' in ASCII */
135 vm86_intcall(0x15, &vmf);
137 if (vmf.vmf_eax == 0x47534943) {
139 *smi_cmd = vmf.vmf_ebx & 0xff;
140 *command = (vmf.vmf_ebx >> 16) & 0xff;
141 *smi_data = vmf.vmf_ecx;
142 *flags = vmf.vmf_edx;
154 /* Temporary structure to hold mapped page and status. */
155 struct set_ownership_data {
162 /* Perform actual SMI call to enable SpeedStep. */
164 set_ownership_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
166 struct set_ownership_data *data;
170 data->result = error;
174 /* Copy in the magic string and send it by writing to the SMI port. */
175 strlcpy(data->buf, smist_magic, PAGE_SIZE);
177 "movl $-1, %%edi\n\t"
179 : "=D" (data->result)
180 : "a" (data->command),
184 "S" ((uint32_t)segs[0].ds_addr)
189 set_ownership(device_t dev)
191 struct smist_softc *sc;
192 struct set_ownership_data cb_data;
197 * Specify the region to store the magic string. Since its address is
198 * passed to the BIOS in a 32-bit register, we have to make sure it is
199 * located in a physical page below 4 GB (i.e., for PAE.)
201 sc = device_get_softc(dev);
202 if (bus_dma_tag_create(/*parent*/ NULL,
203 /*alignment*/ PAGE_SIZE, /*no boundary*/ 0,
204 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, /*highaddr*/ BUS_SPACE_MAXADDR,
205 NULL, NULL, /*maxsize*/ PAGE_SIZE, /*segments*/ 1,
206 /*maxsegsize*/ PAGE_SIZE, 0, busdma_lock_mutex, &Giant,
208 device_printf(dev, "can't create mem tag\n");
211 if (bus_dmamem_alloc(tag, &cb_data.buf, BUS_DMA_NOWAIT, &map) != 0) {
212 bus_dma_tag_destroy(tag);
213 device_printf(dev, "can't alloc mapped mem\n");
217 /* Load the physical page map and take ownership in the callback. */
218 cb_data.smi_cmd = sc->smi_cmd;
219 cb_data.command = sc->command;
220 if (bus_dmamap_load(tag, map, cb_data.buf, PAGE_SIZE, set_ownership_cb,
221 &cb_data, BUS_DMA_NOWAIT) != 0) {
222 bus_dmamem_free(tag, cb_data.buf, map);
223 bus_dma_tag_destroy(tag);
224 device_printf(dev, "can't load mem\n");
227 DPRINT(dev, "taking ownership over BIOS return %d\n", cb_data.result);
228 bus_dmamap_unload(tag, map);
229 bus_dmamem_free(tag, cb_data.buf, map);
230 bus_dma_tag_destroy(tag);
231 return (cb_data.result ? ENXIO : 0);
235 getset_state(struct smist_softc *sc, int *state, int function)
244 if (function != GET_STATE && function != SET_STATE)
247 DPRINT(sc->dev, "calling GSI\n");
250 "movl $-1, %%edi\n\t"
261 DPRINT(sc->dev, "GSI returned: eax %.8x ebx %.8x edi %.8x\n",
262 eax, new_state, result);
264 *state = new_state & 1;
280 smist_identify(driver_t *driver, device_t parent)
282 struct piix4_pci_device *id;
283 device_t piix4 = NULL;
285 if (resource_disabled("ichst", 0))
288 /* Check for a supported processor */
289 if (cpu_vendor_id != CPU_VENDOR_INTEL)
291 switch (cpu_id & 0xff0) {
292 case 0x680: /* Pentium III [coppermine] */
293 case 0x6a0: /* Pentium III [Tualatin] */
299 /* Check for a supported PCI-ISA bridge */
300 for (id = piix4_pci_devices; id->desc != NULL; ++id) {
301 if ((piix4 = pci_find_device(id->vendor, id->device)) != NULL)
308 printf("smist: found supported isa bridge %s\n", id->desc);
310 if (device_find_child(parent, "smist", -1) != NULL)
312 if (BUS_ADD_CHILD(parent, 30, "smist", -1) == NULL)
313 device_printf(parent, "smist: add child failed\n");
317 smist_probe(device_t dev)
319 struct smist_softc *sc;
320 device_t ichss_dev, perf_dev;
321 int sig, smi_cmd, command, smi_data, flags;
325 if (resource_disabled("smist", 0))
328 sc = device_get_softc(dev);
331 * If the ACPI perf or ICH SpeedStep drivers have attached and not
332 * just offering info, let them manage things.
334 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
335 if (perf_dev && device_is_attached(perf_dev)) {
336 rv = CPUFREQ_DRV_TYPE(perf_dev, &type);
337 if (rv == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0)
340 ichss_dev = device_find_child(device_get_parent(dev), "ichss", -1);
341 if (ichss_dev && device_is_attached(ichss_dev))
344 int15_gsic_call(&sig, &smi_cmd, &command, &smi_data, &flags);
346 device_printf(dev, "sig %.8x smi_cmd %.4x command %.2x "
347 "smi_data %.4x flags %.8x\n",
348 sig, smi_cmd, command, smi_data, flags);
351 sc->smi_cmd = smi_cmd;
352 sc->smi_data = smi_data;
355 * Sometimes int 15h 'GSIC' returns 0x80 for command, when
356 * it is actually 0x82. The Windows driver will overwrite
357 * this value given by the registry.
359 if (command == 0x80) {
361 "GSIC returned cmd 0x80, should be 0x82\n");
364 sc->command = (sig & 0xffffff00) | (command & 0xff);
367 /* Give some default values */
370 sc->command = 0x47534982;
374 device_set_desc(dev, "SpeedStep SMI");
380 smist_attach(device_t dev)
382 struct smist_softc *sc;
384 sc = device_get_softc(dev);
387 /* If we can't take ownership over BIOS, then bail out */
388 if (set_ownership(dev) != 0)
391 /* Setup some defaults for our exported settings. */
392 sc->sets[0].freq = CPUFREQ_VAL_UNKNOWN;
393 sc->sets[0].volts = CPUFREQ_VAL_UNKNOWN;
394 sc->sets[0].power = CPUFREQ_VAL_UNKNOWN;
395 sc->sets[0].lat = 1000;
396 sc->sets[0].dev = dev;
397 sc->sets[1] = sc->sets[0];
399 cpufreq_register(dev);
405 smist_detach(device_t dev)
408 return (cpufreq_unregister(dev));
412 smist_settings(device_t dev, struct cf_setting *sets, int *count)
414 struct smist_softc *sc;
415 struct cf_setting set;
418 if (sets == NULL || count == NULL)
424 sc = device_get_softc(dev);
427 * Estimate frequencies for both levels, temporarily switching to
428 * the other one if we haven't calibrated it yet.
430 for (i = 0; i < 2; i++) {
431 if (sc->sets[i].freq == CPUFREQ_VAL_UNKNOWN) {
432 first = (i == 0) ? 1 : 0;
433 smist_set(dev, &sc->sets[i]);
434 smist_get(dev, &set);
435 smist_set(dev, &sc->sets[first]);
439 bcopy(sc->sets, sets, sizeof(sc->sets));
446 smist_set(device_t dev, const struct cf_setting *set)
448 struct smist_softc *sc;
449 int rv, state, req_state, try;
451 /* Look up appropriate bit value based on frequency. */
452 sc = device_get_softc(dev);
453 if (CPUFREQ_CMP(set->freq, sc->sets[0].freq))
455 else if (CPUFREQ_CMP(set->freq, sc->sets[1].freq))
460 DPRINT(dev, "requested setting %d\n", req_state);
462 rv = getset_state(sc, &state, GET_STATE);
463 if (state == req_state)
468 rv = getset_state(sc, &req_state, SET_STATE);
470 /* Sleep for 200 microseconds. This value is just a guess. */
473 } while (rv && --try);
474 DPRINT(dev, "set_state return %d, tried %d times\n",
481 smist_get(device_t dev, struct cf_setting *set)
483 struct smist_softc *sc;
488 sc = device_get_softc(dev);
489 rv = getset_state(sc, &state, GET_STATE);
493 /* If we haven't changed settings yet, estimate the current value. */
494 if (sc->sets[state].freq == CPUFREQ_VAL_UNKNOWN) {
495 cpu_est_clockrate(0, &rate);
496 sc->sets[state].freq = rate / 1000000;
497 DPRINT(dev, "get calibrated new rate of %d\n",
498 sc->sets[state].freq);
500 *set = sc->sets[state];
506 smist_type(device_t dev, int *type)
512 *type = CPUFREQ_TYPE_ABSOLUTE;