2 * Copyright (c) 1991 The Regents of the University of California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 4. Neither the name of the University nor the names of its contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91
33 #ifndef _MACHINE_SPECIALREG_H_
34 #define _MACHINE_SPECIALREG_H_
37 * Bits in 386 special registers:
39 #define CR0_PE 0x00000001 /* Protected mode Enable */
40 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */
41 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */
42 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
43 #define CR0_PG 0x80000000 /* PaGing enable */
46 * Bits in 486 special registers:
48 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
49 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in
51 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
52 #define CR0_NW 0x20000000 /* Not Write-through */
53 #define CR0_CD 0x40000000 /* Cache Disable */
55 #define CR3_PCID_SAVE 0x8000000000000000
58 * Bits in PPro special registers
60 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */
61 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */
62 #define CR4_TSD 0x00000004 /* Time stamp disable */
63 #define CR4_DE 0x00000008 /* Debugging extensions */
64 #define CR4_PSE 0x00000010 /* Page size extensions */
65 #define CR4_PAE 0x00000020 /* Physical address extension */
66 #define CR4_MCE 0x00000040 /* Machine check enable */
67 #define CR4_PGE 0x00000080 /* Page global enable */
68 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */
69 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */
70 #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */
71 #define CR4_VMXE 0x00002000 /* enable VMX operation (Intel-specific) */
72 #define CR4_FSGSBASE 0x00010000 /* Enable FS/GS BASE accessing instructions */
73 #define CR4_PCIDE 0x00020000 /* Enable Context ID */
74 #define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */
75 #define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution Prevention */
78 * Bits in AMD64 special registers. EFER is 64 bits wide.
80 #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */
81 #define EFER_LME 0x000000100 /* Long mode enable (R/W) */
82 #define EFER_LMA 0x000000400 /* Long mode active (R) */
83 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */
84 #define EFER_SVM 0x000001000 /* SVM enable bit for AMD, reserved for Intel */
85 #define EFER_LMSLE 0x000002000 /* Long Mode Segment Limit Enable */
86 #define EFER_FFXSR 0x000004000 /* Fast FXSAVE/FSRSTOR */
87 #define EFER_TCE 0x000008000 /* Translation Cache Extension */
90 * Intel Extended Features registers
92 #define XCR0 0 /* XFEATURE_ENABLED_MASK register */
94 #define XFEATURE_ENABLED_X87 0x00000001
95 #define XFEATURE_ENABLED_SSE 0x00000002
96 #define XFEATURE_ENABLED_YMM_HI128 0x00000004
97 #define XFEATURE_ENABLED_AVX XFEATURE_ENABLED_YMM_HI128
98 #define XFEATURE_ENABLED_BNDREGS 0x00000008
99 #define XFEATURE_ENABLED_BNDCSR 0x00000010
100 #define XFEATURE_ENABLED_OPMASK 0x00000020
101 #define XFEATURE_ENABLED_ZMM_HI256 0x00000040
102 #define XFEATURE_ENABLED_HI16_ZMM 0x00000080
104 #define XFEATURE_AVX \
105 (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX)
106 #define XFEATURE_AVX512 \
107 (XFEATURE_ENABLED_OPMASK | XFEATURE_ENABLED_ZMM_HI256 | \
108 XFEATURE_ENABLED_HI16_ZMM)
109 #define XFEATURE_MPX \
110 (XFEATURE_ENABLED_BNDREGS | XFEATURE_ENABLED_BNDCSR)
113 * CPUID instruction features register
115 #define CPUID_FPU 0x00000001
116 #define CPUID_VME 0x00000002
117 #define CPUID_DE 0x00000004
118 #define CPUID_PSE 0x00000008
119 #define CPUID_TSC 0x00000010
120 #define CPUID_MSR 0x00000020
121 #define CPUID_PAE 0x00000040
122 #define CPUID_MCE 0x00000080
123 #define CPUID_CX8 0x00000100
124 #define CPUID_APIC 0x00000200
125 #define CPUID_B10 0x00000400
126 #define CPUID_SEP 0x00000800
127 #define CPUID_MTRR 0x00001000
128 #define CPUID_PGE 0x00002000
129 #define CPUID_MCA 0x00004000
130 #define CPUID_CMOV 0x00008000
131 #define CPUID_PAT 0x00010000
132 #define CPUID_PSE36 0x00020000
133 #define CPUID_PSN 0x00040000
134 #define CPUID_CLFSH 0x00080000
135 #define CPUID_B20 0x00100000
136 #define CPUID_DS 0x00200000
137 #define CPUID_ACPI 0x00400000
138 #define CPUID_MMX 0x00800000
139 #define CPUID_FXSR 0x01000000
140 #define CPUID_SSE 0x02000000
141 #define CPUID_XMM 0x02000000
142 #define CPUID_SSE2 0x04000000
143 #define CPUID_SS 0x08000000
144 #define CPUID_HTT 0x10000000
145 #define CPUID_TM 0x20000000
146 #define CPUID_IA64 0x40000000
147 #define CPUID_PBE 0x80000000
149 #define CPUID2_SSE3 0x00000001
150 #define CPUID2_PCLMULQDQ 0x00000002
151 #define CPUID2_DTES64 0x00000004
152 #define CPUID2_MON 0x00000008
153 #define CPUID2_DS_CPL 0x00000010
154 #define CPUID2_VMX 0x00000020
155 #define CPUID2_SMX 0x00000040
156 #define CPUID2_EST 0x00000080
157 #define CPUID2_TM2 0x00000100
158 #define CPUID2_SSSE3 0x00000200
159 #define CPUID2_CNXTID 0x00000400
160 #define CPUID2_SDBG 0x00000800
161 #define CPUID2_FMA 0x00001000
162 #define CPUID2_CX16 0x00002000
163 #define CPUID2_XTPR 0x00004000
164 #define CPUID2_PDCM 0x00008000
165 #define CPUID2_PCID 0x00020000
166 #define CPUID2_DCA 0x00040000
167 #define CPUID2_SSE41 0x00080000
168 #define CPUID2_SSE42 0x00100000
169 #define CPUID2_X2APIC 0x00200000
170 #define CPUID2_MOVBE 0x00400000
171 #define CPUID2_POPCNT 0x00800000
172 #define CPUID2_TSCDLT 0x01000000
173 #define CPUID2_AESNI 0x02000000
174 #define CPUID2_XSAVE 0x04000000
175 #define CPUID2_OSXSAVE 0x08000000
176 #define CPUID2_AVX 0x10000000
177 #define CPUID2_F16C 0x20000000
178 #define CPUID2_RDRAND 0x40000000
179 #define CPUID2_HV 0x80000000
182 * Important bits in the Thermal and Power Management flags
183 * CPUID.6 EAX and ECX.
185 #define CPUTPM1_SENSOR 0x00000001
186 #define CPUTPM1_TURBO 0x00000002
187 #define CPUTPM1_ARAT 0x00000004
188 #define CPUTPM2_EFFREQ 0x00000001
191 * Important bits in the AMD extended cpuid flags
193 #define AMDID_SYSCALL 0x00000800
194 #define AMDID_MP 0x00080000
195 #define AMDID_NX 0x00100000
196 #define AMDID_EXT_MMX 0x00400000
197 #define AMDID_FFXSR 0x02000000
198 #define AMDID_PAGE1GB 0x04000000
199 #define AMDID_RDTSCP 0x08000000
200 #define AMDID_LM 0x20000000
201 #define AMDID_EXT_3DNOW 0x40000000
202 #define AMDID_3DNOW 0x80000000
204 #define AMDID2_LAHF 0x00000001
205 #define AMDID2_CMP 0x00000002
206 #define AMDID2_SVM 0x00000004
207 #define AMDID2_EXT_APIC 0x00000008
208 #define AMDID2_CR8 0x00000010
209 #define AMDID2_ABM 0x00000020
210 #define AMDID2_SSE4A 0x00000040
211 #define AMDID2_MAS 0x00000080
212 #define AMDID2_PREFETCH 0x00000100
213 #define AMDID2_OSVW 0x00000200
214 #define AMDID2_IBS 0x00000400
215 #define AMDID2_XOP 0x00000800
216 #define AMDID2_SKINIT 0x00001000
217 #define AMDID2_WDT 0x00002000
218 #define AMDID2_LWP 0x00008000
219 #define AMDID2_FMA4 0x00010000
220 #define AMDID2_TCE 0x00020000
221 #define AMDID2_NODE_ID 0x00080000
222 #define AMDID2_TBM 0x00200000
223 #define AMDID2_TOPOLOGY 0x00400000
224 #define AMDID2_PCXC 0x00800000
225 #define AMDID2_PNXC 0x01000000
226 #define AMDID2_DBE 0x04000000
227 #define AMDID2_PTSC 0x08000000
228 #define AMDID2_PTSCEL2I 0x10000000
231 * CPUID instruction 1 eax info
233 #define CPUID_STEPPING 0x0000000f
234 #define CPUID_MODEL 0x000000f0
235 #define CPUID_FAMILY 0x00000f00
236 #define CPUID_EXT_MODEL 0x000f0000
237 #define CPUID_EXT_FAMILY 0x0ff00000
239 #define CPUID_TO_MODEL(id) \
240 ((((id) & CPUID_MODEL) >> 4) | \
241 ((((id) & CPUID_FAMILY) >= 0x600) ? \
242 (((id) & CPUID_EXT_MODEL) >> 12) : 0))
243 #define CPUID_TO_FAMILY(id) \
244 ((((id) & CPUID_FAMILY) >> 8) + \
245 ((((id) & CPUID_FAMILY) == 0xf00) ? \
246 (((id) & CPUID_EXT_FAMILY) >> 20) : 0))
248 #define CPUID_TO_MODEL(id) \
249 ((((id) & CPUID_MODEL) >> 4) | \
250 (((id) & CPUID_EXT_MODEL) >> 12))
251 #define CPUID_TO_FAMILY(id) \
252 ((((id) & CPUID_FAMILY) >> 8) + \
253 (((id) & CPUID_EXT_FAMILY) >> 20))
257 * CPUID instruction 1 ebx info
259 #define CPUID_BRAND_INDEX 0x000000ff
260 #define CPUID_CLFUSH_SIZE 0x0000ff00
261 #define CPUID_HTT_CORES 0x00ff0000
262 #define CPUID_LOCAL_APIC_ID 0xff000000
265 * CPUID instruction 5 info
267 #define CPUID5_MON_MIN_SIZE 0x0000ffff /* eax */
268 #define CPUID5_MON_MAX_SIZE 0x0000ffff /* ebx */
269 #define CPUID5_MON_MWAIT_EXT 0x00000001 /* ecx */
270 #define CPUID5_MWAIT_INTRBREAK 0x00000002 /* ecx */
273 * MWAIT cpu power states. Lower 4 bits are sub-states.
275 #define MWAIT_C0 0xf0
276 #define MWAIT_C1 0x00
277 #define MWAIT_C2 0x10
278 #define MWAIT_C3 0x20
279 #define MWAIT_C4 0x30
284 /* Interrupt breaks MWAIT even when masked. */
285 #define MWAIT_INTRBREAK 0x00000001
288 * CPUID instruction 6 ecx info
290 #define CPUID_PERF_STAT 0x00000001
291 #define CPUID_PERF_BIAS 0x00000008
294 * CPUID instruction 0xb ebx info.
296 #define CPUID_TYPE_INVAL 0
297 #define CPUID_TYPE_SMT 1
298 #define CPUID_TYPE_CORE 2
301 * CPUID instruction 0xd Processor Extended State Enumeration Sub-leaf 1
303 #define CPUID_EXTSTATE_XSAVEOPT 0x00000001
304 #define CPUID_EXTSTATE_XSAVEC 0x00000002
305 #define CPUID_EXTSTATE_XINUSE 0x00000004
306 #define CPUID_EXTSTATE_XSAVES 0x00000008
309 * AMD extended function 8000_0007h edx info
311 #define AMDPM_TS 0x00000001
312 #define AMDPM_FID 0x00000002
313 #define AMDPM_VID 0x00000004
314 #define AMDPM_TTP 0x00000008
315 #define AMDPM_TM 0x00000010
316 #define AMDPM_STC 0x00000020
317 #define AMDPM_100MHZ_STEPS 0x00000040
318 #define AMDPM_HW_PSTATE 0x00000080
319 #define AMDPM_TSC_INVARIANT 0x00000100
320 #define AMDPM_CPB 0x00000200
323 * AMD extended function 8000_0008h ecx info
325 #define AMDID_CMP_CORES 0x000000ff
326 #define AMDID_COREID_SIZE 0x0000f000
327 #define AMDID_COREID_SIZE_SHIFT 12
330 * CPUID instruction 7 Structured Extended Features, leaf 0 ebx info
332 #define CPUID_STDEXT_FSGSBASE 0x00000001
333 #define CPUID_STDEXT_TSC_ADJUST 0x00000002
334 #define CPUID_STDEXT_SGX 0x00000004
335 #define CPUID_STDEXT_BMI1 0x00000008
336 #define CPUID_STDEXT_HLE 0x00000010
337 #define CPUID_STDEXT_AVX2 0x00000020
338 #define CPUID_STDEXT_FDP_EXC 0x00000040
339 #define CPUID_STDEXT_SMEP 0x00000080
340 #define CPUID_STDEXT_BMI2 0x00000100
341 #define CPUID_STDEXT_ERMS 0x00000200
342 #define CPUID_STDEXT_INVPCID 0x00000400
343 #define CPUID_STDEXT_RTM 0x00000800
344 #define CPUID_STDEXT_PQM 0x00001000
345 #define CPUID_STDEXT_NFPUSG 0x00002000
346 #define CPUID_STDEXT_MPX 0x00004000
347 #define CPUID_STDEXT_PQE 0x00008000
348 #define CPUID_STDEXT_AVX512F 0x00010000
349 #define CPUID_STDEXT_RDSEED 0x00040000
350 #define CPUID_STDEXT_ADX 0x00080000
351 #define CPUID_STDEXT_SMAP 0x00100000
352 #define CPUID_STDEXT_CLFLUSHOPT 0x00800000
353 #define CPUID_STDEXT_PROCTRACE 0x02000000
354 #define CPUID_STDEXT_AVX512PF 0x04000000
355 #define CPUID_STDEXT_AVX512ER 0x08000000
356 #define CPUID_STDEXT_AVX512CD 0x10000000
357 #define CPUID_STDEXT_SHA 0x20000000
360 * CPUID instruction 7 Structured Extended Features, leaf 0 ecx info
362 #define CPUID_STDEXT2_PREFETCHWT1 0x00000001
363 #define CPUID_STDEXT2_UMIP 0x00000004
364 #define CPUID_STDEXT2_PKU 0x00000008
365 #define CPUID_STDEXT2_OSPKE 0x00000010
366 #define CPUID_STDEXT2_RDPID 0x00400000
367 #define CPUID_STDEXT2_SGXLC 0x40000000
370 * CPUID manufacturers identifiers
372 #define AMD_VENDOR_ID "AuthenticAMD"
373 #define CENTAUR_VENDOR_ID "CentaurHauls"
374 #define CYRIX_VENDOR_ID "CyrixInstead"
375 #define INTEL_VENDOR_ID "GenuineIntel"
376 #define NEXGEN_VENDOR_ID "NexGenDriven"
377 #define NSC_VENDOR_ID "Geode by NSC"
378 #define RISE_VENDOR_ID "RiseRiseRise"
379 #define SIS_VENDOR_ID "SiS SiS SiS "
380 #define TRANSMETA_VENDOR_ID "GenuineTMx86"
381 #define UMC_VENDOR_ID "UMC UMC UMC "
384 * Model-specific registers for the i386 family
386 #define MSR_P5_MC_ADDR 0x000
387 #define MSR_P5_MC_TYPE 0x001
388 #define MSR_TSC 0x010
389 #define MSR_P5_CESR 0x011
390 #define MSR_P5_CTR0 0x012
391 #define MSR_P5_CTR1 0x013
392 #define MSR_IA32_PLATFORM_ID 0x017
393 #define MSR_APICBASE 0x01b
394 #define MSR_EBL_CR_POWERON 0x02a
395 #define MSR_TEST_CTL 0x033
396 #define MSR_IA32_FEATURE_CONTROL 0x03a
397 #define MSR_BIOS_UPDT_TRIG 0x079
398 #define MSR_BBL_CR_D0 0x088
399 #define MSR_BBL_CR_D1 0x089
400 #define MSR_BBL_CR_D2 0x08a
401 #define MSR_BIOS_SIGN 0x08b
402 #define MSR_PERFCTR0 0x0c1
403 #define MSR_PERFCTR1 0x0c2
404 #define MSR_PLATFORM_INFO 0x0ce
405 #define MSR_MPERF 0x0e7
406 #define MSR_APERF 0x0e8
407 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */
408 #define MSR_MTRRcap 0x0fe
409 #define MSR_BBL_CR_ADDR 0x116
410 #define MSR_BBL_CR_DECC 0x118
411 #define MSR_BBL_CR_CTL 0x119
412 #define MSR_BBL_CR_TRIG 0x11a
413 #define MSR_BBL_CR_BUSY 0x11b
414 #define MSR_BBL_CR_CTL3 0x11e
415 #define MSR_SYSENTER_CS_MSR 0x174
416 #define MSR_SYSENTER_ESP_MSR 0x175
417 #define MSR_SYSENTER_EIP_MSR 0x176
418 #define MSR_MCG_CAP 0x179
419 #define MSR_MCG_STATUS 0x17a
420 #define MSR_MCG_CTL 0x17b
421 #define MSR_EVNTSEL0 0x186
422 #define MSR_EVNTSEL1 0x187
423 #define MSR_THERM_CONTROL 0x19a
424 #define MSR_THERM_INTERRUPT 0x19b
425 #define MSR_THERM_STATUS 0x19c
426 #define MSR_IA32_MISC_ENABLE 0x1a0
427 #define MSR_IA32_TEMPERATURE_TARGET 0x1a2
428 #define MSR_TURBO_RATIO_LIMIT 0x1ad
429 #define MSR_TURBO_RATIO_LIMIT1 0x1ae
430 #define MSR_DEBUGCTLMSR 0x1d9
431 #define MSR_LASTBRANCHFROMIP 0x1db
432 #define MSR_LASTBRANCHTOIP 0x1dc
433 #define MSR_LASTINTFROMIP 0x1dd
434 #define MSR_LASTINTTOIP 0x1de
435 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0
436 #define MSR_MTRRVarBase 0x200
437 #define MSR_MTRR64kBase 0x250
438 #define MSR_MTRR16kBase 0x258
439 #define MSR_MTRR4kBase 0x268
440 #define MSR_PAT 0x277
441 #define MSR_MC0_CTL2 0x280
442 #define MSR_MTRRdefType 0x2ff
443 #define MSR_MC0_CTL 0x400
444 #define MSR_MC0_STATUS 0x401
445 #define MSR_MC0_ADDR 0x402
446 #define MSR_MC0_MISC 0x403
447 #define MSR_MC1_CTL 0x404
448 #define MSR_MC1_STATUS 0x405
449 #define MSR_MC1_ADDR 0x406
450 #define MSR_MC1_MISC 0x407
451 #define MSR_MC2_CTL 0x408
452 #define MSR_MC2_STATUS 0x409
453 #define MSR_MC2_ADDR 0x40a
454 #define MSR_MC2_MISC 0x40b
455 #define MSR_MC3_CTL 0x40c
456 #define MSR_MC3_STATUS 0x40d
457 #define MSR_MC3_ADDR 0x40e
458 #define MSR_MC3_MISC 0x40f
459 #define MSR_MC4_CTL 0x410
460 #define MSR_MC4_STATUS 0x411
461 #define MSR_MC4_ADDR 0x412
462 #define MSR_MC4_MISC 0x413
463 #define MSR_RAPL_POWER_UNIT 0x606
464 #define MSR_PKG_ENERGY_STATUS 0x611
465 #define MSR_DRAM_ENERGY_STATUS 0x619
466 #define MSR_PP0_ENERGY_STATUS 0x639
467 #define MSR_PP1_ENERGY_STATUS 0x641
472 #define MSR_VMX_BASIC 0x480
473 #define MSR_VMX_PINBASED_CTLS 0x481
474 #define MSR_VMX_PROCBASED_CTLS 0x482
475 #define MSR_VMX_EXIT_CTLS 0x483
476 #define MSR_VMX_ENTRY_CTLS 0x484
477 #define MSR_VMX_CR0_FIXED0 0x486
478 #define MSR_VMX_CR0_FIXED1 0x487
479 #define MSR_VMX_CR4_FIXED0 0x488
480 #define MSR_VMX_CR4_FIXED1 0x489
481 #define MSR_VMX_PROCBASED_CTLS2 0x48b
482 #define MSR_VMX_EPT_VPID_CAP 0x48c
483 #define MSR_VMX_TRUE_PINBASED_CTLS 0x48d
484 #define MSR_VMX_TRUE_PROCBASED_CTLS 0x48e
485 #define MSR_VMX_TRUE_EXIT_CTLS 0x48f
486 #define MSR_VMX_TRUE_ENTRY_CTLS 0x490
491 #define MSR_APIC_ID 0x802
492 #define MSR_APIC_VERSION 0x803
493 #define MSR_APIC_TPR 0x808
494 #define MSR_APIC_EOI 0x80b
495 #define MSR_APIC_LDR 0x80d
496 #define MSR_APIC_SVR 0x80f
497 #define MSR_APIC_ISR0 0x810
498 #define MSR_APIC_ISR1 0x811
499 #define MSR_APIC_ISR2 0x812
500 #define MSR_APIC_ISR3 0x813
501 #define MSR_APIC_ISR4 0x814
502 #define MSR_APIC_ISR5 0x815
503 #define MSR_APIC_ISR6 0x816
504 #define MSR_APIC_ISR7 0x817
505 #define MSR_APIC_TMR0 0x818
506 #define MSR_APIC_IRR0 0x820
507 #define MSR_APIC_ESR 0x828
508 #define MSR_APIC_LVT_CMCI 0x82F
509 #define MSR_APIC_ICR 0x830
510 #define MSR_APIC_LVT_TIMER 0x832
511 #define MSR_APIC_LVT_THERMAL 0x833
512 #define MSR_APIC_LVT_PCINT 0x834
513 #define MSR_APIC_LVT_LINT0 0x835
514 #define MSR_APIC_LVT_LINT1 0x836
515 #define MSR_APIC_LVT_ERROR 0x837
516 #define MSR_APIC_ICR_TIMER 0x838
517 #define MSR_APIC_CCR_TIMER 0x839
518 #define MSR_APIC_DCR_TIMER 0x83e
519 #define MSR_APIC_SELF_IPI 0x83f
521 #define MSR_IA32_XSS 0xda0
524 * Constants related to MSR's.
526 #define APICBASE_RESERVED 0x000002ff
527 #define APICBASE_BSP 0x00000100
528 #define APICBASE_X2APIC 0x00000400
529 #define APICBASE_ENABLED 0x00000800
530 #define APICBASE_ADDRESS 0xfffff000
532 /* MSR_IA32_FEATURE_CONTROL related */
533 #define IA32_FEATURE_CONTROL_LOCK 0x01 /* lock bit */
534 #define IA32_FEATURE_CONTROL_SMX_EN 0x02 /* enable VMX inside SMX */
535 #define IA32_FEATURE_CONTROL_VMX_EN 0x04 /* enable VMX outside SMX */
537 /* MSR IA32_MISC_ENABLE */
538 #define IA32_MISC_EN_FASTSTR 0x0000000000000001ULL
539 #define IA32_MISC_EN_ATCCE 0x0000000000000008ULL
540 #define IA32_MISC_EN_PERFMON 0x0000000000000080ULL
541 #define IA32_MISC_EN_PEBSU 0x0000000000001000ULL
542 #define IA32_MISC_EN_ESSTE 0x0000000000010000ULL
543 #define IA32_MISC_EN_MONE 0x0000000000040000ULL
544 #define IA32_MISC_EN_LIMCPUID 0x0000000000400000ULL
545 #define IA32_MISC_EN_xTPRD 0x0000000000800000ULL
546 #define IA32_MISC_EN_XDD 0x0000000400000000ULL
551 #define PAT_UNCACHEABLE 0x00
552 #define PAT_WRITE_COMBINING 0x01
553 #define PAT_WRITE_THROUGH 0x04
554 #define PAT_WRITE_PROTECTED 0x05
555 #define PAT_WRITE_BACK 0x06
556 #define PAT_UNCACHED 0x07
557 #define PAT_VALUE(i, m) ((long long)(m) << (8 * (i)))
558 #define PAT_MASK(i) PAT_VALUE(i, 0xff)
561 * Constants related to MTRRs
563 #define MTRR_UNCACHEABLE 0x00
564 #define MTRR_WRITE_COMBINING 0x01
565 #define MTRR_WRITE_THROUGH 0x04
566 #define MTRR_WRITE_PROTECTED 0x05
567 #define MTRR_WRITE_BACK 0x06
568 #define MTRR_N64K 8 /* numbers of fixed-size entries */
571 #define MTRR_CAP_WC 0x0000000000000400
572 #define MTRR_CAP_FIXED 0x0000000000000100
573 #define MTRR_CAP_VCNT 0x00000000000000ff
574 #define MTRR_DEF_ENABLE 0x0000000000000800
575 #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400
576 #define MTRR_DEF_TYPE 0x00000000000000ff
577 #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000
578 #define MTRR_PHYSBASE_TYPE 0x00000000000000ff
579 #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000
580 #define MTRR_PHYSMASK_VALID 0x0000000000000800
583 * Cyrix configuration registers, accessible as IO ports.
585 #define CCR0 0xc0 /* Configuration control register 0 */
586 #define CCR0_NC0 0x01 /* First 64K of each 1M memory region is
588 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
589 #define CCR0_A20M 0x04 /* Enables A20M# input pin */
590 #define CCR0_KEN 0x08 /* Enables KEN# input pin */
591 #define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */
592 #define CCR0_BARB 0x20 /* Flushes internal cache when entering hold
594 #define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set
596 #define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */
598 #define CCR1 0xc1 /* Configuration control register 1 */
599 #define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */
600 #define CCR1_SMI 0x02 /* Enables SMM pins */
601 #define CCR1_SMAC 0x04 /* System management memory access */
602 #define CCR1_MMAC 0x08 /* Main memory access */
603 #define CCR1_NO_LOCK 0x10 /* Negate LOCK# */
604 #define CCR1_SM3 0x80 /* SMM address space address region 3 */
607 #define CCR2_WB 0x02 /* Enables WB cache interface pins */
608 #define CCR2_SADS 0x02 /* Slow ADS */
609 #define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */
610 #define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */
611 #define CCR2_WT1 0x10 /* WT region 1 */
612 #define CCR2_WPR1 0x10 /* Write-protect region 1 */
613 #define CCR2_BARB 0x20 /* Flushes write-back cache when entering
615 #define CCR2_BWRT 0x40 /* Enables burst write cycles */
616 #define CCR2_USE_SUSP 0x80 /* Enables suspend pins */
619 #define CCR3_SMILOCK 0x01 /* SMM register lock */
620 #define CCR3_NMI 0x02 /* Enables NMI during SMM */
621 #define CCR3_LINBRST 0x04 /* Linear address burst cycles */
622 #define CCR3_SMMMODE 0x08 /* SMM Mode */
623 #define CCR3_MAPEN0 0x10 /* Enables Map0 */
624 #define CCR3_MAPEN1 0x20 /* Enables Map1 */
625 #define CCR3_MAPEN2 0x40 /* Enables Map2 */
626 #define CCR3_MAPEN3 0x80 /* Enables Map3 */
629 #define CCR4_IOMASK 0x07
630 #define CCR4_MEM 0x08 /* Enables momory bypassing */
631 #define CCR4_DTE 0x10 /* Enables directory table entry cache */
632 #define CCR4_FASTFPE 0x20 /* Fast FPU exception */
633 #define CCR4_CPUID 0x80 /* Enables CPUID instruction */
636 #define CCR5_WT_ALLOC 0x01 /* Write-through allocate */
637 #define CCR5_SLOP 0x02 /* LOOP instruction slowed down */
638 #define CCR5_LBR1 0x10 /* Local bus region 1 */
639 #define CCR5_ARREN 0x20 /* Enables ARR region */
645 /* Performance Control Register (5x86 only). */
647 #define PCR0_RSTK 0x01 /* Enables return stack */
648 #define PCR0_BTB 0x02 /* Enables branch target buffer */
649 #define PCR0_LOOP 0x04 /* Enables loop */
650 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to
652 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */
653 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */
654 #define PCR0_LSSER 0x80 /* Disable reorder */
656 /* Device Identification Registers */
661 * Machine Check register constants.
663 #define MCG_CAP_COUNT 0x000000ff
664 #define MCG_CAP_CTL_P 0x00000100
665 #define MCG_CAP_EXT_P 0x00000200
666 #define MCG_CAP_CMCI_P 0x00000400
667 #define MCG_CAP_TES_P 0x00000800
668 #define MCG_CAP_EXT_CNT 0x00ff0000
669 #define MCG_CAP_SER_P 0x01000000
670 #define MCG_STATUS_RIPV 0x00000001
671 #define MCG_STATUS_EIPV 0x00000002
672 #define MCG_STATUS_MCIP 0x00000004
673 #define MCG_CTL_ENABLE 0xffffffffffffffff
674 #define MCG_CTL_DISABLE 0x0000000000000000
675 #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4)
676 #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4)
677 #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4)
678 #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4)
679 #define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */
680 #define MC_STATUS_MCA_ERROR 0x000000000000ffff
681 #define MC_STATUS_MODEL_ERROR 0x00000000ffff0000
682 #define MC_STATUS_OTHER_INFO 0x01ffffff00000000
683 #define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */
684 #define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */
685 #define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */
686 #define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */
687 #define MC_STATUS_PCC 0x0200000000000000
688 #define MC_STATUS_ADDRV 0x0400000000000000
689 #define MC_STATUS_MISCV 0x0800000000000000
690 #define MC_STATUS_EN 0x1000000000000000
691 #define MC_STATUS_UC 0x2000000000000000
692 #define MC_STATUS_OVER 0x4000000000000000
693 #define MC_STATUS_VAL 0x8000000000000000
694 #define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */
695 #define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */
696 #define MC_CTL2_THRESHOLD 0x0000000000007fff
697 #define MC_CTL2_CMCI_EN 0x0000000040000000
700 * The following four 3-byte registers control the non-cacheable regions.
701 * These registers must be written as three separate bytes.
703 * NCRx+0: A31-A24 of starting address
704 * NCRx+1: A23-A16 of starting address
705 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
707 * The non-cacheable region's starting address must be aligned to the
708 * size indicated by the NCR_SIZE_xx field.
715 #define NCR_SIZE_0K 0
716 #define NCR_SIZE_4K 1
717 #define NCR_SIZE_8K 2
718 #define NCR_SIZE_16K 3
719 #define NCR_SIZE_32K 4
720 #define NCR_SIZE_64K 5
721 #define NCR_SIZE_128K 6
722 #define NCR_SIZE_256K 7
723 #define NCR_SIZE_512K 8
724 #define NCR_SIZE_1M 9
725 #define NCR_SIZE_2M 10
726 #define NCR_SIZE_4M 11
727 #define NCR_SIZE_8M 12
728 #define NCR_SIZE_16M 13
729 #define NCR_SIZE_32M 14
730 #define NCR_SIZE_4G 15
733 * The address region registers are used to specify the location and
734 * size for the eight address regions.
736 * ARRx + 0: A31-A24 of start address
737 * ARRx + 1: A23-A16 of start address
738 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
749 #define ARR_SIZE_0K 0
750 #define ARR_SIZE_4K 1
751 #define ARR_SIZE_8K 2
752 #define ARR_SIZE_16K 3
753 #define ARR_SIZE_32K 4
754 #define ARR_SIZE_64K 5
755 #define ARR_SIZE_128K 6
756 #define ARR_SIZE_256K 7
757 #define ARR_SIZE_512K 8
758 #define ARR_SIZE_1M 9
759 #define ARR_SIZE_2M 10
760 #define ARR_SIZE_4M 11
761 #define ARR_SIZE_8M 12
762 #define ARR_SIZE_16M 13
763 #define ARR_SIZE_32M 14
764 #define ARR_SIZE_4G 15
767 * The region control registers specify the attributes associated with
768 * the ARRx addres regions.
779 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
780 #define RCR_RCE 0x01 /* Enables caching for ARR7. */
781 #define RCR_WWO 0x02 /* Weak write ordering. */
782 #define RCR_WL 0x04 /* Weak locking. */
783 #define RCR_WG 0x08 /* Write gathering. */
784 #define RCR_WT 0x10 /* Write-through. */
785 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */
787 /* AMD Write Allocate Top-Of-Memory and Control Register */
788 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */
789 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */
790 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */
793 #define MSR_EFER 0xc0000080 /* extended features */
794 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */
795 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */
796 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */
797 #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */
798 #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */
799 #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */
800 #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */
801 #define MSR_PERFEVSEL0 0xc0010000
802 #define MSR_PERFEVSEL1 0xc0010001
803 #define MSR_PERFEVSEL2 0xc0010002
804 #define MSR_PERFEVSEL3 0xc0010003
805 #define MSR_K7_PERFCTR0 0xc0010004
806 #define MSR_K7_PERFCTR1 0xc0010005
807 #define MSR_K7_PERFCTR2 0xc0010006
808 #define MSR_K7_PERFCTR3 0xc0010007
809 #define MSR_SYSCFG 0xc0010010
810 #define MSR_HWCR 0xc0010015
811 #define MSR_IORRBASE0 0xc0010016
812 #define MSR_IORRMASK0 0xc0010017
813 #define MSR_IORRBASE1 0xc0010018
814 #define MSR_IORRMASK1 0xc0010019
815 #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */
816 #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */
817 #define MSR_NB_CFG1 0xc001001f /* NB configuration 1 */
818 #define MSR_P_STATE_LIMIT 0xc0010061 /* P-state Current Limit Register */
819 #define MSR_P_STATE_CONTROL 0xc0010062 /* P-state Control Register */
820 #define MSR_P_STATE_STATUS 0xc0010063 /* P-state Status Register */
821 #define MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */
822 #define MSR_SMM_ADDR 0xc0010112 /* SMM TSEG base address */
823 #define MSR_SMM_MASK 0xc0010113 /* SMM TSEG address mask */
824 #define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */
825 #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */
826 #define MSR_MC0_CTL_MASK 0xc0010044
827 #define MSR_VM_CR 0xc0010114 /* SVM: feature control */
828 #define MSR_VM_HSAVE_PA 0xc0010117 /* SVM: host save area address */
830 /* MSR_VM_CR related */
831 #define VM_CR_SVMDIS 0x10 /* SVM: disabled by BIOS */
833 /* VIA ACE crypto featureset: for via_feature_rng */
834 #define VIA_HAS_RNG 1 /* cpu has RNG */
836 /* VIA ACE crypto featureset: for via_feature_xcrypt */
837 #define VIA_HAS_AES 1 /* cpu has AES */
838 #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */
839 #define VIA_HAS_MM 4 /* cpu has RSA instructions */
840 #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */
842 /* Centaur Extended Feature flags */
843 #define VIA_CPUID_HAS_RNG 0x000004
844 #define VIA_CPUID_DO_RNG 0x000008
845 #define VIA_CPUID_HAS_ACE 0x000040
846 #define VIA_CPUID_DO_ACE 0x000080
847 #define VIA_CPUID_HAS_ACE2 0x000100
848 #define VIA_CPUID_DO_ACE2 0x000200
849 #define VIA_CPUID_HAS_PHE 0x000400
850 #define VIA_CPUID_DO_PHE 0x000800
851 #define VIA_CPUID_HAS_PMM 0x001000
852 #define VIA_CPUID_DO_PMM 0x002000
854 /* VIA ACE xcrypt-* instruction context control options */
855 #define VIA_CRYPT_CWLO_ROUND_M 0x0000000f
856 #define VIA_CRYPT_CWLO_ALG_M 0x00000070
857 #define VIA_CRYPT_CWLO_ALG_AES 0x00000000
858 #define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080
859 #define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000
860 #define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080
861 #define VIA_CRYPT_CWLO_NORMAL 0x00000000
862 #define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100
863 #define VIA_CRYPT_CWLO_ENCRYPT 0x00000000
864 #define VIA_CRYPT_CWLO_DECRYPT 0x00000200
865 #define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */
866 #define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */
867 #define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */
869 #endif /* !_MACHINE_SPECIALREG_H_ */
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