2 * Copyright (c) 1991 The Regents of the University of California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 4. Neither the name of the University nor the names of its contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91
33 #ifndef _MACHINE_SPECIALREG_H_
34 #define _MACHINE_SPECIALREG_H_
37 * Bits in 386 special registers:
39 #define CR0_PE 0x00000001 /* Protected mode Enable */
40 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */
41 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */
42 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
43 #define CR0_PG 0x80000000 /* PaGing enable */
46 * Bits in 486 special registers:
48 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
49 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in
51 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
52 #define CR0_NW 0x20000000 /* Not Write-through */
53 #define CR0_CD 0x40000000 /* Cache Disable */
55 #define CR3_PCID_SAVE 0x8000000000000000
58 * Bits in PPro special registers
60 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */
61 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */
62 #define CR4_TSD 0x00000004 /* Time stamp disable */
63 #define CR4_DE 0x00000008 /* Debugging extensions */
64 #define CR4_PSE 0x00000010 /* Page size extensions */
65 #define CR4_PAE 0x00000020 /* Physical address extension */
66 #define CR4_MCE 0x00000040 /* Machine check enable */
67 #define CR4_PGE 0x00000080 /* Page global enable */
68 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */
69 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */
70 #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */
71 #define CR4_VMXE 0x00002000 /* enable VMX operation (Intel-specific) */
72 #define CR4_FSGSBASE 0x00010000 /* Enable FS/GS BASE accessing instructions */
73 #define CR4_PCIDE 0x00020000 /* Enable Context ID */
74 #define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */
75 #define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution Prevention */
78 * Bits in AMD64 special registers. EFER is 64 bits wide.
80 #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */
81 #define EFER_LME 0x000000100 /* Long mode enable (R/W) */
82 #define EFER_LMA 0x000000400 /* Long mode active (R) */
83 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */
86 * Intel Extended Features registers
88 #define XCR0 0 /* XFEATURE_ENABLED_MASK register */
90 #define XFEATURE_ENABLED_X87 0x00000001
91 #define XFEATURE_ENABLED_SSE 0x00000002
92 #define XFEATURE_ENABLED_YMM_HI128 0x00000004
93 #define XFEATURE_ENABLED_AVX XFEATURE_ENABLED_YMM_HI128
94 #define XFEATURE_ENABLED_BNDREGS 0x00000008
95 #define XFEATURE_ENABLED_BNDCSR 0x00000010
96 #define XFEATURE_ENABLED_OPMASK 0x00000020
97 #define XFEATURE_ENABLED_ZMM_HI256 0x00000040
98 #define XFEATURE_ENABLED_HI16_ZMM 0x00000080
100 #define XFEATURE_AVX \
101 (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX)
102 #define XFEATURE_AVX512 \
103 (XFEATURE_ENABLED_OPMASK | XFEATURE_ENABLED_ZMM_HI256 | \
104 XFEATURE_ENABLED_HI16_ZMM)
105 #define XFEATURE_MPX \
106 (XFEATURE_ENABLED_BNDREGS | XFEATURE_ENABLED_BNDCSR)
109 * CPUID instruction features register
111 #define CPUID_FPU 0x00000001
112 #define CPUID_VME 0x00000002
113 #define CPUID_DE 0x00000004
114 #define CPUID_PSE 0x00000008
115 #define CPUID_TSC 0x00000010
116 #define CPUID_MSR 0x00000020
117 #define CPUID_PAE 0x00000040
118 #define CPUID_MCE 0x00000080
119 #define CPUID_CX8 0x00000100
120 #define CPUID_APIC 0x00000200
121 #define CPUID_B10 0x00000400
122 #define CPUID_SEP 0x00000800
123 #define CPUID_MTRR 0x00001000
124 #define CPUID_PGE 0x00002000
125 #define CPUID_MCA 0x00004000
126 #define CPUID_CMOV 0x00008000
127 #define CPUID_PAT 0x00010000
128 #define CPUID_PSE36 0x00020000
129 #define CPUID_PSN 0x00040000
130 #define CPUID_CLFSH 0x00080000
131 #define CPUID_B20 0x00100000
132 #define CPUID_DS 0x00200000
133 #define CPUID_ACPI 0x00400000
134 #define CPUID_MMX 0x00800000
135 #define CPUID_FXSR 0x01000000
136 #define CPUID_SSE 0x02000000
137 #define CPUID_XMM 0x02000000
138 #define CPUID_SSE2 0x04000000
139 #define CPUID_SS 0x08000000
140 #define CPUID_HTT 0x10000000
141 #define CPUID_TM 0x20000000
142 #define CPUID_IA64 0x40000000
143 #define CPUID_PBE 0x80000000
145 #define CPUID2_SSE3 0x00000001
146 #define CPUID2_PCLMULQDQ 0x00000002
147 #define CPUID2_DTES64 0x00000004
148 #define CPUID2_MON 0x00000008
149 #define CPUID2_DS_CPL 0x00000010
150 #define CPUID2_VMX 0x00000020
151 #define CPUID2_SMX 0x00000040
152 #define CPUID2_EST 0x00000080
153 #define CPUID2_TM2 0x00000100
154 #define CPUID2_SSSE3 0x00000200
155 #define CPUID2_CNXTID 0x00000400
156 #define CPUID2_FMA 0x00001000
157 #define CPUID2_CX16 0x00002000
158 #define CPUID2_XTPR 0x00004000
159 #define CPUID2_PDCM 0x00008000
160 #define CPUID2_PCID 0x00020000
161 #define CPUID2_DCA 0x00040000
162 #define CPUID2_SSE41 0x00080000
163 #define CPUID2_SSE42 0x00100000
164 #define CPUID2_X2APIC 0x00200000
165 #define CPUID2_MOVBE 0x00400000
166 #define CPUID2_POPCNT 0x00800000
167 #define CPUID2_TSCDLT 0x01000000
168 #define CPUID2_AESNI 0x02000000
169 #define CPUID2_XSAVE 0x04000000
170 #define CPUID2_OSXSAVE 0x08000000
171 #define CPUID2_AVX 0x10000000
172 #define CPUID2_F16C 0x20000000
173 #define CPUID2_RDRAND 0x40000000
174 #define CPUID2_HV 0x80000000
177 * Important bits in the Thermal and Power Management flags
178 * CPUID.6 EAX and ECX.
180 #define CPUTPM1_SENSOR 0x00000001
181 #define CPUTPM1_TURBO 0x00000002
182 #define CPUTPM1_ARAT 0x00000004
183 #define CPUTPM2_EFFREQ 0x00000001
186 * Important bits in the AMD extended cpuid flags
188 #define AMDID_SYSCALL 0x00000800
189 #define AMDID_MP 0x00080000
190 #define AMDID_NX 0x00100000
191 #define AMDID_EXT_MMX 0x00400000
192 #define AMDID_FFXSR 0x01000000
193 #define AMDID_PAGE1GB 0x04000000
194 #define AMDID_RDTSCP 0x08000000
195 #define AMDID_LM 0x20000000
196 #define AMDID_EXT_3DNOW 0x40000000
197 #define AMDID_3DNOW 0x80000000
199 #define AMDID2_LAHF 0x00000001
200 #define AMDID2_CMP 0x00000002
201 #define AMDID2_SVM 0x00000004
202 #define AMDID2_EXT_APIC 0x00000008
203 #define AMDID2_CR8 0x00000010
204 #define AMDID2_ABM 0x00000020
205 #define AMDID2_SSE4A 0x00000040
206 #define AMDID2_MAS 0x00000080
207 #define AMDID2_PREFETCH 0x00000100
208 #define AMDID2_OSVW 0x00000200
209 #define AMDID2_IBS 0x00000400
210 #define AMDID2_XOP 0x00000800
211 #define AMDID2_SKINIT 0x00001000
212 #define AMDID2_WDT 0x00002000
213 #define AMDID2_LWP 0x00008000
214 #define AMDID2_FMA4 0x00010000
215 #define AMDID2_TCE 0x00020000
216 #define AMDID2_NODE_ID 0x00080000
217 #define AMDID2_TBM 0x00200000
218 #define AMDID2_TOPOLOGY 0x00400000
219 #define AMDID2_PCXC 0x00800000
220 #define AMDID2_PNXC 0x01000000
221 #define AMDID2_DBE 0x04000000
222 #define AMDID2_PTSC 0x08000000
223 #define AMDID2_PTSCEL2I 0x10000000
226 * CPUID instruction 1 eax info
228 #define CPUID_STEPPING 0x0000000f
229 #define CPUID_MODEL 0x000000f0
230 #define CPUID_FAMILY 0x00000f00
231 #define CPUID_EXT_MODEL 0x000f0000
232 #define CPUID_EXT_FAMILY 0x0ff00000
234 #define CPUID_TO_MODEL(id) \
235 ((((id) & CPUID_MODEL) >> 4) | \
236 ((((id) & CPUID_FAMILY) >= 0x600) ? \
237 (((id) & CPUID_EXT_MODEL) >> 12) : 0))
238 #define CPUID_TO_FAMILY(id) \
239 ((((id) & CPUID_FAMILY) >> 8) + \
240 ((((id) & CPUID_FAMILY) == 0xf00) ? \
241 (((id) & CPUID_EXT_FAMILY) >> 20) : 0))
243 #define CPUID_TO_MODEL(id) \
244 ((((id) & CPUID_MODEL) >> 4) | \
245 (((id) & CPUID_EXT_MODEL) >> 12))
246 #define CPUID_TO_FAMILY(id) \
247 ((((id) & CPUID_FAMILY) >> 8) + \
248 (((id) & CPUID_EXT_FAMILY) >> 20))
252 * CPUID instruction 1 ebx info
254 #define CPUID_BRAND_INDEX 0x000000ff
255 #define CPUID_CLFUSH_SIZE 0x0000ff00
256 #define CPUID_HTT_CORES 0x00ff0000
257 #define CPUID_LOCAL_APIC_ID 0xff000000
260 * CPUID instruction 5 info
262 #define CPUID5_MON_MIN_SIZE 0x0000ffff /* eax */
263 #define CPUID5_MON_MAX_SIZE 0x0000ffff /* ebx */
264 #define CPUID5_MON_MWAIT_EXT 0x00000001 /* ecx */
265 #define CPUID5_MWAIT_INTRBREAK 0x00000002 /* ecx */
268 * MWAIT cpu power states. Lower 4 bits are sub-states.
270 #define MWAIT_C0 0xf0
271 #define MWAIT_C1 0x00
272 #define MWAIT_C2 0x10
273 #define MWAIT_C3 0x20
274 #define MWAIT_C4 0x30
279 /* Interrupt breaks MWAIT even when masked. */
280 #define MWAIT_INTRBREAK 0x00000001
283 * CPUID instruction 6 ecx info
285 #define CPUID_PERF_STAT 0x00000001
286 #define CPUID_PERF_BIAS 0x00000008
289 * CPUID instruction 0xb ebx info.
291 #define CPUID_TYPE_INVAL 0
292 #define CPUID_TYPE_SMT 1
293 #define CPUID_TYPE_CORE 2
296 * CPUID instruction 0xd Processor Extended State Enumeration Sub-leaf 1
298 #define CPUID_EXTSTATE_XSAVEOPT 0x00000001
299 #define CPUID_EXTSTATE_XSAVEC 0x00000002
300 #define CPUID_EXTSTATE_XINUSE 0x00000004
301 #define CPUID_EXTSTATE_XSAVES 0x00000008
304 * AMD extended function 8000_0007h edx info
306 #define AMDPM_TS 0x00000001
307 #define AMDPM_FID 0x00000002
308 #define AMDPM_VID 0x00000004
309 #define AMDPM_TTP 0x00000008
310 #define AMDPM_TM 0x00000010
311 #define AMDPM_STC 0x00000020
312 #define AMDPM_100MHZ_STEPS 0x00000040
313 #define AMDPM_HW_PSTATE 0x00000080
314 #define AMDPM_TSC_INVARIANT 0x00000100
315 #define AMDPM_CPB 0x00000200
318 * AMD extended function 8000_0008h ecx info
320 #define AMDID_CMP_CORES 0x000000ff
321 #define AMDID_COREID_SIZE 0x0000f000
322 #define AMDID_COREID_SIZE_SHIFT 12
325 * CPUID instruction 7 Structured Extended Features, leaf 0 ebx info
327 #define CPUID_STDEXT_FSGSBASE 0x00000001
328 #define CPUID_STDEXT_TSC_ADJUST 0x00000002
329 #define CPUID_STDEXT_BMI1 0x00000008
330 #define CPUID_STDEXT_HLE 0x00000010
331 #define CPUID_STDEXT_AVX2 0x00000020
332 #define CPUID_STDEXT_SMEP 0x00000080
333 #define CPUID_STDEXT_BMI2 0x00000100
334 #define CPUID_STDEXT_ERMS 0x00000200
335 #define CPUID_STDEXT_INVPCID 0x00000400
336 #define CPUID_STDEXT_RTM 0x00000800
337 #define CPUID_STDEXT_MPX 0x00004000
338 #define CPUID_STDEXT_AVX512F 0x00010000
339 #define CPUID_STDEXT_RDSEED 0x00040000
340 #define CPUID_STDEXT_ADX 0x00080000
341 #define CPUID_STDEXT_SMAP 0x00100000
342 #define CPUID_STDEXT_CLFLUSHOPT 0x00800000
343 #define CPUID_STDEXT_PROCTRACE 0x02000000
344 #define CPUID_STDEXT_AVX512PF 0x04000000
345 #define CPUID_STDEXT_AVX512ER 0x08000000
346 #define CPUID_STDEXT_AVX512CD 0x10000000
347 #define CPUID_STDEXT_SHA 0x20000000
350 * CPUID manufacturers identifiers
352 #define AMD_VENDOR_ID "AuthenticAMD"
353 #define CENTAUR_VENDOR_ID "CentaurHauls"
354 #define CYRIX_VENDOR_ID "CyrixInstead"
355 #define INTEL_VENDOR_ID "GenuineIntel"
356 #define NEXGEN_VENDOR_ID "NexGenDriven"
357 #define NSC_VENDOR_ID "Geode by NSC"
358 #define RISE_VENDOR_ID "RiseRiseRise"
359 #define SIS_VENDOR_ID "SiS SiS SiS "
360 #define TRANSMETA_VENDOR_ID "GenuineTMx86"
361 #define UMC_VENDOR_ID "UMC UMC UMC "
364 * Model-specific registers for the i386 family
366 #define MSR_P5_MC_ADDR 0x000
367 #define MSR_P5_MC_TYPE 0x001
368 #define MSR_TSC 0x010
369 #define MSR_P5_CESR 0x011
370 #define MSR_P5_CTR0 0x012
371 #define MSR_P5_CTR1 0x013
372 #define MSR_IA32_PLATFORM_ID 0x017
373 #define MSR_APICBASE 0x01b
374 #define MSR_EBL_CR_POWERON 0x02a
375 #define MSR_TEST_CTL 0x033
376 #define MSR_IA32_FEATURE_CONTROL 0x03a
377 #define MSR_BIOS_UPDT_TRIG 0x079
378 #define MSR_BBL_CR_D0 0x088
379 #define MSR_BBL_CR_D1 0x089
380 #define MSR_BBL_CR_D2 0x08a
381 #define MSR_BIOS_SIGN 0x08b
382 #define MSR_PERFCTR0 0x0c1
383 #define MSR_PERFCTR1 0x0c2
384 #define MSR_MPERF 0x0e7
385 #define MSR_APERF 0x0e8
386 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */
387 #define MSR_MTRRcap 0x0fe
388 #define MSR_BBL_CR_ADDR 0x116
389 #define MSR_BBL_CR_DECC 0x118
390 #define MSR_BBL_CR_CTL 0x119
391 #define MSR_BBL_CR_TRIG 0x11a
392 #define MSR_BBL_CR_BUSY 0x11b
393 #define MSR_BBL_CR_CTL3 0x11e
394 #define MSR_SYSENTER_CS_MSR 0x174
395 #define MSR_SYSENTER_ESP_MSR 0x175
396 #define MSR_SYSENTER_EIP_MSR 0x176
397 #define MSR_MCG_CAP 0x179
398 #define MSR_MCG_STATUS 0x17a
399 #define MSR_MCG_CTL 0x17b
400 #define MSR_EVNTSEL0 0x186
401 #define MSR_EVNTSEL1 0x187
402 #define MSR_THERM_CONTROL 0x19a
403 #define MSR_THERM_INTERRUPT 0x19b
404 #define MSR_THERM_STATUS 0x19c
405 #define MSR_IA32_MISC_ENABLE 0x1a0
406 #define MSR_IA32_TEMPERATURE_TARGET 0x1a2
407 #define MSR_DEBUGCTLMSR 0x1d9
408 #define MSR_LASTBRANCHFROMIP 0x1db
409 #define MSR_LASTBRANCHTOIP 0x1dc
410 #define MSR_LASTINTFROMIP 0x1dd
411 #define MSR_LASTINTTOIP 0x1de
412 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0
413 #define MSR_MTRRVarBase 0x200
414 #define MSR_MTRR64kBase 0x250
415 #define MSR_MTRR16kBase 0x258
416 #define MSR_MTRR4kBase 0x268
417 #define MSR_PAT 0x277
418 #define MSR_MC0_CTL2 0x280
419 #define MSR_MTRRdefType 0x2ff
420 #define MSR_MC0_CTL 0x400
421 #define MSR_MC0_STATUS 0x401
422 #define MSR_MC0_ADDR 0x402
423 #define MSR_MC0_MISC 0x403
424 #define MSR_MC1_CTL 0x404
425 #define MSR_MC1_STATUS 0x405
426 #define MSR_MC1_ADDR 0x406
427 #define MSR_MC1_MISC 0x407
428 #define MSR_MC2_CTL 0x408
429 #define MSR_MC2_STATUS 0x409
430 #define MSR_MC2_ADDR 0x40a
431 #define MSR_MC2_MISC 0x40b
432 #define MSR_MC3_CTL 0x40c
433 #define MSR_MC3_STATUS 0x40d
434 #define MSR_MC3_ADDR 0x40e
435 #define MSR_MC3_MISC 0x40f
436 #define MSR_MC4_CTL 0x410
437 #define MSR_MC4_STATUS 0x411
438 #define MSR_MC4_ADDR 0x412
439 #define MSR_MC4_MISC 0x413
444 #define MSR_VMX_BASIC 0x480
445 #define MSR_VMX_PINBASED_CTLS 0x481
446 #define MSR_VMX_PROCBASED_CTLS 0x482
447 #define MSR_VMX_EXIT_CTLS 0x483
448 #define MSR_VMX_ENTRY_CTLS 0x484
449 #define MSR_VMX_CR0_FIXED0 0x486
450 #define MSR_VMX_CR0_FIXED1 0x487
451 #define MSR_VMX_CR4_FIXED0 0x488
452 #define MSR_VMX_CR4_FIXED1 0x489
453 #define MSR_VMX_PROCBASED_CTLS2 0x48b
454 #define MSR_VMX_EPT_VPID_CAP 0x48c
455 #define MSR_VMX_TRUE_PINBASED_CTLS 0x48d
456 #define MSR_VMX_TRUE_PROCBASED_CTLS 0x48e
457 #define MSR_VMX_TRUE_EXIT_CTLS 0x48f
458 #define MSR_VMX_TRUE_ENTRY_CTLS 0x490
463 #define MSR_APIC_ID 0x802
464 #define MSR_APIC_VERSION 0x803
465 #define MSR_APIC_TPR 0x808
466 #define MSR_APIC_EOI 0x80b
467 #define MSR_APIC_LDR 0x80d
468 #define MSR_APIC_SVR 0x80f
469 #define MSR_APIC_ISR0 0x810
470 #define MSR_APIC_ISR1 0x811
471 #define MSR_APIC_ISR2 0x812
472 #define MSR_APIC_ISR3 0x813
473 #define MSR_APIC_ISR4 0x814
474 #define MSR_APIC_ISR5 0x815
475 #define MSR_APIC_ISR6 0x816
476 #define MSR_APIC_ISR7 0x817
477 #define MSR_APIC_TMR0 0x818
478 #define MSR_APIC_IRR0 0x820
479 #define MSR_APIC_ESR 0x828
480 #define MSR_APIC_LVT_CMCI 0x82F
481 #define MSR_APIC_ICR 0x830
482 #define MSR_APIC_LVT_TIMER 0x832
483 #define MSR_APIC_LVT_THERMAL 0x833
484 #define MSR_APIC_LVT_PCINT 0x834
485 #define MSR_APIC_LVT_LINT0 0x835
486 #define MSR_APIC_LVT_LINT1 0x836
487 #define MSR_APIC_LVT_ERROR 0x837
488 #define MSR_APIC_ICR_TIMER 0x838
489 #define MSR_APIC_CCR_TIMER 0x839
490 #define MSR_APIC_DCR_TIMER 0x83e
491 #define MSR_APIC_SELF_IPI 0x83f
493 #define MSR_IA32_XSS 0xda0
496 * Constants related to MSR's.
498 #define APICBASE_RESERVED 0x000002ff
499 #define APICBASE_BSP 0x00000100
500 #define APICBASE_X2APIC 0x00000400
501 #define APICBASE_ENABLED 0x00000800
502 #define APICBASE_ADDRESS 0xfffff000
504 /* MSR_IA32_FEATURE_CONTROL related */
505 #define IA32_FEATURE_CONTROL_LOCK 0x01 /* lock bit */
506 #define IA32_FEATURE_CONTROL_SMX_EN 0x02 /* enable VMX inside SMX */
507 #define IA32_FEATURE_CONTROL_VMX_EN 0x04 /* enable VMX outside SMX */
512 #define PAT_UNCACHEABLE 0x00
513 #define PAT_WRITE_COMBINING 0x01
514 #define PAT_WRITE_THROUGH 0x04
515 #define PAT_WRITE_PROTECTED 0x05
516 #define PAT_WRITE_BACK 0x06
517 #define PAT_UNCACHED 0x07
518 #define PAT_VALUE(i, m) ((long long)(m) << (8 * (i)))
519 #define PAT_MASK(i) PAT_VALUE(i, 0xff)
522 * Constants related to MTRRs
524 #define MTRR_UNCACHEABLE 0x00
525 #define MTRR_WRITE_COMBINING 0x01
526 #define MTRR_WRITE_THROUGH 0x04
527 #define MTRR_WRITE_PROTECTED 0x05
528 #define MTRR_WRITE_BACK 0x06
529 #define MTRR_N64K 8 /* numbers of fixed-size entries */
532 #define MTRR_CAP_WC 0x0000000000000400
533 #define MTRR_CAP_FIXED 0x0000000000000100
534 #define MTRR_CAP_VCNT 0x00000000000000ff
535 #define MTRR_DEF_ENABLE 0x0000000000000800
536 #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400
537 #define MTRR_DEF_TYPE 0x00000000000000ff
538 #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000
539 #define MTRR_PHYSBASE_TYPE 0x00000000000000ff
540 #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000
541 #define MTRR_PHYSMASK_VALID 0x0000000000000800
544 * Cyrix configuration registers, accessible as IO ports.
546 #define CCR0 0xc0 /* Configuration control register 0 */
547 #define CCR0_NC0 0x01 /* First 64K of each 1M memory region is
549 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
550 #define CCR0_A20M 0x04 /* Enables A20M# input pin */
551 #define CCR0_KEN 0x08 /* Enables KEN# input pin */
552 #define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */
553 #define CCR0_BARB 0x20 /* Flushes internal cache when entering hold
555 #define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set
557 #define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */
559 #define CCR1 0xc1 /* Configuration control register 1 */
560 #define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */
561 #define CCR1_SMI 0x02 /* Enables SMM pins */
562 #define CCR1_SMAC 0x04 /* System management memory access */
563 #define CCR1_MMAC 0x08 /* Main memory access */
564 #define CCR1_NO_LOCK 0x10 /* Negate LOCK# */
565 #define CCR1_SM3 0x80 /* SMM address space address region 3 */
568 #define CCR2_WB 0x02 /* Enables WB cache interface pins */
569 #define CCR2_SADS 0x02 /* Slow ADS */
570 #define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */
571 #define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */
572 #define CCR2_WT1 0x10 /* WT region 1 */
573 #define CCR2_WPR1 0x10 /* Write-protect region 1 */
574 #define CCR2_BARB 0x20 /* Flushes write-back cache when entering
576 #define CCR2_BWRT 0x40 /* Enables burst write cycles */
577 #define CCR2_USE_SUSP 0x80 /* Enables suspend pins */
580 #define CCR3_SMILOCK 0x01 /* SMM register lock */
581 #define CCR3_NMI 0x02 /* Enables NMI during SMM */
582 #define CCR3_LINBRST 0x04 /* Linear address burst cycles */
583 #define CCR3_SMMMODE 0x08 /* SMM Mode */
584 #define CCR3_MAPEN0 0x10 /* Enables Map0 */
585 #define CCR3_MAPEN1 0x20 /* Enables Map1 */
586 #define CCR3_MAPEN2 0x40 /* Enables Map2 */
587 #define CCR3_MAPEN3 0x80 /* Enables Map3 */
590 #define CCR4_IOMASK 0x07
591 #define CCR4_MEM 0x08 /* Enables momory bypassing */
592 #define CCR4_DTE 0x10 /* Enables directory table entry cache */
593 #define CCR4_FASTFPE 0x20 /* Fast FPU exception */
594 #define CCR4_CPUID 0x80 /* Enables CPUID instruction */
597 #define CCR5_WT_ALLOC 0x01 /* Write-through allocate */
598 #define CCR5_SLOP 0x02 /* LOOP instruction slowed down */
599 #define CCR5_LBR1 0x10 /* Local bus region 1 */
600 #define CCR5_ARREN 0x20 /* Enables ARR region */
606 /* Performance Control Register (5x86 only). */
608 #define PCR0_RSTK 0x01 /* Enables return stack */
609 #define PCR0_BTB 0x02 /* Enables branch target buffer */
610 #define PCR0_LOOP 0x04 /* Enables loop */
611 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to
613 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */
614 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */
615 #define PCR0_LSSER 0x80 /* Disable reorder */
617 /* Device Identification Registers */
622 * Machine Check register constants.
624 #define MCG_CAP_COUNT 0x000000ff
625 #define MCG_CAP_CTL_P 0x00000100
626 #define MCG_CAP_EXT_P 0x00000200
627 #define MCG_CAP_CMCI_P 0x00000400
628 #define MCG_CAP_TES_P 0x00000800
629 #define MCG_CAP_EXT_CNT 0x00ff0000
630 #define MCG_CAP_SER_P 0x01000000
631 #define MCG_STATUS_RIPV 0x00000001
632 #define MCG_STATUS_EIPV 0x00000002
633 #define MCG_STATUS_MCIP 0x00000004
634 #define MCG_CTL_ENABLE 0xffffffffffffffff
635 #define MCG_CTL_DISABLE 0x0000000000000000
636 #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4)
637 #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4)
638 #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4)
639 #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4)
640 #define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */
641 #define MC_STATUS_MCA_ERROR 0x000000000000ffff
642 #define MC_STATUS_MODEL_ERROR 0x00000000ffff0000
643 #define MC_STATUS_OTHER_INFO 0x01ffffff00000000
644 #define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */
645 #define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */
646 #define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */
647 #define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */
648 #define MC_STATUS_PCC 0x0200000000000000
649 #define MC_STATUS_ADDRV 0x0400000000000000
650 #define MC_STATUS_MISCV 0x0800000000000000
651 #define MC_STATUS_EN 0x1000000000000000
652 #define MC_STATUS_UC 0x2000000000000000
653 #define MC_STATUS_OVER 0x4000000000000000
654 #define MC_STATUS_VAL 0x8000000000000000
655 #define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */
656 #define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */
657 #define MC_CTL2_THRESHOLD 0x0000000000007fff
658 #define MC_CTL2_CMCI_EN 0x0000000040000000
661 * The following four 3-byte registers control the non-cacheable regions.
662 * These registers must be written as three separate bytes.
664 * NCRx+0: A31-A24 of starting address
665 * NCRx+1: A23-A16 of starting address
666 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
668 * The non-cacheable region's starting address must be aligned to the
669 * size indicated by the NCR_SIZE_xx field.
676 #define NCR_SIZE_0K 0
677 #define NCR_SIZE_4K 1
678 #define NCR_SIZE_8K 2
679 #define NCR_SIZE_16K 3
680 #define NCR_SIZE_32K 4
681 #define NCR_SIZE_64K 5
682 #define NCR_SIZE_128K 6
683 #define NCR_SIZE_256K 7
684 #define NCR_SIZE_512K 8
685 #define NCR_SIZE_1M 9
686 #define NCR_SIZE_2M 10
687 #define NCR_SIZE_4M 11
688 #define NCR_SIZE_8M 12
689 #define NCR_SIZE_16M 13
690 #define NCR_SIZE_32M 14
691 #define NCR_SIZE_4G 15
694 * The address region registers are used to specify the location and
695 * size for the eight address regions.
697 * ARRx + 0: A31-A24 of start address
698 * ARRx + 1: A23-A16 of start address
699 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
710 #define ARR_SIZE_0K 0
711 #define ARR_SIZE_4K 1
712 #define ARR_SIZE_8K 2
713 #define ARR_SIZE_16K 3
714 #define ARR_SIZE_32K 4
715 #define ARR_SIZE_64K 5
716 #define ARR_SIZE_128K 6
717 #define ARR_SIZE_256K 7
718 #define ARR_SIZE_512K 8
719 #define ARR_SIZE_1M 9
720 #define ARR_SIZE_2M 10
721 #define ARR_SIZE_4M 11
722 #define ARR_SIZE_8M 12
723 #define ARR_SIZE_16M 13
724 #define ARR_SIZE_32M 14
725 #define ARR_SIZE_4G 15
728 * The region control registers specify the attributes associated with
729 * the ARRx addres regions.
740 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
741 #define RCR_RCE 0x01 /* Enables caching for ARR7. */
742 #define RCR_WWO 0x02 /* Weak write ordering. */
743 #define RCR_WL 0x04 /* Weak locking. */
744 #define RCR_WG 0x08 /* Write gathering. */
745 #define RCR_WT 0x10 /* Write-through. */
746 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */
748 /* AMD Write Allocate Top-Of-Memory and Control Register */
749 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */
750 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */
751 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */
754 #define MSR_EFER 0xc0000080 /* extended features */
755 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */
756 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */
757 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */
758 #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */
759 #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */
760 #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */
761 #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */
762 #define MSR_PERFEVSEL0 0xc0010000
763 #define MSR_PERFEVSEL1 0xc0010001
764 #define MSR_PERFEVSEL2 0xc0010002
765 #define MSR_PERFEVSEL3 0xc0010003
768 #define MSR_PERFCTR0 0xc0010004
769 #define MSR_PERFCTR1 0xc0010005
770 #define MSR_PERFCTR2 0xc0010006
771 #define MSR_PERFCTR3 0xc0010007
772 #define MSR_SYSCFG 0xc0010010
773 #define MSR_HWCR 0xc0010015
774 #define MSR_IORRBASE0 0xc0010016
775 #define MSR_IORRMASK0 0xc0010017
776 #define MSR_IORRBASE1 0xc0010018
777 #define MSR_IORRMASK1 0xc0010019
778 #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */
779 #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */
780 #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */
781 #define MSR_MC0_CTL_MASK 0xc0010044
783 /* VIA ACE crypto featureset: for via_feature_rng */
784 #define VIA_HAS_RNG 1 /* cpu has RNG */
786 /* VIA ACE crypto featureset: for via_feature_xcrypt */
787 #define VIA_HAS_AES 1 /* cpu has AES */
788 #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */
789 #define VIA_HAS_MM 4 /* cpu has RSA instructions */
790 #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */
792 /* Centaur Extended Feature flags */
793 #define VIA_CPUID_HAS_RNG 0x000004
794 #define VIA_CPUID_DO_RNG 0x000008
795 #define VIA_CPUID_HAS_ACE 0x000040
796 #define VIA_CPUID_DO_ACE 0x000080
797 #define VIA_CPUID_HAS_ACE2 0x000100
798 #define VIA_CPUID_DO_ACE2 0x000200
799 #define VIA_CPUID_HAS_PHE 0x000400
800 #define VIA_CPUID_DO_PHE 0x000800
801 #define VIA_CPUID_HAS_PMM 0x001000
802 #define VIA_CPUID_DO_PMM 0x002000
804 /* VIA ACE xcrypt-* instruction context control options */
805 #define VIA_CRYPT_CWLO_ROUND_M 0x0000000f
806 #define VIA_CRYPT_CWLO_ALG_M 0x00000070
807 #define VIA_CRYPT_CWLO_ALG_AES 0x00000000
808 #define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080
809 #define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000
810 #define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080
811 #define VIA_CRYPT_CWLO_NORMAL 0x00000000
812 #define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100
813 #define VIA_CRYPT_CWLO_ENCRYPT 0x00000000
814 #define VIA_CRYPT_CWLO_DECRYPT 0x00000200
815 #define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */
816 #define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */
817 #define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */
819 #endif /* !_MACHINE_SPECIALREG_H_ */
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