2 * Copyright (c) 2004 John Baldwin <jhb@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 * The ELCR is a register that controls the trigger mode and polarity of
32 * EISA and ISA interrupts. In FreeBSD 3.x and 4.x, the ELCR was only
33 * consulted for determining the appropriate trigger mode of EISA
34 * interrupts when using an APIC. However, it seems that almost all
35 * systems that include PCI also include an ELCR that manages the ISA
36 * IRQs 0 through 15. Thus, we check for the presence of an ELCR on
37 * every machine by checking to see if the values found at bootup are
38 * sane. Note that the polarity of ISA and EISA IRQs are linked to the
39 * trigger mode. All edge triggered IRQs use active-hi polarity, and
40 * all level triggered interrupts use active-lo polarity.
42 * The format of the ELCR is simple: it is a 16-bit bitmap where bit 0
43 * controls IRQ 0, bit 1 controls IRQ 1, etc. If the bit is zero, the
44 * associated IRQ is edge triggered. If the bit is one, the IRQ is
48 #include <sys/param.h>
50 #include <sys/systm.h>
51 #include <machine/intr_machdep.h>
53 #define ELCR_PORT 0x4d0
54 #define ELCR_MASK(irq) (1 << (irq))
56 static int elcr_status;
60 * Check to see if we have what looks like a valid ELCR. We do this by
61 * verifying that IRQs 0, 1, 2, and 13 are all edge triggered.
68 elcr_status = inb(ELCR_PORT) | inb(ELCR_PORT + 1) << 8;
69 if ((elcr_status & (ELCR_MASK(0) | ELCR_MASK(1) | ELCR_MASK(2) |
70 ELCR_MASK(8) | ELCR_MASK(13))) != 0)
73 printf("ELCR Found. ISA IRQs programmed as:\n");
74 for (i = 0; i < 16; i++)
77 for (i = 0; i < 16; i++)
78 if (elcr_status & ELCR_MASK(i))
84 if (resource_disabled("elcr", 0))
91 * Returns 1 for level trigger, 0 for edge.
94 elcr_read_trigger(u_int irq)
97 KASSERT(elcr_found, ("%s: no ELCR was found!", __func__));
98 KASSERT(irq <= 15, ("%s: invalid IRQ %u", __func__, irq));
99 if (elcr_status & ELCR_MASK(irq))
100 return (INTR_TRIGGER_LEVEL);
102 return (INTR_TRIGGER_EDGE);
106 * Set the trigger mode for a specified IRQ. Mode of 0 means edge triggered,
107 * and a mode of 1 means level triggered.
110 elcr_write_trigger(u_int irq, enum intr_trigger trigger)
114 KASSERT(elcr_found, ("%s: no ELCR was found!", __func__));
115 KASSERT(irq <= 15, ("%s: invalid IRQ %u", __func__, irq));
116 if (trigger == INTR_TRIGGER_LEVEL)
117 new_status = elcr_status | ELCR_MASK(irq);
119 new_status = elcr_status & ~ELCR_MASK(irq);
120 if (new_status == elcr_status)
122 elcr_status = new_status;
124 outb(ELCR_PORT + 1, elcr_status >> 8);
126 outb(ELCR_PORT, elcr_status & 0xff);
133 KASSERT(elcr_found, ("%s: no ELCR was found!", __func__));
134 outb(ELCR_PORT, elcr_status & 0xff);
135 outb(ELCR_PORT + 1, elcr_status >> 8);