2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
39 #include <sys/sysctl.h>
41 #include <dev/pci/pcivar.h>
42 #include <dev/pci/pcireg.h>
43 #include <dev/pci/pcib_private.h>
44 #include <isa/isavar.h>
46 #include <machine/md_var.h>
48 #include <machine/legacyvar.h>
49 #include <machine/pci_cfgreg.h>
50 #include <machine/resource.h>
55 legacy_pcib_maxslots(device_t dev)
60 /* read configuration space register */
63 legacy_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
66 return(pci_cfgregread(bus, slot, func, reg, bytes));
69 /* write configuration space register */
72 legacy_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
73 u_int reg, uint32_t data, int bytes)
75 pci_cfgregwrite(bus, slot, func, reg, data, bytes);
81 legacy_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
85 return (pci_pir_route_interrupt(pci_get_bus(dev), pci_get_slot(dev),
86 pci_get_function(dev), pin));
88 /* No routing possible */
89 return (PCI_INVALID_IRQ);
93 /* Pass MSI requests up to the nexus. */
96 legacy_pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount,
101 bus = device_get_parent(pcib);
102 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
107 legacy_pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
111 bus = device_get_parent(pcib);
112 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
116 legacy_pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
120 int error, func, slot;
122 bus = device_get_parent(pcib);
123 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data);
127 slot = legacy_get_pcislot(pcib);
128 func = legacy_get_pcifunc(pcib);
129 if (slot == -1 || func == -1)
131 hostb = pci_find_bsf(0, slot, func);
132 KASSERT(hostb != NULL, ("%s: missing hostb for 0:%d:%d", __func__,
134 pci_ht_map_msi(hostb, *addr);
140 legacy_pcib_is_host_bridge(int bus, int slot, int func,
141 uint32_t id, uint8_t class, uint8_t subclass,
145 const char *s = NULL;
146 static uint8_t pxb[4]; /* hack for 450nx */
152 s = "Intel 824?? host to PCI bridge";
153 /* XXX This is a guess */
154 /* *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x41, 1); */
158 s = "Intel 82810 (i810 GMCH) Host To Hub bridge";
161 s = "Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge";
164 s = "Intel 82810E (i810E GMCH) Host To Hub bridge";
167 s = "Intel 82815 (i815 GMCH) Host To Hub bridge";
170 s = "Intel 82443LX (440 LX) host to PCI bridge";
173 s = "Intel 82443BX (440 BX) host to PCI bridge";
176 s = "Intel 82443BX host to PCI bridge (AGP disabled)";
179 s = "Intel 82443MX host to PCI bridge";
182 s = "Intel 82443GX host to PCI bridge";
185 s = "Intel 82443GX host to AGP bridge";
188 s = "Intel 82443GX host to PCI bridge (AGP disabled)";
191 s = "Intel 82454KX/GX (Orion) host to PCI bridge";
192 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x4a, 1);
196 * For the 450nx chipset, there is a whole bundle of
197 * things pretending to be host bridges. The MIOC will
198 * be seen first and isn't really a pci bridge (the
199 * actual busses are attached to the PXB's). We need to
200 * read the registers of the MIOC to figure out the
201 * bus numbers for the PXB channels.
203 * Since the MIOC doesn't have a pci bus attached, we
204 * pretend it wasn't there.
206 pxb[0] = legacy_pcib_read_config(0, bus, slot, func,
207 0xd0, 1); /* BUSNO[0] */
208 pxb[1] = legacy_pcib_read_config(0, bus, slot, func,
209 0xd1, 1) + 1; /* SUBA[0]+1 */
210 pxb[2] = legacy_pcib_read_config(0, bus, slot, func,
211 0xd3, 1); /* BUSNO[1] */
212 pxb[3] = legacy_pcib_read_config(0, bus, slot, func,
213 0xd4, 1) + 1; /* SUBA[1]+1 */
218 s = "Intel 82454NX PXB#0, Bus#A";
222 s = "Intel 82454NX PXB#0, Bus#B";
226 s = "Intel 82454NX PXB#1, Bus#A";
230 s = "Intel 82454NX PXB#1, Bus#B";
236 s = "Intel 82845 Host to PCI bridge";
239 /* AMD -- vendor 0x1022 */
241 s = "AMD Elan SC520 host to PCI bridge";
243 init_AMD_Elan_sc520();
246 "*** WARNING: missing CPU_ELAN -- timekeeping may be wrong\n");
250 s = "AMD-751 host to PCI bridge";
253 s = "AMD-761 host to PCI bridge";
256 /* SiS -- vendor 0x1039 */
267 s = "SiS 5591 host to PCI bridge";
270 s = "SiS 5591 host to AGP bridge";
273 /* VLSI -- vendor 0x1004 */
275 s = "VLSI 82C592 Host to PCI bridge";
278 /* XXX Here is MVP3, I got the datasheet but NO M/B to test it */
279 /* totally. Please let me know if anything wrong. -F */
280 /* XXX need info on the MVP3 -- any takers? */
282 s = "VIA 82C598MVP (Apollo MVP3) host bridge";
285 /* AcerLabs -- vendor 0x10b9 */
286 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
287 /* id is '10b9" but the register always shows "10b9". -Foxfair */
289 s = "AcerLabs M1541 (Aladdin-V) PCI host bridge";
292 /* OPTi -- vendor 0x1045 */
294 s = "OPTi 82C700 host to PCI bridge";
297 s = "OPTi 82C822 host to PCI Bridge";
300 /* ServerWorks -- vendor 0x1166 */
302 s = "ServerWorks NB6536 2.0HE host to PCI bridge";
303 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
312 case 0x010f1014: /* IBM re-badged ServerWorks chipset */
313 s = "ServerWorks host to PCI bridge";
314 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
318 s = "ServerWorks NB6635 3.0LE host to PCI bridge";
319 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
323 s = "ServerWorks CIOB30 host to PCI bridge";
324 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
329 case 0x03021014: /* IBM re-badged ServerWorks chipset */
330 s = "ServerWorks CMIC-HE host to PCI-X bridge";
331 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
334 /* XXX unknown chipset, but working */
340 s = "ServerWorks host to PCI bridge(unknown chipset)";
341 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
344 /* Compaq/HP -- vendor 0x0e11 */
346 s = "Compaq/HP Model 6010 HotPlug PCI Bridge";
347 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0xc8, 1);
350 /* Integrated Micro Solutions -- vendor 0x10e0 */
352 s = "Integrated Micro Solutions VL Bridge";
356 if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
357 s = "Host to PCI bridge";
363 const char *s = NULL;
366 if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
367 s = "Host to PCI bridge";
373 * Scan the first pci bus for host-pci bridges and add pcib instances
374 * to the nexus for each bridge.
377 legacy_pcib_identify(driver_t *driver, device_t parent)
386 devclass_t pci_devclass;
388 if (pci_cfgregopen() == 0)
391 * Check to see if we haven't already had a PCI bus added
392 * via some other means. If we have, bail since otherwise
393 * we're going to end up duplicating it.
395 if ((pci_devclass = devclass_find("pci")) &&
396 devclass_get_device(pci_devclass, 0))
402 for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
404 hdrtype = legacy_pcib_read_config(0, bus, slot, func,
407 * When enumerating bus devices, the standard says that
408 * one should check the header type and ignore the slots whose
409 * header types that the software doesn't know about. We use
410 * this to filter out devices.
412 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
414 if ((hdrtype & PCIM_MFDEV) &&
415 (!found_orion || hdrtype != 0xff))
416 pcifunchigh = PCI_FUNCMAX;
419 for (func = 0; func <= pcifunchigh; func++) {
421 * Read the IDs and class from the device.
424 uint8_t class, subclass, busnum;
429 id = legacy_pcib_read_config(0, bus, slot, func,
433 class = legacy_pcib_read_config(0, bus, slot, func,
435 subclass = legacy_pcib_read_config(0, bus, slot, func,
438 s = legacy_pcib_is_host_bridge(bus, slot, func,
445 * Check to see if the physical bus has already
446 * been seen. Eg: hybrid 32 and 64 bit host
447 * bridges to the same logical bus.
449 if (device_get_children(parent, &devs, &ndevs) == 0) {
450 for (i = 0; s != NULL && i < ndevs; i++) {
451 if (strcmp(device_get_name(devs[i]),
454 if (legacy_get_pcibus(devs[i]) == busnum)
463 * Add at priority 100 to make sure we
464 * go after any motherboard resources
466 child = BUS_ADD_CHILD(parent, 100,
468 device_set_desc(child, s);
469 legacy_set_pcibus(child, busnum);
470 legacy_set_pcislot(child, slot);
471 legacy_set_pcifunc(child, func);
474 if (id == 0x12258086)
476 if (id == 0x84c48086)
480 if (found824xx && bus == 0) {
486 * Make sure we add at least one bridge since some old
487 * hardware doesn't actually have a host-pci bridge device.
488 * Note that pci_cfgregopen() thinks we have PCI devices..
493 "legacy_pcib_identify: no bridge found, adding pcib0 anyway\n");
494 child = BUS_ADD_CHILD(parent, 100, "pcib", 0);
495 legacy_set_pcibus(child, 0);
500 legacy_pcib_probe(device_t dev)
503 if (pci_cfgregopen() == 0)
509 legacy_pcib_attach(device_t dev)
516 bus = pcib_get_bus(dev);
519 * Look for a PCI BIOS interrupt routing table as that will be
520 * our method of routing interrupts if we have one.
522 if (pci_pir_probe(bus, 0)) {
523 pir = BUS_ADD_CHILD(device_get_parent(dev), 0, "pir", 0);
525 device_probe_and_attach(pir);
528 device_add_child(dev, "pci", bus);
529 return bus_generic_attach(dev);
533 legacy_pcib_read_ivar(device_t dev, device_t child, int which,
538 case PCIB_IVAR_DOMAIN:
542 *result = legacy_get_pcibus(dev);
549 legacy_pcib_write_ivar(device_t dev, device_t child, int which,
554 case PCIB_IVAR_DOMAIN:
557 legacy_set_pcibus(dev, value);
564 * Helper routine for x86 Host-PCI bridge driver resource allocation.
565 * This is used to adjust the start address of wildcard allocation
566 * requests to avoid low addresses that are known to be problematic.
568 * If no memory preference is given, use upper 32MB slot most BIOSes
569 * use for their memory window. This is typically only used on older
570 * laptops that don't have PCI busses behind a PCI bridge, so assuming
571 * > 32MB is likely OK.
573 * However, this can cause problems for other chipsets, so we make
574 * this tunable by hw.pci.host_mem_start.
576 SYSCTL_DECL(_hw_pci);
578 static unsigned long host_mem_start = 0x80000000;
579 TUNABLE_ULONG("hw.pci.host_mem_start", &host_mem_start);
580 SYSCTL_ULONG(_hw_pci, OID_AUTO, host_mem_start, CTLFLAG_RDTUN, &host_mem_start,
581 0, "Limit the host bridge memory to being above this address.");
584 hostb_alloc_start(int type, u_long start, u_long end, u_long count)
587 if (start + count - 1 != end) {
588 if (type == SYS_RES_MEMORY && start < host_mem_start)
589 start = host_mem_start;
590 if (type == SYS_RES_IOPORT && start < 0x1000)
597 legacy_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
598 u_long start, u_long end, u_long count, u_int flags)
601 start = hostb_alloc_start(type, start, end, count);
602 return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
606 static device_method_t legacy_pcib_methods[] = {
607 /* Device interface */
608 DEVMETHOD(device_identify, legacy_pcib_identify),
609 DEVMETHOD(device_probe, legacy_pcib_probe),
610 DEVMETHOD(device_attach, legacy_pcib_attach),
611 DEVMETHOD(device_shutdown, bus_generic_shutdown),
612 DEVMETHOD(device_suspend, bus_generic_suspend),
613 DEVMETHOD(device_resume, bus_generic_resume),
616 DEVMETHOD(bus_read_ivar, legacy_pcib_read_ivar),
617 DEVMETHOD(bus_write_ivar, legacy_pcib_write_ivar),
618 DEVMETHOD(bus_alloc_resource, legacy_pcib_alloc_resource),
619 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
620 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
621 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
622 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
623 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
624 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
627 DEVMETHOD(pcib_maxslots, legacy_pcib_maxslots),
628 DEVMETHOD(pcib_read_config, legacy_pcib_read_config),
629 DEVMETHOD(pcib_write_config, legacy_pcib_write_config),
630 DEVMETHOD(pcib_route_interrupt, legacy_pcib_route_interrupt),
631 DEVMETHOD(pcib_alloc_msi, legacy_pcib_alloc_msi),
632 DEVMETHOD(pcib_release_msi, pcib_release_msi),
633 DEVMETHOD(pcib_alloc_msix, legacy_pcib_alloc_msix),
634 DEVMETHOD(pcib_release_msix, pcib_release_msix),
635 DEVMETHOD(pcib_map_msi, legacy_pcib_map_msi),
640 static devclass_t hostb_devclass;
642 DEFINE_CLASS_0(pcib, legacy_pcib_driver, legacy_pcib_methods, 1);
643 DRIVER_MODULE(pcib, legacy, legacy_pcib_driver, hostb_devclass, 0, 0);
647 * Install placeholder to claim the resources owned by the
648 * PCI bus interface. This could be used to extract the
649 * config space registers in the extreme case where the PnP
650 * ID is available and the PCI BIOS isn't, but for now we just
651 * eat the PnP ID and do nothing else.
653 * XXX we should silence this probe, as it will generally confuse
656 static struct isa_pnp_id pcibus_pnp_ids[] = {
657 { 0x030ad041 /* PNP0A03 */, "PCI Bus" },
658 { 0x080ad041 /* PNP0A08 */, "PCIe Bus" },
663 pcibus_pnp_probe(device_t dev)
667 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, pcibus_pnp_ids)) <= 0)
673 pcibus_pnp_attach(device_t dev)
678 static device_method_t pcibus_pnp_methods[] = {
679 /* Device interface */
680 DEVMETHOD(device_probe, pcibus_pnp_probe),
681 DEVMETHOD(device_attach, pcibus_pnp_attach),
682 DEVMETHOD(device_detach, bus_generic_detach),
683 DEVMETHOD(device_shutdown, bus_generic_shutdown),
684 DEVMETHOD(device_suspend, bus_generic_suspend),
685 DEVMETHOD(device_resume, bus_generic_resume),
689 static devclass_t pcibus_pnp_devclass;
691 DEFINE_CLASS_0(pcibus_pnp, pcibus_pnp_driver, pcibus_pnp_methods, 1);
692 DRIVER_MODULE(pcibus_pnp, isa, pcibus_pnp_driver, pcibus_pnp_devclass, 0, 0);
696 * Provide a PCI-PCI bridge driver for PCI busses behind PCI-PCI bridges
697 * that appear in the PCIBIOS Interrupt Routing Table to use the routing
698 * table for interrupt routing when possible.
700 static int pcibios_pcib_probe(device_t bus);
702 static device_method_t pcibios_pcib_pci_methods[] = {
703 /* Device interface */
704 DEVMETHOD(device_probe, pcibios_pcib_probe),
707 DEVMETHOD(pcib_route_interrupt, legacy_pcib_route_interrupt),
712 static devclass_t pcib_devclass;
714 DEFINE_CLASS_1(pcib, pcibios_pcib_driver, pcibios_pcib_pci_methods,
715 sizeof(struct pcib_softc), pcib_driver);
716 DRIVER_MODULE(pcibios_pcib, pci, pcibios_pcib_driver, pcib_devclass, 0, 0);
719 pcibios_pcib_probe(device_t dev)
723 if ((pci_get_class(dev) != PCIC_BRIDGE) ||
724 (pci_get_subclass(dev) != PCIS_BRIDGE_PCI))
726 bus = pci_read_config(dev, PCIR_SECBUS_1, 1);
729 if (!pci_pir_probe(bus, 1))
731 device_set_desc(dev, "PCIBIOS PCI-PCI bridge");