sys/x86/x86/identcpu.c

   1 /*-
   2  * Copyright (c) 1992 Terrence R. Lambert.
   3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
   4  * Copyright (c) 1997 KATO Takenori.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * William Jolitz.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by the University of
  21  *      California, Berkeley and its contributors.
  22  * 4. Neither the name of the University nor the names of its contributors
  23  *    may be used to endorse or promote products derived from this software
  24  *    without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  36  * SUCH DAMAGE.
  37  *
  38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include "opt_cpu.h"
  45
  46 #include <sys/param.h>
  47 #include <sys/bus.h>
  48 #include <sys/cpu.h>
  49 #include <sys/eventhandler.h>
  50 #include <sys/systm.h>
  51 #include <sys/kernel.h>
  52 #include <sys/sysctl.h>
  53 #include <sys/power.h>
  54
  55 #include <machine/asmacros.h>
  56 #include <machine/clock.h>
  57 #include <machine/cputypes.h>
  58 #include <machine/frame.h>
  59 #include <machine/intr_machdep.h>
  60 #include <machine/md_var.h>
  61 #include <machine/segments.h>
  62 #include <machine/specialreg.h>
  63
  64 #include <amd64/vmm/intel/vmx_controls.h>
  65 #include <x86/isa/icu.h>
  66
  67 #ifdef __i386__
  68 #define IDENTBLUE_CYRIX486      0
  69 #define IDENTBLUE_IBMCPU        1
  70 #define IDENTBLUE_CYRIXM2       2
  71
  72 static void identifycyrix(void);
  73 static void print_transmeta_info(void);
  74 #endif
  75 static u_int find_cpu_vendor_id(void);
  76 static void print_AMD_info(void);
  77 static void print_INTEL_info(void);
  78 static void print_INTEL_TLB(u_int data);
  79 static void print_via_padlock_info(void);
  80 static void print_vmx_info(void);
  81
  82 int     cpu_class;
  83 char machine[] = MACHINE;
  84
  85 #ifdef __amd64__
  86 #ifdef SCTL_MASK32
  87 extern int adaptive_machine_arch;
  88 #endif
  89
  90 static int
  91 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
  92 {
  93 #ifdef SCTL_MASK32
  94         static const char machine32[] = "i386";
  95 #endif
  96         int error;
  97
  98 #ifdef SCTL_MASK32
  99         if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
 100                 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
 101         else
 102 #endif
 103                 error = SYSCTL_OUT(req, machine, sizeof(machine));
 104         return (error);
 105
 106 }
 107 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD,
 108     NULL, 0, sysctl_hw_machine, "A", "Machine class");
 109 #else
 110 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
 111     machine, 0, "Machine class");
 112 #endif
 113
 114 static char cpu_model[128];
 115 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
 116     cpu_model, 0, "Machine model");
 117
 118 static int hw_clockrate;
 119 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
 120     &hw_clockrate, 0, "CPU instruction clock rate");
 121
 122 static eventhandler_tag tsc_post_tag;
 123
 124 static char cpu_brand[48];
 125
 126 #ifdef __i386__
 127 #define MAX_BRAND_INDEX 8
 128
 129 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
 130         NULL,                   /* No brand */
 131         "Intel Celeron",
 132         "Intel Pentium III",
 133         "Intel Pentium III Xeon",
 134         NULL,
 135         NULL,
 136         NULL,
 137         NULL,
 138         "Intel Pentium 4"
 139 };
 140 #endif
 141
 142 static struct {
 143         char    *cpu_name;
 144         int     cpu_class;
 145 } cpus[] = {
 146 #ifdef __i386__
 147         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
 148         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
 149         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
 150         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
 151         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
 152         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
 153         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
 154         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
 155         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
 156         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
 157         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
 158         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
 159         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
 160         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
 161         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
 162         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
 163         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
 164 #else
 165         { "Clawhammer",         CPUCLASS_K8 },          /* CPU_CLAWHAMMER */
 166         { "Sledgehammer",       CPUCLASS_K8 },          /* CPU_SLEDGEHAMMER */
 167 #endif
 168 };
 169
 170 static struct {
 171         char    *vendor;
 172         u_int   vendor_id;
 173 } cpu_vendors[] = {
 174         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
 175         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
 176         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
 177 #ifdef __i386__
 178         { NSC_VENDOR_ID,        CPU_VENDOR_NSC },       /* Geode by NSC */
 179         { CYRIX_VENDOR_ID,      CPU_VENDOR_CYRIX },     /* CyrixInstead */
 180         { TRANSMETA_VENDOR_ID,  CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
 181         { SIS_VENDOR_ID,        CPU_VENDOR_SIS },       /* SiS SiS SiS  */
 182         { UMC_VENDOR_ID,        CPU_VENDOR_UMC },       /* UMC UMC UMC  */
 183         { NEXGEN_VENDOR_ID,     CPU_VENDOR_NEXGEN },    /* NexGenDriven */
 184         { RISE_VENDOR_ID,       CPU_VENDOR_RISE },      /* RiseRiseRise */
 185 #if 0
 186         /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
 187         { "TransmetaCPU",       CPU_VENDOR_TRANSMETA },
 188 #endif
 189 #endif
 190 };
 191
 192 void
 193 printcpuinfo(void)
 194 {
 195         u_int regs[4], i;
 196         char *brand;
 197
 198         cpu_class = cpus[cpu].cpu_class;
 199         printf("CPU: ");
 200         strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
 201
 202         /* Check for extended CPUID information and a processor name. */
 203         if (cpu_exthigh >= 0x80000004) {
 204                 brand = cpu_brand;
 205                 for (i = 0x80000002; i < 0x80000005; i++) {
 206                         do_cpuid(i, regs);
 207                         memcpy(brand, regs, sizeof(regs));
 208                         brand += sizeof(regs);
 209                 }
 210         }
 211
 212         switch (cpu_vendor_id) {
 213         case CPU_VENDOR_INTEL:
 214 #ifdef __i386__
 215                 if ((cpu_id & 0xf00) > 0x300) {
 216                         u_int brand_index;
 217
 218                         cpu_model[0] = '\0';
 219
 220                         switch (cpu_id & 0x3000) {
 221                         case 0x1000:
 222                                 strcpy(cpu_model, "Overdrive ");
 223                                 break;
 224                         case 0x2000:
 225                                 strcpy(cpu_model, "Dual ");
 226                                 break;
 227                         }
 228
 229                         switch (cpu_id & 0xf00) {
 230                         case 0x400:
 231                                 strcat(cpu_model, "i486 ");
 232                                 /* Check the particular flavor of 486 */
 233                                 switch (cpu_id & 0xf0) {
 234                                 case 0x00:
 235                                 case 0x10:
 236                                         strcat(cpu_model, "DX");
 237                                         break;
 238                                 case 0x20:
 239                                         strcat(cpu_model, "SX");
 240                                         break;
 241                                 case 0x30:
 242                                         strcat(cpu_model, "DX2");
 243                                         break;
 244                                 case 0x40:
 245                                         strcat(cpu_model, "SL");
 246                                         break;
 247                                 case 0x50:
 248                                         strcat(cpu_model, "SX2");
 249                                         break;
 250                                 case 0x70:
 251                                         strcat(cpu_model,
 252                                             "DX2 Write-Back Enhanced");
 253                                         break;
 254                                 case 0x80:
 255                                         strcat(cpu_model, "DX4");
 256                                         break;
 257                                 }
 258                                 break;
 259                         case 0x500:
 260                                 /* Check the particular flavor of 586 */
 261                                 strcat(cpu_model, "Pentium");
 262                                 switch (cpu_id & 0xf0) {
 263                                 case 0x00:
 264                                         strcat(cpu_model, " A-step");
 265                                         break;
 266                                 case 0x10:
 267                                         strcat(cpu_model, "/P5");
 268                                         break;
 269                                 case 0x20:
 270                                         strcat(cpu_model, "/P54C");
 271                                         break;
 272                                 case 0x30:
 273                                         strcat(cpu_model, "/P24T");
 274                                         break;
 275                                 case 0x40:
 276                                         strcat(cpu_model, "/P55C");
 277                                         break;
 278                                 case 0x70:
 279                                         strcat(cpu_model, "/P54C");
 280                                         break;
 281                                 case 0x80:
 282                                         strcat(cpu_model, "/P55C (quarter-micron)");
 283                                         break;
 284                                 default:
 285                                         /* nothing */
 286                                         break;
 287                                 }
 288 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 289                                 /*
 290                                  * XXX - If/when Intel fixes the bug, this
 291                                  * should also check the version of the
 292                                  * CPU, not just that it's a Pentium.
 293                                  */
 294                                 has_f00f_bug = 1;
 295 #endif
 296                                 break;
 297                         case 0x600:
 298                                 /* Check the particular flavor of 686 */
 299                                 switch (cpu_id & 0xf0) {
 300                                 case 0x00:
 301                                         strcat(cpu_model, "Pentium Pro A-step");
 302                                         break;
 303                                 case 0x10:
 304                                         strcat(cpu_model, "Pentium Pro");
 305                                         break;
 306                                 case 0x30:
 307                                 case 0x50:
 308                                 case 0x60:
 309                                         strcat(cpu_model,
 310                                 "Pentium II/Pentium II Xeon/Celeron");
 311                                         cpu = CPU_PII;
 312                                         break;
 313                                 case 0x70:
 314                                 case 0x80:
 315                                 case 0xa0:
 316                                 case 0xb0:
 317                                         strcat(cpu_model,
 318                                         "Pentium III/Pentium III Xeon/Celeron");
 319                                         cpu = CPU_PIII;
 320                                         break;
 321                                 default:
 322                                         strcat(cpu_model, "Unknown 80686");
 323                                         break;
 324                                 }
 325                                 break;
 326                         case 0xf00:
 327                                 strcat(cpu_model, "Pentium 4");
 328                                 cpu = CPU_P4;
 329                                 break;
 330                         default:
 331                                 strcat(cpu_model, "unknown");
 332                                 break;
 333                         }
 334
 335                         /*
 336                          * If we didn't get a brand name from the extended
 337                          * CPUID, try to look it up in the brand table.
 338                          */
 339                         if (cpu_high > 0 && *cpu_brand == '\0') {
 340                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
 341                                 if (brand_index <= MAX_BRAND_INDEX &&
 342                                     cpu_brandtable[brand_index] != NULL)
 343                                         strcpy(cpu_brand,
 344                                             cpu_brandtable[brand_index]);
 345                         }
 346                 }
 347 #else
 348                 /* Please make up your mind folks! */
 349                 strcat(cpu_model, "EM64T");
 350 #endif
 351                 break;
 352         case CPU_VENDOR_AMD:
 353                 /*
 354                  * Values taken from AMD Processor Recognition
 355                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
 356                  * (also describes ``Features'' encodings.
 357                  */
 358                 strcpy(cpu_model, "AMD ");
 359 #ifdef __i386__
 360                 switch (cpu_id & 0xFF0) {
 361                 case 0x410:
 362                         strcat(cpu_model, "Standard Am486DX");
 363                         break;
 364                 case 0x430:
 365                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
 366                         break;
 367                 case 0x470:
 368                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
 369                         break;
 370                 case 0x480:
 371                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
 372                         break;
 373                 case 0x490:
 374                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
 375                         break;
 376                 case 0x4E0:
 377                         strcat(cpu_model, "Am5x86 Write-Through");
 378                         break;
 379                 case 0x4F0:
 380                         strcat(cpu_model, "Am5x86 Write-Back");
 381                         break;
 382                 case 0x500:
 383                         strcat(cpu_model, "K5 model 0");
 384                         break;
 385                 case 0x510:
 386                         strcat(cpu_model, "K5 model 1");
 387                         break;
 388                 case 0x520:
 389                         strcat(cpu_model, "K5 PR166 (model 2)");
 390                         break;
 391                 case 0x530:
 392                         strcat(cpu_model, "K5 PR200 (model 3)");
 393                         break;
 394                 case 0x560:
 395                         strcat(cpu_model, "K6");
 396                         break;
 397                 case 0x570:
 398                         strcat(cpu_model, "K6 266 (model 1)");
 399                         break;
 400                 case 0x580:
 401                         strcat(cpu_model, "K6-2");
 402                         break;
 403                 case 0x590:
 404                         strcat(cpu_model, "K6-III");
 405                         break;
 406                 case 0x5a0:
 407                         strcat(cpu_model, "Geode LX");
 408                         /*
 409                          * Make sure the TSC runs through suspension,
 410                          * otherwise we can't use it as timecounter
 411                          */
 412                         wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL);
 413                         break;
 414                 default:
 415                         strcat(cpu_model, "Unknown");
 416                         break;
 417                 }
 418 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
 419                 if ((cpu_id & 0xf00) == 0x500) {
 420                         if (((cpu_id & 0x0f0) > 0)
 421                             && ((cpu_id & 0x0f0) < 0x60)
 422                             && ((cpu_id & 0x00f) > 3))
 423                                 enable_K5_wt_alloc();
 424                         else if (((cpu_id & 0x0f0) > 0x80)
 425                                  || (((cpu_id & 0x0f0) == 0x80)
 426                                      && (cpu_id & 0x00f) > 0x07))
 427                                 enable_K6_2_wt_alloc();
 428                         else if ((cpu_id & 0x0f0) > 0x50)
 429                                 enable_K6_wt_alloc();
 430                 }
 431 #endif
 432 #else
 433                 if ((cpu_id & 0xf00) == 0xf00)
 434                         strcat(cpu_model, "AMD64 Processor");
 435                 else
 436                         strcat(cpu_model, "Unknown");
 437 #endif
 438                 break;
 439 #ifdef __i386__
 440         case CPU_VENDOR_CYRIX:
 441                 strcpy(cpu_model, "Cyrix ");
 442                 switch (cpu_id & 0xff0) {
 443                 case 0x440:
 444                         strcat(cpu_model, "MediaGX");
 445                         break;
 446                 case 0x520:
 447                         strcat(cpu_model, "6x86");
 448                         break;
 449                 case 0x540:
 450                         cpu_class = CPUCLASS_586;
 451                         strcat(cpu_model, "GXm");
 452                         break;
 453                 case 0x600:
 454                         strcat(cpu_model, "6x86MX");
 455                         break;
 456                 default:
 457                         /*
 458                          * Even though CPU supports the cpuid
 459                          * instruction, it can be disabled.
 460                          * Therefore, this routine supports all Cyrix
 461                          * CPUs.
 462                          */
 463                         switch (cyrix_did & 0xf0) {
 464                         case 0x00:
 465                                 switch (cyrix_did & 0x0f) {
 466                                 case 0x00:
 467                                         strcat(cpu_model, "486SLC");
 468                                         break;
 469                                 case 0x01:
 470                                         strcat(cpu_model, "486DLC");
 471                                         break;
 472                                 case 0x02:
 473                                         strcat(cpu_model, "486SLC2");
 474                                         break;
 475                                 case 0x03:
 476                                         strcat(cpu_model, "486DLC2");
 477                                         break;
 478                                 case 0x04:
 479                                         strcat(cpu_model, "486SRx");
 480                                         break;
 481                                 case 0x05:
 482                                         strcat(cpu_model, "486DRx");
 483                                         break;
 484                                 case 0x06:
 485                                         strcat(cpu_model, "486SRx2");
 486                                         break;
 487                                 case 0x07:
 488                                         strcat(cpu_model, "486DRx2");
 489                                         break;
 490                                 case 0x08:
 491                                         strcat(cpu_model, "486SRu");
 492                                         break;
 493                                 case 0x09:
 494                                         strcat(cpu_model, "486DRu");
 495                                         break;
 496                                 case 0x0a:
 497                                         strcat(cpu_model, "486SRu2");
 498                                         break;
 499                                 case 0x0b:
 500                                         strcat(cpu_model, "486DRu2");
 501                                         break;
 502                                 default:
 503                                         strcat(cpu_model, "Unknown");
 504                                         break;
 505                                 }
 506                                 break;
 507                         case 0x10:
 508                                 switch (cyrix_did & 0x0f) {
 509                                 case 0x00:
 510                                         strcat(cpu_model, "486S");
 511                                         break;
 512                                 case 0x01:
 513                                         strcat(cpu_model, "486S2");
 514                                         break;
 515                                 case 0x02:
 516                                         strcat(cpu_model, "486Se");
 517                                         break;
 518                                 case 0x03:
 519                                         strcat(cpu_model, "486S2e");
 520                                         break;
 521                                 case 0x0a:
 522                                         strcat(cpu_model, "486DX");
 523                                         break;
 524                                 case 0x0b:
 525                                         strcat(cpu_model, "486DX2");
 526                                         break;
 527                                 case 0x0f:
 528                                         strcat(cpu_model, "486DX4");
 529                                         break;
 530                                 default:
 531                                         strcat(cpu_model, "Unknown");
 532                                         break;
 533                                 }
 534                                 break;
 535                         case 0x20:
 536                                 if ((cyrix_did & 0x0f) < 8)
 537                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
 538                                 else
 539                                         strcat(cpu_model, "5x86");
 540                                 break;
 541                         case 0x30:
 542                                 strcat(cpu_model, "6x86");
 543                                 break;
 544                         case 0x40:
 545                                 if ((cyrix_did & 0xf000) == 0x3000) {
 546                                         cpu_class = CPUCLASS_586;
 547                                         strcat(cpu_model, "GXm");
 548                                 } else
 549                                         strcat(cpu_model, "MediaGX");
 550                                 break;
 551                         case 0x50:
 552                                 strcat(cpu_model, "6x86MX");
 553                                 break;
 554                         case 0xf0:
 555                                 switch (cyrix_did & 0x0f) {
 556                                 case 0x0d:
 557                                         strcat(cpu_model, "Overdrive CPU");
 558                                         break;
 559                                 case 0x0e:
 560                                         strcpy(cpu_model, "Texas Instruments 486SXL");
 561                                         break;
 562                                 case 0x0f:
 563                                         strcat(cpu_model, "486SLC/DLC");
 564                                         break;
 565                                 default:
 566                                         strcat(cpu_model, "Unknown");
 567                                         break;
 568                                 }
 569                                 break;
 570                         default:
 571                                 strcat(cpu_model, "Unknown");
 572                                 break;
 573                         }
 574                         break;
 575                 }
 576                 break;
 577         case CPU_VENDOR_RISE:
 578                 strcpy(cpu_model, "Rise ");
 579                 switch (cpu_id & 0xff0) {
 580                 case 0x500:     /* 6401 and 6441 (Kirin) */
 581                 case 0x520:     /* 6510 (Lynx) */
 582                         strcat(cpu_model, "mP6");
 583                         break;
 584                 default:
 585                         strcat(cpu_model, "Unknown");
 586                 }
 587                 break;
 588 #endif
 589         case CPU_VENDOR_CENTAUR:
 590 #ifdef __i386__
 591                 switch (cpu_id & 0xff0) {
 592                 case 0x540:
 593                         strcpy(cpu_model, "IDT WinChip C6");
 594                         break;
 595                 case 0x580:
 596                         strcpy(cpu_model, "IDT WinChip 2");
 597                         break;
 598                 case 0x590:
 599                         strcpy(cpu_model, "IDT WinChip 3");
 600                         break;
 601                 case 0x660:
 602                         strcpy(cpu_model, "VIA C3 Samuel");
 603                         break;
 604                 case 0x670:
 605                         if (cpu_id & 0x8)
 606                                 strcpy(cpu_model, "VIA C3 Ezra");
 607                         else
 608                                 strcpy(cpu_model, "VIA C3 Samuel 2");
 609                         break;
 610                 case 0x680:
 611                         strcpy(cpu_model, "VIA C3 Ezra-T");
 612                         break;
 613                 case 0x690:
 614                         strcpy(cpu_model, "VIA C3 Nehemiah");
 615                         break;
 616                 case 0x6a0:
 617                 case 0x6d0:
 618                         strcpy(cpu_model, "VIA C7 Esther");
 619                         break;
 620                 case 0x6f0:
 621                         strcpy(cpu_model, "VIA Nano");
 622                         break;
 623                 default:
 624                         strcpy(cpu_model, "VIA/IDT Unknown");
 625                 }
 626 #else
 627                 strcpy(cpu_model, "VIA ");
 628                 if ((cpu_id & 0xff0) == 0x6f0)
 629                         strcat(cpu_model, "Nano Processor");
 630                 else
 631                         strcat(cpu_model, "Unknown");
 632 #endif
 633                 break;
 634 #ifdef __i386__
 635         case CPU_VENDOR_IBM:
 636                 strcpy(cpu_model, "Blue Lightning CPU");
 637                 break;
 638         case CPU_VENDOR_NSC:
 639                 switch (cpu_id & 0xff0) {
 640                 case 0x540:
 641                         strcpy(cpu_model, "Geode SC1100");
 642                         cpu = CPU_GEODE1100;
 643                         break;
 644                 default:
 645                         strcpy(cpu_model, "Geode/NSC unknown");
 646                         break;
 647                 }
 648                 break;
 649 #endif
 650         default:
 651                 strcat(cpu_model, "Unknown");
 652                 break;
 653         }
 654
 655         /*
 656          * Replace cpu_model with cpu_brand minus leading spaces if
 657          * we have one.
 658          */
 659         brand = cpu_brand;
 660         while (*brand == ' ')
 661                 ++brand;
 662         if (*brand != '\0')
 663                 strcpy(cpu_model, brand);
 664
 665         printf("%s (", cpu_model);
 666         if (tsc_freq != 0) {
 667                 hw_clockrate = (tsc_freq + 5000) / 1000000;
 668                 printf("%jd.%02d-MHz ",
 669                     (intmax_t)(tsc_freq + 4999) / 1000000,
 670                     (u_int)((tsc_freq + 4999) / 10000) % 100);
 671         }
 672         switch(cpu_class) {
 673 #ifdef __i386__
 674         case CPUCLASS_286:
 675                 printf("286");
 676                 break;
 677         case CPUCLASS_386:
 678                 printf("386");
 679                 break;
 680 #if defined(I486_CPU)
 681         case CPUCLASS_486:
 682                 printf("486");
 683                 break;
 684 #endif
 685 #if defined(I586_CPU)
 686         case CPUCLASS_586:
 687                 printf("586");
 688                 break;
 689 #endif
 690 #if defined(I686_CPU)
 691         case CPUCLASS_686:
 692                 printf("686");
 693                 break;
 694 #endif
 695 #else
 696         case CPUCLASS_K8:
 697                 printf("K8");
 698                 break;
 699 #endif
 700         default:
 701                 printf("Unknown");      /* will panic below... */
 702         }
 703         printf("-class CPU)\n");
 704         if (*cpu_vendor)
 705                 printf("  Origin=\"%s\"", cpu_vendor);
 706         if (cpu_id)
 707                 printf("  Id=0x%x", cpu_id);
 708
 709         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 710             cpu_vendor_id == CPU_VENDOR_AMD ||
 711             cpu_vendor_id == CPU_VENDOR_CENTAUR ||
 712 #ifdef __i386__
 713             cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
 714             cpu_vendor_id == CPU_VENDOR_RISE ||
 715             cpu_vendor_id == CPU_VENDOR_NSC ||
 716             (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
 717 #endif
 718             0) {
 719                 printf("  Family=0x%x", CPUID_TO_FAMILY(cpu_id));
 720                 printf("  Model=0x%x", CPUID_TO_MODEL(cpu_id));
 721                 printf("  Stepping=%u", cpu_id & CPUID_STEPPING);
 722 #ifdef __i386__
 723                 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
 724                         printf("\n  DIR=0x%04x", cyrix_did);
 725 #endif
 726
 727                 /*
 728                  * AMD CPUID Specification
 729                  * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
 730                  *
 731                  * Intel Processor Identification and CPUID Instruction
 732                  * http://www.intel.com/assets/pdf/appnote/241618.pdf
 733                  */
 734                 if (cpu_high > 0) {
 735
 736                         /*
 737                          * Here we should probably set up flags indicating
 738                          * whether or not various features are available.
 739                          * The interesting ones are probably VME, PSE, PAE,
 740                          * and PGE.  The code already assumes without bothering
 741                          * to check that all CPUs >= Pentium have a TSC and
 742                          * MSRs.
 743                          */
 744                         printf("\n  Features=0x%b", cpu_feature,
 745                         "\020"
 746                         "\001FPU"       /* Integral FPU */
 747                         "\002VME"       /* Extended VM86 mode support */
 748                         "\003DE"        /* Debugging Extensions (CR4.DE) */
 749                         "\004PSE"       /* 4MByte page tables */
 750                         "\005TSC"       /* Timestamp counter */
 751                         "\006MSR"       /* Machine specific registers */
 752                         "\007PAE"       /* Physical address extension */
 753                         "\010MCE"       /* Machine Check support */
 754                         "\011CX8"       /* CMPEXCH8 instruction */
 755                         "\012APIC"      /* SMP local APIC */
 756                         "\013oldMTRR"   /* Previous implementation of MTRR */
 757                         "\014SEP"       /* Fast System Call */
 758                         "\015MTRR"      /* Memory Type Range Registers */
 759                         "\016PGE"       /* PG_G (global bit) support */
 760                         "\017MCA"       /* Machine Check Architecture */
 761                         "\020CMOV"      /* CMOV instruction */
 762                         "\021PAT"       /* Page attributes table */
 763                         "\022PSE36"     /* 36 bit address space support */
 764                         "\023PN"        /* Processor Serial number */
 765                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
 766                         "\025<b20>"
 767                         "\026DTS"       /* Debug Trace Store */
 768                         "\027ACPI"      /* ACPI support */
 769                         "\030MMX"       /* MMX instructions */
 770                         "\031FXSR"      /* FXSAVE/FXRSTOR */
 771                         "\032SSE"       /* Streaming SIMD Extensions */
 772                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
 773                         "\034SS"        /* Self snoop */
 774                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
 775                         "\036TM"        /* Thermal Monitor clock slowdown */
 776                         "\037IA64"      /* CPU can execute IA64 instructions */
 777                         "\040PBE"       /* Pending Break Enable */
 778                         );
 779
 780                         if (cpu_feature2 != 0) {
 781                                 printf("\n  Features2=0x%b", cpu_feature2,
 782                                 "\020"
 783                                 "\001SSE3"      /* SSE3 */
 784                                 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
 785                                 "\003DTES64"    /* 64-bit Debug Trace */
 786                                 "\004MON"       /* MONITOR/MWAIT Instructions */
 787                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
 788                                 "\006VMX"       /* Virtual Machine Extensions */
 789                                 "\007SMX"       /* Safer Mode Extensions */
 790                                 "\010EST"       /* Enhanced SpeedStep */
 791                                 "\011TM2"       /* Thermal Monitor 2 */
 792                                 "\012SSSE3"     /* SSSE3 */
 793                                 "\013CNXT-ID"   /* L1 context ID available */
 794                                 "\014<b11>"
 795                                 "\015FMA"       /* Fused Multiply Add */
 796                                 "\016CX16"      /* CMPXCHG16B Instruction */
 797                                 "\017xTPR"      /* Send Task Priority Messages*/
 798                                 "\020PDCM"      /* Perf/Debug Capability MSR */
 799                                 "\021<b16>"
 800                                 "\022PCID"      /* Process-context Identifiers*/
 801                                 "\023DCA"       /* Direct Cache Access */
 802                                 "\024SSE4.1"    /* SSE 4.1 */
 803                                 "\025SSE4.2"    /* SSE 4.2 */
 804                                 "\026x2APIC"    /* xAPIC Extensions */
 805                                 "\027MOVBE"     /* MOVBE Instruction */
 806                                 "\030POPCNT"    /* POPCNT Instruction */
 807                                 "\031TSCDLT"    /* TSC-Deadline Timer */
 808                                 "\032AESNI"     /* AES Crypto */
 809                                 "\033XSAVE"     /* XSAVE/XRSTOR States */
 810                                 "\034OSXSAVE"   /* OS-Enabled State Management*/
 811                                 "\035AVX"       /* Advanced Vector Extensions */
 812                                 "\036F16C"      /* Half-precision conversions */
 813                                 "\037RDRAND"    /* RDRAND Instruction */
 814                                 "\040HV"        /* Hypervisor */
 815                                 );
 816                         }
 817
 818                         if (amd_feature != 0) {
 819                                 printf("\n  AMD Features=0x%b", amd_feature,
 820                                 "\020"          /* in hex */
 821                                 "\001<s0>"      /* Same */
 822                                 "\002<s1>"      /* Same */
 823                                 "\003<s2>"      /* Same */
 824                                 "\004<s3>"      /* Same */
 825                                 "\005<s4>"      /* Same */
 826                                 "\006<s5>"      /* Same */
 827                                 "\007<s6>"      /* Same */
 828                                 "\010<s7>"      /* Same */
 829                                 "\011<s8>"      /* Same */
 830                                 "\012<s9>"      /* Same */
 831                                 "\013<b10>"     /* Undefined */
 832                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
 833                                 "\015<s12>"     /* Same */
 834                                 "\016<s13>"     /* Same */
 835                                 "\017<s14>"     /* Same */
 836                                 "\020<s15>"     /* Same */
 837                                 "\021<s16>"     /* Same */
 838                                 "\022<s17>"     /* Same */
 839                                 "\023<b18>"     /* Reserved, unknown */
 840                                 "\024MP"        /* Multiprocessor Capable */
 841                                 "\025NX"        /* Has EFER.NXE, NX */
 842                                 "\026<b21>"     /* Undefined */
 843                                 "\027MMX+"      /* AMD MMX Extensions */
 844                                 "\030<s23>"     /* Same */
 845                                 "\031<s24>"     /* Same */
 846                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
 847                                 "\033Page1GB"   /* 1-GB large page support */
 848                                 "\034RDTSCP"    /* RDTSCP */
 849                                 "\035<b28>"     /* Undefined */
 850                                 "\036LM"        /* 64 bit long mode */
 851                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
 852                                 "\0403DNow!"    /* AMD 3DNow! */
 853                                 );
 854                         }
 855
 856                         if (amd_feature2 != 0) {
 857                                 printf("\n  AMD Features2=0x%b", amd_feature2,
 858                                 "\020"
 859                                 "\001LAHF"      /* LAHF/SAHF in long mode */
 860                                 "\002CMP"       /* CMP legacy */
 861                                 "\003SVM"       /* Secure Virtual Mode */
 862                                 "\004ExtAPIC"   /* Extended APIC register */
 863                                 "\005CR8"       /* CR8 in legacy mode */
 864                                 "\006ABM"       /* LZCNT instruction */
 865                                 "\007SSE4A"     /* SSE4A */
 866                                 "\010MAS"       /* Misaligned SSE mode */
 867                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
 868                                 "\012OSVW"      /* OS visible workaround */
 869                                 "\013IBS"       /* Instruction based sampling */
 870                                 "\014XOP"       /* XOP extended instructions */
 871                                 "\015SKINIT"    /* SKINIT/STGI */
 872                                 "\016WDT"       /* Watchdog timer */
 873                                 "\017<b14>"
 874                                 "\020LWP"       /* Lightweight Profiling */
 875                                 "\021FMA4"      /* 4-operand FMA instructions */
 876                                 "\022TCE"       /* Translation Cache Extension */
 877                                 "\023<b18>"
 878                                 "\024NodeId"    /* NodeId MSR support */
 879                                 "\025<b20>"
 880                                 "\026TBM"       /* Trailing Bit Manipulation */
 881                                 "\027Topology"  /* Topology Extensions */
 882                                 "\030PCXC"      /* Core perf count */
 883                                 "\031PNXC"      /* NB perf count */
 884                                 "\032<b25>"
 885                                 "\033DBE"       /* Data Breakpoint extension */
 886                                 "\034PTSC"      /* Performance TSC */
 887                                 "\035PL2I"      /* L2I perf count */
 888                                 "\036<b29>"
 889                                 "\037<b30>"
 890                                 "\040<b31>"
 891                                 );
 892                         }
 893
 894                         if (cpu_stdext_feature != 0) {
 895                                 printf("\n  Structured Extended Features=0x%b",
 896                                     cpu_stdext_feature,
 897                                        "\020"
 898                                        /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
 899                                        "\001FSGSBASE"
 900                                        "\002TSCADJ"
 901                                        /* Bit Manipulation Instructions */
 902                                        "\004BMI1"
 903                                        /* Hardware Lock Elision */
 904                                        "\005HLE"
 905                                        /* Advanced Vector Instructions 2 */
 906                                        "\006AVX2"
 907                                        /* Supervisor Mode Execution Prot. */
 908                                        "\010SMEP"
 909                                        /* Bit Manipulation Instructions */
 910                                        "\011BMI2"
 911                                        "\012ERMS"
 912                                        /* Invalidate Processor Context ID */
 913                                        "\013INVPCID"
 914                                        /* Restricted Transactional Memory */
 915                                        "\014RTM"
 916                                        /* Intel Memory Protection Extensions */
 917                                        "\017MPX"
 918                                        /* AVX512 Foundation */
 919                                        "\021AVX512F"
 920                                        /* Enhanced NRBG */
 921                                        "\023RDSEED"
 922                                        /* ADCX + ADOX */
 923                                        "\024ADX"
 924                                        /* Supervisor Mode Access Prevention */
 925                                        "\025SMAP"
 926                                        "\030CLFLUSHOPT"
 927                                        "\032PROCTRACE"
 928                                        "\033AVX512PF"
 929                                        "\034AVX512ER"
 930                                        "\035AVX512CD"
 931                                        "\036SHA"
 932                                        );
 933                         }
 934
 935                         if (via_feature_rng != 0 || via_feature_xcrypt != 0)
 936                                 print_via_padlock_info();
 937
 938                         if (cpu_feature2 & CPUID2_VMX)
 939                                 print_vmx_info();
 940
 941                         if ((cpu_feature & CPUID_HTT) &&
 942                             cpu_vendor_id == CPU_VENDOR_AMD)
 943                                 cpu_feature &= ~CPUID_HTT;
 944
 945                         /*
 946                          * If this CPU supports P-state invariant TSC then
 947                          * mention the capability.
 948                          */
 949                         if (tsc_is_invariant) {
 950                                 printf("\n  TSC: P-state invariant");
 951                                 if (tsc_perf_stat)
 952                                         printf(", performance statistics");
 953                         }
 954
 955                 }
 956 #ifdef __i386__
 957         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
 958                 printf("  DIR=0x%04x", cyrix_did);
 959                 printf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
 960                 printf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
 961 #ifndef CYRIX_CACHE_REALLY_WORKS
 962                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
 963                         printf("\n  CPU cache: write-through mode");
 964 #endif
 965 #endif
 966         }
 967
 968         /* Avoid ugly blank lines: only print newline when we have to. */
 969         if (*cpu_vendor || cpu_id)
 970                 printf("\n");
 971
 972         if (!bootverbose)
 973                 return;
 974
 975         if (cpu_vendor_id == CPU_VENDOR_AMD)
 976                 print_AMD_info();
 977         else if (cpu_vendor_id == CPU_VENDOR_INTEL)
 978                 print_INTEL_info();
 979 #ifdef __i386__
 980         else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
 981                 print_transmeta_info();
 982 #endif
 983 }
 984
 985 void
 986 panicifcpuunsupported(void)
 987 {
 988
 989 #ifdef __i386__
 990 #if !defined(lint)
 991 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
 992 #error This kernel is not configured for one of the supported CPUs
 993 #endif
 994 #else /* lint */
 995 #endif /* lint */
 996 #else /* __amd64__ */
 997 #ifndef HAMMER
 998 #error "You need to specify a cpu type"
 999 #endif
1000 #endif
1001         /*
1002          * Now that we have told the user what they have,
1003          * let them know if that machine type isn't configured.
1004          */
1005         switch (cpu_class) {
1006 #ifdef __i386__
1007         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
1008         case CPUCLASS_386:
1009 #if !defined(I486_CPU)
1010         case CPUCLASS_486:
1011 #endif
1012 #if !defined(I586_CPU)
1013         case CPUCLASS_586:
1014 #endif
1015 #if !defined(I686_CPU)
1016         case CPUCLASS_686:
1017 #endif
1018 #else /* __amd64__ */
1019         case CPUCLASS_X86:
1020 #ifndef HAMMER
1021         case CPUCLASS_K8:
1022 #endif
1023 #endif
1024                 panic("CPU class not configured");
1025         default:
1026                 break;
1027         }
1028 }
1029
1030 #ifdef __i386__
1031 static  volatile u_int trap_by_rdmsr;
1032
1033 /*
1034  * Special exception 6 handler.
1035  * The rdmsr instruction generates invalid opcodes fault on 486-class
1036  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
1037  * function identblue() when this handler is called.  Stacked eip should
1038  * be advanced.
1039  */
1040 inthand_t       bluetrap6;
1041 #ifdef __GNUCLIKE_ASM
1042 __asm
1043 ("                                                                      \n\
1044         .text                                                           \n\
1045         .p2align 2,0x90                                                 \n\
1046         .type   " __XSTRING(CNAME(bluetrap6)) ",@function               \n\
1047 " __XSTRING(CNAME(bluetrap6)) ":                                        \n\
1048         ss                                                              \n\
1049         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1050         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1051         iret                                                            \n\
1052 ");
1053 #endif
1054
1055 /*
1056  * Special exception 13 handler.
1057  * Accessing non-existent MSR generates general protection fault.
1058  */
1059 inthand_t       bluetrap13;
1060 #ifdef __GNUCLIKE_ASM
1061 __asm
1062 ("                                                                      \n\
1063         .text                                                           \n\
1064         .p2align 2,0x90                                                 \n\
1065         .type   " __XSTRING(CNAME(bluetrap13)) ",@function              \n\
1066 " __XSTRING(CNAME(bluetrap13)) ":                                       \n\
1067         ss                                                              \n\
1068         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1069         popl    %eax            /* discard error code */                \n\
1070         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1071         iret                                                            \n\
1072 ");
1073 #endif
1074
1075 /*
1076  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1077  * support cpuid instruction.  This function should be called after
1078  * loading interrupt descriptor table register.
1079  *
1080  * I don't like this method that handles fault, but I couldn't get
1081  * information for any other methods.  Does blue giant know?
1082  */
1083 static int
1084 identblue(void)
1085 {
1086
1087         trap_by_rdmsr = 0;
1088
1089         /*
1090          * Cyrix 486-class CPU does not support rdmsr instruction.
1091          * The rdmsr instruction generates invalid opcode fault, and exception
1092          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
1093          * bluetrap6() set the magic number to trap_by_rdmsr.
1094          */
1095         setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1096             GSEL(GCODE_SEL, SEL_KPL));
1097
1098         /*
1099          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1100          * In this case, rdmsr generates general protection fault, and
1101          * exception will be trapped by bluetrap13().
1102          */
1103         setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1104             GSEL(GCODE_SEL, SEL_KPL));
1105
1106         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
1107
1108         if (trap_by_rdmsr == 0xa8c1d)
1109                 return IDENTBLUE_CYRIX486;
1110         else if (trap_by_rdmsr == 0xa89c4)
1111                 return IDENTBLUE_CYRIXM2;
1112         return IDENTBLUE_IBMCPU;
1113 }
1114
1115
1116 /*
1117  * identifycyrix() set lower 16 bits of cyrix_did as follows:
1118  *
1119  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
1120  * +-------+-------+---------------+
1121  * |  SID  |  RID  |   Device ID   |
1122  * |    (DIR 1)    |    (DIR 0)    |
1123  * +-------+-------+---------------+
1124  */
1125 static void
1126 identifycyrix(void)
1127 {
1128         register_t saveintr;
1129         int     ccr2_test = 0, dir_test = 0;
1130         u_char  ccr2, ccr3;
1131
1132         saveintr = intr_disable();
1133
1134         ccr2 = read_cyrix_reg(CCR2);
1135         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1136         read_cyrix_reg(CCR2);
1137         if (read_cyrix_reg(CCR2) != ccr2)
1138                 ccr2_test = 1;
1139         write_cyrix_reg(CCR2, ccr2);
1140
1141         ccr3 = read_cyrix_reg(CCR3);
1142         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1143         read_cyrix_reg(CCR3);
1144         if (read_cyrix_reg(CCR3) != ccr3)
1145                 dir_test = 1;                                   /* CPU supports DIRs. */
1146         write_cyrix_reg(CCR3, ccr3);
1147
1148         if (dir_test) {
1149                 /* Device ID registers are available. */
1150                 cyrix_did = read_cyrix_reg(DIR1) << 8;
1151                 cyrix_did += read_cyrix_reg(DIR0);
1152         } else if (ccr2_test)
1153                 cyrix_did = 0x0010;             /* 486S A-step */
1154         else
1155                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
1156
1157         intr_restore(saveintr);
1158 }
1159 #endif
1160
1161 /* Update TSC freq with the value indicated by the caller. */
1162 static void
1163 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1164 {
1165
1166         /* If there was an error during the transition, don't do anything. */
1167         if (status != 0)
1168                 return;
1169
1170         /* Total setting for this level gives the new frequency in MHz. */
1171         hw_clockrate = level->total_set.freq;
1172 }
1173
1174 static void
1175 hook_tsc_freq(void *arg __unused)
1176 {
1177
1178         if (tsc_is_invariant)
1179                 return;
1180
1181         tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1182             tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1183 }
1184
1185 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1186
1187 /*
1188  * Final stage of CPU identification.
1189  */
1190 #ifdef __i386__
1191 void
1192 finishidentcpu(void)
1193 #else
1194 void
1195 identify_cpu(void)
1196 #endif
1197 {
1198         u_int regs[4], cpu_stdext_disable;
1199 #ifdef __i386__
1200         u_char ccr3;
1201 #endif
1202
1203 #ifdef __amd64__
1204         do_cpuid(0, regs);
1205         cpu_high = regs[0];
1206         ((u_int *)&cpu_vendor)[0] = regs[1];
1207         ((u_int *)&cpu_vendor)[1] = regs[3];
1208         ((u_int *)&cpu_vendor)[2] = regs[2];
1209         cpu_vendor[12] = '\0';
1210
1211         do_cpuid(1, regs);
1212         cpu_id = regs[0];
1213         cpu_procinfo = regs[1];
1214         cpu_feature = regs[3];
1215         cpu_feature2 = regs[2];
1216 #endif
1217
1218         cpu_vendor_id = find_cpu_vendor_id();
1219
1220         /*
1221          * Clear "Limit CPUID Maxval" bit and get the largest standard CPUID
1222          * function number again if it is set from BIOS.  It is necessary
1223          * for probing correct CPU topology later.
1224          * XXX This is only done on the BSP package.
1225          */
1226         if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high > 0 && cpu_high < 4 &&
1227             ((CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1228             (CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1229                 uint64_t msr;
1230                 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1231                 if ((msr & 0x400000ULL) != 0) {
1232                         wrmsr(MSR_IA32_MISC_ENABLE, msr & ~0x400000ULL);
1233                         do_cpuid(0, regs);
1234                         cpu_high = regs[0];
1235                 }
1236         }
1237
1238         if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1239                 do_cpuid(5, regs);
1240                 cpu_mon_mwait_flags = regs[2];
1241                 cpu_mon_min_size = regs[0] &  CPUID5_MON_MIN_SIZE;
1242                 cpu_mon_max_size = regs[1] &  CPUID5_MON_MAX_SIZE;
1243         }
1244
1245         if (cpu_high >= 7) {
1246                 cpuid_count(7, 0, regs);
1247                 cpu_stdext_feature = regs[1];
1248
1249                 /*
1250                  * Some hypervisors fail to filter out unsupported
1251                  * extended features.  For now, disable the
1252                  * extensions, activation of which requires setting a
1253                  * bit in CR4, and which VM monitors do not support.
1254                  */
1255                 if (cpu_feature2 & CPUID2_HV) {
1256                         cpu_stdext_disable = CPUID_STDEXT_FSGSBASE |
1257                             CPUID_STDEXT_SMEP;
1258                 } else
1259                         cpu_stdext_disable = 0;
1260                 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1261                 cpu_stdext_feature &= ~cpu_stdext_disable;
1262         }
1263
1264 #ifdef __i386__
1265         if (cpu_high > 0 &&
1266             (cpu_vendor_id == CPU_VENDOR_INTEL ||
1267              cpu_vendor_id == CPU_VENDOR_AMD ||
1268              cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1269              cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1270              cpu_vendor_id == CPU_VENDOR_NSC)) {
1271                 do_cpuid(0x80000000, regs);
1272                 if (regs[0] >= 0x80000000)
1273                         cpu_exthigh = regs[0];
1274         }
1275 #else
1276         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1277             cpu_vendor_id == CPU_VENDOR_AMD ||
1278             cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1279                 do_cpuid(0x80000000, regs);
1280                 cpu_exthigh = regs[0];
1281         }
1282 #endif
1283         if (cpu_exthigh >= 0x80000001) {
1284                 do_cpuid(0x80000001, regs);
1285                 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1286                 amd_feature2 = regs[2];
1287         }
1288         if (cpu_exthigh >= 0x80000007) {
1289                 do_cpuid(0x80000007, regs);
1290                 amd_pminfo = regs[3];
1291         }
1292         if (cpu_exthigh >= 0x80000008) {
1293                 do_cpuid(0x80000008, regs);
1294                 cpu_procinfo2 = regs[2];
1295         }
1296
1297 #ifdef __i386__
1298         if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1299                 if (cpu == CPU_486) {
1300                         /*
1301                          * These conditions are equivalent to:
1302                          *     - CPU does not support cpuid instruction.
1303                          *     - Cyrix/IBM CPU is detected.
1304                          */
1305                         if (identblue() == IDENTBLUE_IBMCPU) {
1306                                 strcpy(cpu_vendor, "IBM");
1307                                 cpu_vendor_id = CPU_VENDOR_IBM;
1308                                 cpu = CPU_BLUE;
1309                                 return;
1310                         }
1311                 }
1312                 switch (cpu_id & 0xf00) {
1313                 case 0x600:
1314                         /*
1315                          * Cyrix's datasheet does not describe DIRs.
1316                          * Therefor, I assume it does not have them
1317                          * and use the result of the cpuid instruction.
1318                          * XXX they seem to have it for now at least. -Peter
1319                          */
1320                         identifycyrix();
1321                         cpu = CPU_M2;
1322                         break;
1323                 default:
1324                         identifycyrix();
1325                         /*
1326                          * This routine contains a trick.
1327                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1328                          */
1329                         switch (cyrix_did & 0x00f0) {
1330                         case 0x00:
1331                         case 0xf0:
1332                                 cpu = CPU_486DLC;
1333                                 break;
1334                         case 0x10:
1335                                 cpu = CPU_CY486DX;
1336                                 break;
1337                         case 0x20:
1338                                 if ((cyrix_did & 0x000f) < 8)
1339                                         cpu = CPU_M1;
1340                                 else
1341                                         cpu = CPU_M1SC;
1342                                 break;
1343                         case 0x30:
1344                                 cpu = CPU_M1;
1345                                 break;
1346                         case 0x40:
1347                                 /* MediaGX CPU */
1348                                 cpu = CPU_M1SC;
1349                                 break;
1350                         default:
1351                                 /* M2 and later CPUs are treated as M2. */
1352                                 cpu = CPU_M2;
1353
1354                                 /*
1355                                  * enable cpuid instruction.
1356                                  */
1357                                 ccr3 = read_cyrix_reg(CCR3);
1358                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1359                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1360                                 write_cyrix_reg(CCR3, ccr3);
1361
1362                                 do_cpuid(0, regs);
1363                                 cpu_high = regs[0];     /* eax */
1364                                 do_cpuid(1, regs);
1365                                 cpu_id = regs[0];       /* eax */
1366                                 cpu_feature = regs[3];  /* edx */
1367                                 break;
1368                         }
1369                 }
1370         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1371                 /*
1372                  * There are BlueLightning CPUs that do not change
1373                  * undefined flags by dividing 5 by 2.  In this case,
1374                  * the CPU identification routine in locore.s leaves
1375                  * cpu_vendor null string and puts CPU_486 into the
1376                  * cpu.
1377                  */
1378                 if (identblue() == IDENTBLUE_IBMCPU) {
1379                         strcpy(cpu_vendor, "IBM");
1380                         cpu_vendor_id = CPU_VENDOR_IBM;
1381                         cpu = CPU_BLUE;
1382                         return;
1383                 }
1384         }
1385 #else
1386         /* XXX */
1387         cpu = CPU_CLAWHAMMER;
1388 #endif
1389 }
1390
1391 static u_int
1392 find_cpu_vendor_id(void)
1393 {
1394         int     i;
1395
1396         for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++)
1397                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1398                         return (cpu_vendors[i].vendor_id);
1399         return (0);
1400 }
1401
1402 static void
1403 print_AMD_assoc(int i)
1404 {
1405         if (i == 255)
1406                 printf(", fully associative\n");
1407         else
1408                 printf(", %d-way associative\n", i);
1409 }
1410
1411 static void
1412 print_AMD_l2_assoc(int i)
1413 {
1414         switch (i & 0x0f) {
1415         case 0: printf(", disabled/not present\n"); break;
1416         case 1: printf(", direct mapped\n"); break;
1417         case 2: printf(", 2-way associative\n"); break;
1418         case 4: printf(", 4-way associative\n"); break;
1419         case 6: printf(", 8-way associative\n"); break;
1420         case 8: printf(", 16-way associative\n"); break;
1421         case 15: printf(", fully associative\n"); break;
1422         default: printf(", reserved configuration\n"); break;
1423         }
1424 }
1425
1426 static void
1427 print_AMD_info(void)
1428 {
1429 #ifdef __i386__
1430         uint64_t amd_whcr;
1431 #endif
1432         u_int regs[4];
1433
1434         if (cpu_exthigh >= 0x80000005) {
1435                 do_cpuid(0x80000005, regs);
1436                 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1437                 print_AMD_assoc(regs[0] >> 24);
1438
1439                 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1440                 print_AMD_assoc((regs[0] >> 8) & 0xff);
1441
1442                 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1443                 print_AMD_assoc(regs[1] >> 24);
1444
1445                 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1446                 print_AMD_assoc((regs[1] >> 8) & 0xff);
1447
1448                 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1449                 printf(", %d bytes/line", regs[2] & 0xff);
1450                 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1451                 print_AMD_assoc((regs[2] >> 16) & 0xff);
1452
1453                 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1454                 printf(", %d bytes/line", regs[3] & 0xff);
1455                 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1456                 print_AMD_assoc((regs[3] >> 16) & 0xff);
1457         }
1458
1459         if (cpu_exthigh >= 0x80000006) {
1460                 do_cpuid(0x80000006, regs);
1461                 if ((regs[0] >> 16) != 0) {
1462                         printf("L2 2MB data TLB: %d entries",
1463                             (regs[0] >> 16) & 0xfff);
1464                         print_AMD_l2_assoc(regs[0] >> 28);
1465                         printf("L2 2MB instruction TLB: %d entries",
1466                             regs[0] & 0xfff);
1467                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1468                 } else {
1469                         printf("L2 2MB unified TLB: %d entries",
1470                             regs[0] & 0xfff);
1471                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1472                 }
1473                 if ((regs[1] >> 16) != 0) {
1474                         printf("L2 4KB data TLB: %d entries",
1475                             (regs[1] >> 16) & 0xfff);
1476                         print_AMD_l2_assoc(regs[1] >> 28);
1477
1478                         printf("L2 4KB instruction TLB: %d entries",
1479                             (regs[1] >> 16) & 0xfff);
1480                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1481                 } else {
1482                         printf("L2 4KB unified TLB: %d entries",
1483                             (regs[1] >> 16) & 0xfff);
1484                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1485                 }
1486                 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1487                 printf(", %d bytes/line", regs[2] & 0xff);
1488                 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1489                 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1490         }
1491
1492 #ifdef __i386__
1493         if (((cpu_id & 0xf00) == 0x500)
1494             && (((cpu_id & 0x0f0) > 0x80)
1495                 || (((cpu_id & 0x0f0) == 0x80)
1496                     && (cpu_id & 0x00f) > 0x07))) {
1497                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1498                 amd_whcr = rdmsr(0xc0000082);
1499                 if (!(amd_whcr & (0x3ff << 22))) {
1500                         printf("Write Allocate Disable\n");
1501                 } else {
1502                         printf("Write Allocate Enable Limit: %dM bytes\n",
1503                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1504                         printf("Write Allocate 15-16M bytes: %s\n",
1505                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1506                 }
1507         } else if (((cpu_id & 0xf00) == 0x500)
1508                    && ((cpu_id & 0x0f0) > 0x50)) {
1509                 /* K6, K6-2(old core) */
1510                 amd_whcr = rdmsr(0xc0000082);
1511                 if (!(amd_whcr & (0x7f << 1))) {
1512                         printf("Write Allocate Disable\n");
1513                 } else {
1514                         printf("Write Allocate Enable Limit: %dM bytes\n",
1515                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1516                         printf("Write Allocate 15-16M bytes: %s\n",
1517                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
1518                         printf("Hardware Write Allocate Control: %s\n",
1519                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
1520                 }
1521         }
1522 #endif
1523         /*
1524          * Opteron Rev E shows a bug as in very rare occasions a read memory
1525          * barrier is not performed as expected if it is followed by a
1526          * non-atomic read-modify-write instruction.
1527          * As long as that bug pops up very rarely (intensive machine usage
1528          * on other operating systems generally generates one unexplainable
1529          * crash any 2 months) and as long as a model specific fix would be
1530          * impratical at this stage, print out a warning string if the broken
1531          * model and family are identified.
1532          */
1533         if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1534             CPUID_TO_MODEL(cpu_id) <= 0x3f)
1535                 printf("WARNING: This architecture revision has known SMP "
1536                     "hardware bugs which may cause random instability\n");
1537 }
1538
1539 static void
1540 print_INTEL_info(void)
1541 {
1542         u_int regs[4];
1543         u_int rounds, regnum;
1544         u_int nwaycode, nway;
1545
1546         if (cpu_high >= 2) {
1547                 rounds = 0;
1548                 do {
1549                         do_cpuid(0x2, regs);
1550                         if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1551                                 break;  /* we have a buggy CPU */
1552
1553                         for (regnum = 0; regnum <= 3; ++regnum) {
1554                                 if (regs[regnum] & (1<<31))
1555                                         continue;
1556                                 if (regnum != 0)
1557                                         print_INTEL_TLB(regs[regnum] & 0xff);
1558                                 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1559                                 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1560                                 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1561                         }
1562                 } while (--rounds > 0);
1563         }
1564
1565         if (cpu_exthigh >= 0x80000006) {
1566                 do_cpuid(0x80000006, regs);
1567                 nwaycode = (regs[2] >> 12) & 0x0f;
1568                 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1569                         nway = 1 << (nwaycode / 2);
1570                 else
1571                         nway = 0;
1572                 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1573                     (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1574         }
1575 }
1576
1577 static void
1578 print_INTEL_TLB(u_int data)
1579 {
1580         switch (data) {
1581         case 0x0:
1582         case 0x40:
1583         default:
1584                 break;
1585         case 0x1:
1586                 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1587                 break;
1588         case 0x2:
1589                 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1590                 break;
1591         case 0x3:
1592                 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1593                 break;
1594         case 0x4:
1595                 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1596                 break;
1597         case 0x6:
1598                 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1599                 break;
1600         case 0x8:
1601                 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
1602                 break;
1603         case 0xa:
1604                 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
1605                 break;
1606         case 0xc:
1607                 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
1608                 break;
1609         case 0x22:
1610                 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1611                 break;
1612         case 0x23:
1613                 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1614                 break;
1615         case 0x25:
1616                 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1617                 break;
1618         case 0x29:
1619                 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1620                 break;
1621         case 0x2c:
1622                 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
1623                 break;
1624         case 0x30:
1625                 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
1626                 break;
1627         case 0x39:
1628                 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1629                 break;
1630         case 0x3b:
1631                 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
1632                 break;
1633         case 0x3c:
1634                 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1635                 break;
1636         case 0x41:
1637                 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
1638                 break;
1639         case 0x42:
1640                 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
1641                 break;
1642         case 0x43:
1643                 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
1644                 break;
1645         case 0x44:
1646                 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
1647                 break;
1648         case 0x45:
1649                 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
1650                 break;
1651         case 0x46:
1652                 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
1653                 break;
1654         case 0x47:
1655                 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
1656                 break;
1657         case 0x50:
1658                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
1659                 break;
1660         case 0x51:
1661                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
1662                 break;
1663         case 0x52:
1664                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
1665                 break;
1666         case 0x5b:
1667                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
1668                 break;
1669         case 0x5c:
1670                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
1671                 break;
1672         case 0x5d:
1673                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
1674                 break;
1675         case 0x60:
1676                 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1677                 break;
1678         case 0x66:
1679                 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1680                 break;
1681         case 0x67:
1682                 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1683                 break;
1684         case 0x68:
1685                 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
1686                 break;
1687         case 0x70:
1688                 printf("Trace cache: 12K-uops, 8-way set associative\n");
1689                 break;
1690         case 0x71:
1691                 printf("Trace cache: 16K-uops, 8-way set associative\n");
1692                 break;
1693         case 0x72:
1694                 printf("Trace cache: 32K-uops, 8-way set associative\n");
1695                 break;
1696         case 0x78:
1697                 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
1698                 break;
1699         case 0x79:
1700                 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1701                 break;
1702         case 0x7a:
1703                 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1704                 break;
1705         case 0x7b:
1706                 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1707                 break;
1708         case 0x7c:
1709                 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1710                 break;
1711         case 0x7d:
1712                 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
1713                 break;
1714         case 0x7f:
1715                 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
1716                 break;
1717         case 0x82:
1718                 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
1719                 break;
1720         case 0x83:
1721                 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
1722                 break;
1723         case 0x84:
1724                 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
1725                 break;
1726         case 0x85:
1727                 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
1728                 break;
1729         case 0x86:
1730                 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
1731                 break;
1732         case 0x87:
1733                 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
1734                 break;
1735         case 0xb0:
1736                 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
1737                 break;
1738         case 0xb3:
1739                 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
1740                 break;
1741         }
1742 }
1743
1744 #ifdef __i386__
1745 static void
1746 print_transmeta_info(void)
1747 {
1748         u_int regs[4], nreg = 0;
1749
1750         do_cpuid(0x80860000, regs);
1751         nreg = regs[0];
1752         if (nreg >= 0x80860001) {
1753                 do_cpuid(0x80860001, regs);
1754                 printf("  Processor revision %u.%u.%u.%u\n",
1755                        (regs[1] >> 24) & 0xff,
1756                        (regs[1] >> 16) & 0xff,
1757                        (regs[1] >> 8) & 0xff,
1758                        regs[1] & 0xff);
1759         }
1760         if (nreg >= 0x80860002) {
1761                 do_cpuid(0x80860002, regs);
1762                 printf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
1763                        (regs[1] >> 24) & 0xff,
1764                        (regs[1] >> 16) & 0xff,
1765                        (regs[1] >> 8) & 0xff,
1766                        regs[1] & 0xff,
1767                        regs[2]);
1768         }
1769         if (nreg >= 0x80860006) {
1770                 char info[65];
1771                 do_cpuid(0x80860003, (u_int*) &info[0]);
1772                 do_cpuid(0x80860004, (u_int*) &info[16]);
1773                 do_cpuid(0x80860005, (u_int*) &info[32]);
1774                 do_cpuid(0x80860006, (u_int*) &info[48]);
1775                 info[64] = 0;
1776                 printf("  %s\n", info);
1777         }
1778 }
1779 #endif
1780
1781 static void
1782 print_via_padlock_info(void)
1783 {
1784         u_int regs[4];
1785
1786         do_cpuid(0xc0000001, regs);
1787         printf("\n  VIA Padlock Features=0x%b", regs[3],
1788         "\020"
1789         "\003RNG"               /* RNG */
1790         "\007AES"               /* ACE */
1791         "\011AES-CTR"           /* ACE2 */
1792         "\013SHA1,SHA256"       /* PHE */
1793         "\015RSA"               /* PMM */
1794         );
1795 }
1796
1797 static uint32_t
1798 vmx_settable(uint64_t basic, int msr, int true_msr)
1799 {
1800         uint64_t val;
1801
1802         if (basic & (1ULL << 55))
1803                 val = rdmsr(true_msr);
1804         else
1805                 val = rdmsr(msr);
1806
1807         /* Just report the controls that can be set to 1. */
1808         return (val >> 32);
1809 }
1810
1811 static void
1812 print_vmx_info(void)
1813 {
1814         uint64_t basic, msr;
1815         uint32_t entry, exit, mask, pin, proc, proc2;
1816         int comma;
1817
1818         printf("\n  VT-x: ");
1819         msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
1820         if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
1821                 printf("(disabled in BIOS) ");
1822         basic = rdmsr(MSR_VMX_BASIC);
1823         pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
1824             MSR_VMX_TRUE_PINBASED_CTLS);
1825         proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
1826             MSR_VMX_TRUE_PROCBASED_CTLS);
1827         if (proc & PROCBASED_SECONDARY_CONTROLS)
1828                 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
1829                     MSR_VMX_PROCBASED_CTLS2);
1830         else
1831                 proc2 = 0;
1832         exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
1833         entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
1834
1835         if (!bootverbose) {
1836                 comma = 0;
1837                 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
1838                     entry & VM_ENTRY_LOAD_PAT) {
1839                         printf("%sPAT", comma ? "," : "");
1840                         comma = 1;
1841                 }
1842                 if (proc & PROCBASED_HLT_EXITING) {
1843                         printf("%sHLT", comma ? "," : "");
1844                         comma = 1;
1845                 }
1846                 if (proc & PROCBASED_MTF) {
1847                         printf("%sMTF", comma ? "," : "");
1848                         comma = 1;
1849                 }
1850                 if (proc & PROCBASED_PAUSE_EXITING) {
1851                         printf("%sPAUSE", comma ? "," : "");
1852                         comma = 1;
1853                 }
1854                 if (proc2 & PROCBASED2_ENABLE_EPT) {
1855                         printf("%sEPT", comma ? "," : "");
1856                         comma = 1;
1857                 }
1858                 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
1859                         printf("%sUG", comma ? "," : "");
1860                         comma = 1;
1861                 }
1862                 if (proc2 & PROCBASED2_ENABLE_VPID) {
1863                         printf("%sVPID", comma ? "," : "");
1864                         comma = 1;
1865                 }
1866                 if (proc & PROCBASED_USE_TPR_SHADOW &&
1867                     proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
1868                     proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
1869                     proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
1870                     proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
1871                         printf("%sVID", comma ? "," : "");
1872                         comma = 1;
1873                         if (pin & PINBASED_POSTED_INTERRUPT)
1874                                 printf(",PostIntr");
1875                 }
1876                 return;
1877         }
1878
1879         mask = basic >> 32;
1880         printf("Basic Features=0x%b", mask,
1881         "\020"
1882         "\02132PA"              /* 32-bit physical addresses */
1883         "\022SMM"               /* SMM dual-monitor */
1884         "\027INS/OUTS"          /* VM-exit info for INS and OUTS */
1885         "\030TRUE"              /* TRUE_CTLS MSRs */
1886         );
1887         printf("\n        Pin-Based Controls=0x%b", pin,
1888         "\020"
1889         "\001ExtINT"            /* External-interrupt exiting */
1890         "\004NMI"               /* NMI exiting */
1891         "\006VNMI"              /* Virtual NMIs */
1892         "\007PreTmr"            /* Activate VMX-preemption timer */
1893         "\010PostIntr"          /* Process posted interrupts */
1894         );
1895         printf("\n        Primary Processor Controls=0x%b", proc,
1896         "\020"
1897         "\003INTWIN"            /* Interrupt-window exiting */
1898         "\004TSCOff"            /* Use TSC offsetting */
1899         "\010HLT"               /* HLT exiting */
1900         "\012INVLPG"            /* INVLPG exiting */
1901         "\013MWAIT"             /* MWAIT exiting */
1902         "\014RDPMC"             /* RDPMC exiting */
1903         "\015RDTSC"             /* RDTSC exiting */
1904         "\020CR3-LD"            /* CR3-load exiting */
1905         "\021CR3-ST"            /* CR3-store exiting */
1906         "\024CR8-LD"            /* CR8-load exiting */
1907         "\025CR8-ST"            /* CR8-store exiting */
1908         "\026TPR"               /* Use TPR shadow */
1909         "\027NMIWIN"            /* NMI-window exiting */
1910         "\030MOV-DR"            /* MOV-DR exiting */
1911         "\031IO"                /* Unconditional I/O exiting */
1912         "\032IOmap"             /* Use I/O bitmaps */
1913         "\034MTF"               /* Monitor trap flag */
1914         "\035MSRmap"            /* Use MSR bitmaps */
1915         "\036MONITOR"           /* MONITOR exiting */
1916         "\037PAUSE"             /* PAUSE exiting */
1917         );
1918         if (proc & PROCBASED_SECONDARY_CONTROLS)
1919                 printf("\n        Secondary Processor Controls=0x%b", proc2,
1920                 "\020"
1921                 "\001APIC"              /* Virtualize APIC accesses */
1922                 "\002EPT"               /* Enable EPT */
1923                 "\003DT"                /* Descriptor-table exiting */
1924                 "\004RDTSCP"            /* Enable RDTSCP */
1925                 "\005x2APIC"            /* Virtualize x2APIC mode */
1926                 "\006VPID"              /* Enable VPID */
1927                 "\007WBINVD"            /* WBINVD exiting */
1928                 "\010UG"                /* Unrestricted guest */
1929                 "\011APIC-reg"          /* APIC-register virtualization */
1930                 "\012VID"               /* Virtual-interrupt delivery */
1931                 "\013PAUSE-loop"        /* PAUSE-loop exiting */
1932                 "\014RDRAND"            /* RDRAND exiting */
1933                 "\015INVPCID"           /* Enable INVPCID */
1934                 "\016VMFUNC"            /* Enable VM functions */
1935                 "\017VMCS"              /* VMCS shadowing */
1936                 "\020EPT#VE"            /* EPT-violation #VE */
1937                 "\021XSAVES"            /* Enable XSAVES/XRSTORS */
1938                 );
1939         printf("\n        Exit Controls=0x%b", mask,
1940         "\020"
1941         "\003DR"                /* Save debug controls */
1942                                 /* Ignore Host address-space size */
1943         "\015PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
1944         "\020AckInt"            /* Acknowledge interrupt on exit */
1945         "\023PAT-SV"            /* Save MSR_PAT */
1946         "\024PAT-LD"            /* Load MSR_PAT */
1947         "\025EFER-SV"           /* Save MSR_EFER */
1948         "\026EFER-LD"           /* Load MSR_EFER */
1949         "\027PTMR-SV"           /* Save VMX-preemption timer value */
1950         );
1951         printf("\n        Entry Controls=0x%b", mask,
1952         "\020"
1953         "\003DR"                /* Save debug controls */
1954                                 /* Ignore IA-32e mode guest */
1955                                 /* Ignore Entry to SMM */
1956                                 /* Ignore Deactivate dual-monitor treatment */
1957         "\016PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
1958         "\017PAT"               /* Load MSR_PAT */
1959         "\020EFER"              /* Load MSR_EFER */
1960         );
1961         if (proc & PROCBASED_SECONDARY_CONTROLS &&
1962             (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
1963                 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
1964                 mask = msr;
1965                 printf("\n        EPT Features=0x%b", mask,
1966                 "\020"
1967                 "\001XO"                /* Execute-only translations */
1968                 "\007PW4"               /* Page-walk length of 4 */
1969                 "\011UC"                /* EPT paging-structure mem can be UC */
1970                 "\017WB"                /* EPT paging-structure mem can be WB */
1971                 "\0212M"                /* EPT PDE can map a 2-Mbyte page */
1972                 "\0221G"                /* EPT PDPTE can map a 1-Gbyte page */
1973                 "\025INVEPT"            /* INVEPT is supported */
1974                 "\026AD"                /* Accessed and dirty flags for EPT */
1975                 "\032single"            /* INVEPT single-context type */
1976                 "\033all"               /* INVEPT all-context type */
1977                 );
1978                 mask = msr >> 32;
1979                 printf("\n        VPID Features=0x%b", mask,
1980                 "\020"
1981                 "\001INVVPID"           /* INVVPID is supported */
1982                 "\011individual"        /* INVVPID individual-address type */
1983                 "\012single"            /* INVVPID single-context type */
1984                 "\013all"               /* INVVPID all-context type */
1985                  /* INVVPID single-context-retaining-globals type */
1986                 "\014single-globals"
1987                 );
1988         }
1989 }