sys/x86/x86/identcpu.c

   1 /*-
   2  * Copyright (c) 1992 Terrence R. Lambert.
   3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
   4  * Copyright (c) 1997 KATO Takenori.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * William Jolitz.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by the University of
  21  *      California, Berkeley and its contributors.
  22  * 4. Neither the name of the University nor the names of its contributors
  23  *    may be used to endorse or promote products derived from this software
  24  *    without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  36  * SUCH DAMAGE.
  37  *
  38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include "opt_cpu.h"
  45
  46 #include <sys/param.h>
  47 #include <sys/bus.h>
  48 #include <sys/cpu.h>
  49 #include <sys/eventhandler.h>
  50 #include <sys/limits.h>
  51 #include <sys/systm.h>
  52 #include <sys/kernel.h>
  53 #include <sys/sysctl.h>
  54 #include <sys/power.h>
  55
  56 #include <machine/asmacros.h>
  57 #include <machine/clock.h>
  58 #include <machine/cputypes.h>
  59 #include <machine/frame.h>
  60 #include <machine/intr_machdep.h>
  61 #include <machine/md_var.h>
  62 #include <machine/segments.h>
  63 #include <machine/specialreg.h>
  64
  65 #include <amd64/vmm/intel/vmx_controls.h>
  66 #include <x86/isa/icu.h>
  67 #include <x86/vmware.h>
  68
  69 #ifdef __i386__
  70 #define IDENTBLUE_CYRIX486      0
  71 #define IDENTBLUE_IBMCPU        1
  72 #define IDENTBLUE_CYRIXM2       2
  73
  74 static void identifycyrix(void);
  75 static void print_transmeta_info(void);
  76 #endif
  77 static u_int find_cpu_vendor_id(void);
  78 static void print_AMD_info(void);
  79 static void print_INTEL_info(void);
  80 static void print_INTEL_TLB(u_int data);
  81 static void print_hypervisor_info(void);
  82 static void print_svm_info(void);
  83 static void print_via_padlock_info(void);
  84 static void print_vmx_info(void);
  85
  86 int     cpu_class;
  87 char machine[] = MACHINE;
  88
  89 #ifdef __amd64__
  90 #ifdef SCTL_MASK32
  91 extern int adaptive_machine_arch;
  92 #endif
  93
  94 static int
  95 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
  96 {
  97 #ifdef SCTL_MASK32
  98         static const char machine32[] = "i386";
  99 #endif
 100         int error;
 101
 102 #ifdef SCTL_MASK32
 103         if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
 104                 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
 105         else
 106 #endif
 107                 error = SYSCTL_OUT(req, machine, sizeof(machine));
 108         return (error);
 109
 110 }
 111 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD,
 112     NULL, 0, sysctl_hw_machine, "A", "Machine class");
 113 #else
 114 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
 115     machine, 0, "Machine class");
 116 #endif
 117
 118 static char cpu_model[128];
 119 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
 120     cpu_model, 0, "Machine model");
 121
 122 static int hw_clockrate;
 123 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
 124     &hw_clockrate, 0, "CPU instruction clock rate");
 125
 126 u_int hv_high;
 127 char hv_vendor[16];
 128 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD, hv_vendor, 0,
 129     "Hypervisor vendor");
 130
 131 static eventhandler_tag tsc_post_tag;
 132
 133 static char cpu_brand[48];
 134
 135 #ifdef __i386__
 136 #define MAX_BRAND_INDEX 8
 137
 138 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
 139         NULL,                   /* No brand */
 140         "Intel Celeron",
 141         "Intel Pentium III",
 142         "Intel Pentium III Xeon",
 143         NULL,
 144         NULL,
 145         NULL,
 146         NULL,
 147         "Intel Pentium 4"
 148 };
 149 #endif
 150
 151 static struct {
 152         char    *cpu_name;
 153         int     cpu_class;
 154 } cpus[] = {
 155 #ifdef __i386__
 156         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
 157         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
 158         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
 159         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
 160         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
 161         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
 162         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
 163         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
 164         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
 165         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
 166         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
 167         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
 168         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
 169         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
 170         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
 171         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
 172         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
 173 #else
 174         { "Clawhammer",         CPUCLASS_K8 },          /* CPU_CLAWHAMMER */
 175         { "Sledgehammer",       CPUCLASS_K8 },          /* CPU_SLEDGEHAMMER */
 176 #endif
 177 };
 178
 179 static struct {
 180         char    *vendor;
 181         u_int   vendor_id;
 182 } cpu_vendors[] = {
 183         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
 184         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
 185         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
 186 #ifdef __i386__
 187         { NSC_VENDOR_ID,        CPU_VENDOR_NSC },       /* Geode by NSC */
 188         { CYRIX_VENDOR_ID,      CPU_VENDOR_CYRIX },     /* CyrixInstead */
 189         { TRANSMETA_VENDOR_ID,  CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
 190         { SIS_VENDOR_ID,        CPU_VENDOR_SIS },       /* SiS SiS SiS  */
 191         { UMC_VENDOR_ID,        CPU_VENDOR_UMC },       /* UMC UMC UMC  */
 192         { NEXGEN_VENDOR_ID,     CPU_VENDOR_NEXGEN },    /* NexGenDriven */
 193         { RISE_VENDOR_ID,       CPU_VENDOR_RISE },      /* RiseRiseRise */
 194 #if 0
 195         /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
 196         { "TransmetaCPU",       CPU_VENDOR_TRANSMETA },
 197 #endif
 198 #endif
 199 };
 200
 201 void
 202 printcpuinfo(void)
 203 {
 204         u_int regs[4], i;
 205         char *brand;
 206
 207         cpu_class = cpus[cpu].cpu_class;
 208         printf("CPU: ");
 209         strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
 210
 211         /* Check for extended CPUID information and a processor name. */
 212         if (cpu_exthigh >= 0x80000004) {
 213                 brand = cpu_brand;
 214                 for (i = 0x80000002; i < 0x80000005; i++) {
 215                         do_cpuid(i, regs);
 216                         memcpy(brand, regs, sizeof(regs));
 217                         brand += sizeof(regs);
 218                 }
 219         }
 220
 221         switch (cpu_vendor_id) {
 222         case CPU_VENDOR_INTEL:
 223 #ifdef __i386__
 224                 if ((cpu_id & 0xf00) > 0x300) {
 225                         u_int brand_index;
 226
 227                         cpu_model[0] = '\0';
 228
 229                         switch (cpu_id & 0x3000) {
 230                         case 0x1000:
 231                                 strcpy(cpu_model, "Overdrive ");
 232                                 break;
 233                         case 0x2000:
 234                                 strcpy(cpu_model, "Dual ");
 235                                 break;
 236                         }
 237
 238                         switch (cpu_id & 0xf00) {
 239                         case 0x400:
 240                                 strcat(cpu_model, "i486 ");
 241                                 /* Check the particular flavor of 486 */
 242                                 switch (cpu_id & 0xf0) {
 243                                 case 0x00:
 244                                 case 0x10:
 245                                         strcat(cpu_model, "DX");
 246                                         break;
 247                                 case 0x20:
 248                                         strcat(cpu_model, "SX");
 249                                         break;
 250                                 case 0x30:
 251                                         strcat(cpu_model, "DX2");
 252                                         break;
 253                                 case 0x40:
 254                                         strcat(cpu_model, "SL");
 255                                         break;
 256                                 case 0x50:
 257                                         strcat(cpu_model, "SX2");
 258                                         break;
 259                                 case 0x70:
 260                                         strcat(cpu_model,
 261                                             "DX2 Write-Back Enhanced");
 262                                         break;
 263                                 case 0x80:
 264                                         strcat(cpu_model, "DX4");
 265                                         break;
 266                                 }
 267                                 break;
 268                         case 0x500:
 269                                 /* Check the particular flavor of 586 */
 270                                 strcat(cpu_model, "Pentium");
 271                                 switch (cpu_id & 0xf0) {
 272                                 case 0x00:
 273                                         strcat(cpu_model, " A-step");
 274                                         break;
 275                                 case 0x10:
 276                                         strcat(cpu_model, "/P5");
 277                                         break;
 278                                 case 0x20:
 279                                         strcat(cpu_model, "/P54C");
 280                                         break;
 281                                 case 0x30:
 282                                         strcat(cpu_model, "/P24T");
 283                                         break;
 284                                 case 0x40:
 285                                         strcat(cpu_model, "/P55C");
 286                                         break;
 287                                 case 0x70:
 288                                         strcat(cpu_model, "/P54C");
 289                                         break;
 290                                 case 0x80:
 291                                         strcat(cpu_model, "/P55C (quarter-micron)");
 292                                         break;
 293                                 default:
 294                                         /* nothing */
 295                                         break;
 296                                 }
 297 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 298                                 /*
 299                                  * XXX - If/when Intel fixes the bug, this
 300                                  * should also check the version of the
 301                                  * CPU, not just that it's a Pentium.
 302                                  */
 303                                 has_f00f_bug = 1;
 304 #endif
 305                                 break;
 306                         case 0x600:
 307                                 /* Check the particular flavor of 686 */
 308                                 switch (cpu_id & 0xf0) {
 309                                 case 0x00:
 310                                         strcat(cpu_model, "Pentium Pro A-step");
 311                                         break;
 312                                 case 0x10:
 313                                         strcat(cpu_model, "Pentium Pro");
 314                                         break;
 315                                 case 0x30:
 316                                 case 0x50:
 317                                 case 0x60:
 318                                         strcat(cpu_model,
 319                                 "Pentium II/Pentium II Xeon/Celeron");
 320                                         cpu = CPU_PII;
 321                                         break;
 322                                 case 0x70:
 323                                 case 0x80:
 324                                 case 0xa0:
 325                                 case 0xb0:
 326                                         strcat(cpu_model,
 327                                         "Pentium III/Pentium III Xeon/Celeron");
 328                                         cpu = CPU_PIII;
 329                                         break;
 330                                 default:
 331                                         strcat(cpu_model, "Unknown 80686");
 332                                         break;
 333                                 }
 334                                 break;
 335                         case 0xf00:
 336                                 strcat(cpu_model, "Pentium 4");
 337                                 cpu = CPU_P4;
 338                                 break;
 339                         default:
 340                                 strcat(cpu_model, "unknown");
 341                                 break;
 342                         }
 343
 344                         /*
 345                          * If we didn't get a brand name from the extended
 346                          * CPUID, try to look it up in the brand table.
 347                          */
 348                         if (cpu_high > 0 && *cpu_brand == '\0') {
 349                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
 350                                 if (brand_index <= MAX_BRAND_INDEX &&
 351                                     cpu_brandtable[brand_index] != NULL)
 352                                         strcpy(cpu_brand,
 353                                             cpu_brandtable[brand_index]);
 354                         }
 355                 }
 356 #else
 357                 /* Please make up your mind folks! */
 358                 strcat(cpu_model, "EM64T");
 359 #endif
 360                 break;
 361         case CPU_VENDOR_AMD:
 362                 /*
 363                  * Values taken from AMD Processor Recognition
 364                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
 365                  * (also describes ``Features'' encodings.
 366                  */
 367                 strcpy(cpu_model, "AMD ");
 368 #ifdef __i386__
 369                 switch (cpu_id & 0xFF0) {
 370                 case 0x410:
 371                         strcat(cpu_model, "Standard Am486DX");
 372                         break;
 373                 case 0x430:
 374                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
 375                         break;
 376                 case 0x470:
 377                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
 378                         break;
 379                 case 0x480:
 380                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
 381                         break;
 382                 case 0x490:
 383                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
 384                         break;
 385                 case 0x4E0:
 386                         strcat(cpu_model, "Am5x86 Write-Through");
 387                         break;
 388                 case 0x4F0:
 389                         strcat(cpu_model, "Am5x86 Write-Back");
 390                         break;
 391                 case 0x500:
 392                         strcat(cpu_model, "K5 model 0");
 393                         break;
 394                 case 0x510:
 395                         strcat(cpu_model, "K5 model 1");
 396                         break;
 397                 case 0x520:
 398                         strcat(cpu_model, "K5 PR166 (model 2)");
 399                         break;
 400                 case 0x530:
 401                         strcat(cpu_model, "K5 PR200 (model 3)");
 402                         break;
 403                 case 0x560:
 404                         strcat(cpu_model, "K6");
 405                         break;
 406                 case 0x570:
 407                         strcat(cpu_model, "K6 266 (model 1)");
 408                         break;
 409                 case 0x580:
 410                         strcat(cpu_model, "K6-2");
 411                         break;
 412                 case 0x590:
 413                         strcat(cpu_model, "K6-III");
 414                         break;
 415                 case 0x5a0:
 416                         strcat(cpu_model, "Geode LX");
 417                         break;
 418                 default:
 419                         strcat(cpu_model, "Unknown");
 420                         break;
 421                 }
 422 #else
 423                 if ((cpu_id & 0xf00) == 0xf00)
 424                         strcat(cpu_model, "AMD64 Processor");
 425                 else
 426                         strcat(cpu_model, "Unknown");
 427 #endif
 428                 break;
 429 #ifdef __i386__
 430         case CPU_VENDOR_CYRIX:
 431                 strcpy(cpu_model, "Cyrix ");
 432                 switch (cpu_id & 0xff0) {
 433                 case 0x440:
 434                         strcat(cpu_model, "MediaGX");
 435                         break;
 436                 case 0x520:
 437                         strcat(cpu_model, "6x86");
 438                         break;
 439                 case 0x540:
 440                         cpu_class = CPUCLASS_586;
 441                         strcat(cpu_model, "GXm");
 442                         break;
 443                 case 0x600:
 444                         strcat(cpu_model, "6x86MX");
 445                         break;
 446                 default:
 447                         /*
 448                          * Even though CPU supports the cpuid
 449                          * instruction, it can be disabled.
 450                          * Therefore, this routine supports all Cyrix
 451                          * CPUs.
 452                          */
 453                         switch (cyrix_did & 0xf0) {
 454                         case 0x00:
 455                                 switch (cyrix_did & 0x0f) {
 456                                 case 0x00:
 457                                         strcat(cpu_model, "486SLC");
 458                                         break;
 459                                 case 0x01:
 460                                         strcat(cpu_model, "486DLC");
 461                                         break;
 462                                 case 0x02:
 463                                         strcat(cpu_model, "486SLC2");
 464                                         break;
 465                                 case 0x03:
 466                                         strcat(cpu_model, "486DLC2");
 467                                         break;
 468                                 case 0x04:
 469                                         strcat(cpu_model, "486SRx");
 470                                         break;
 471                                 case 0x05:
 472                                         strcat(cpu_model, "486DRx");
 473                                         break;
 474                                 case 0x06:
 475                                         strcat(cpu_model, "486SRx2");
 476                                         break;
 477                                 case 0x07:
 478                                         strcat(cpu_model, "486DRx2");
 479                                         break;
 480                                 case 0x08:
 481                                         strcat(cpu_model, "486SRu");
 482                                         break;
 483                                 case 0x09:
 484                                         strcat(cpu_model, "486DRu");
 485                                         break;
 486                                 case 0x0a:
 487                                         strcat(cpu_model, "486SRu2");
 488                                         break;
 489                                 case 0x0b:
 490                                         strcat(cpu_model, "486DRu2");
 491                                         break;
 492                                 default:
 493                                         strcat(cpu_model, "Unknown");
 494                                         break;
 495                                 }
 496                                 break;
 497                         case 0x10:
 498                                 switch (cyrix_did & 0x0f) {
 499                                 case 0x00:
 500                                         strcat(cpu_model, "486S");
 501                                         break;
 502                                 case 0x01:
 503                                         strcat(cpu_model, "486S2");
 504                                         break;
 505                                 case 0x02:
 506                                         strcat(cpu_model, "486Se");
 507                                         break;
 508                                 case 0x03:
 509                                         strcat(cpu_model, "486S2e");
 510                                         break;
 511                                 case 0x0a:
 512                                         strcat(cpu_model, "486DX");
 513                                         break;
 514                                 case 0x0b:
 515                                         strcat(cpu_model, "486DX2");
 516                                         break;
 517                                 case 0x0f:
 518                                         strcat(cpu_model, "486DX4");
 519                                         break;
 520                                 default:
 521                                         strcat(cpu_model, "Unknown");
 522                                         break;
 523                                 }
 524                                 break;
 525                         case 0x20:
 526                                 if ((cyrix_did & 0x0f) < 8)
 527                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
 528                                 else
 529                                         strcat(cpu_model, "5x86");
 530                                 break;
 531                         case 0x30:
 532                                 strcat(cpu_model, "6x86");
 533                                 break;
 534                         case 0x40:
 535                                 if ((cyrix_did & 0xf000) == 0x3000) {
 536                                         cpu_class = CPUCLASS_586;
 537                                         strcat(cpu_model, "GXm");
 538                                 } else
 539                                         strcat(cpu_model, "MediaGX");
 540                                 break;
 541                         case 0x50:
 542                                 strcat(cpu_model, "6x86MX");
 543                                 break;
 544                         case 0xf0:
 545                                 switch (cyrix_did & 0x0f) {
 546                                 case 0x0d:
 547                                         strcat(cpu_model, "Overdrive CPU");
 548                                         break;
 549                                 case 0x0e:
 550                                         strcpy(cpu_model, "Texas Instruments 486SXL");
 551                                         break;
 552                                 case 0x0f:
 553                                         strcat(cpu_model, "486SLC/DLC");
 554                                         break;
 555                                 default:
 556                                         strcat(cpu_model, "Unknown");
 557                                         break;
 558                                 }
 559                                 break;
 560                         default:
 561                                 strcat(cpu_model, "Unknown");
 562                                 break;
 563                         }
 564                         break;
 565                 }
 566                 break;
 567         case CPU_VENDOR_RISE:
 568                 strcpy(cpu_model, "Rise ");
 569                 switch (cpu_id & 0xff0) {
 570                 case 0x500:     /* 6401 and 6441 (Kirin) */
 571                 case 0x520:     /* 6510 (Lynx) */
 572                         strcat(cpu_model, "mP6");
 573                         break;
 574                 default:
 575                         strcat(cpu_model, "Unknown");
 576                 }
 577                 break;
 578 #endif
 579         case CPU_VENDOR_CENTAUR:
 580 #ifdef __i386__
 581                 switch (cpu_id & 0xff0) {
 582                 case 0x540:
 583                         strcpy(cpu_model, "IDT WinChip C6");
 584                         break;
 585                 case 0x580:
 586                         strcpy(cpu_model, "IDT WinChip 2");
 587                         break;
 588                 case 0x590:
 589                         strcpy(cpu_model, "IDT WinChip 3");
 590                         break;
 591                 case 0x660:
 592                         strcpy(cpu_model, "VIA C3 Samuel");
 593                         break;
 594                 case 0x670:
 595                         if (cpu_id & 0x8)
 596                                 strcpy(cpu_model, "VIA C3 Ezra");
 597                         else
 598                                 strcpy(cpu_model, "VIA C3 Samuel 2");
 599                         break;
 600                 case 0x680:
 601                         strcpy(cpu_model, "VIA C3 Ezra-T");
 602                         break;
 603                 case 0x690:
 604                         strcpy(cpu_model, "VIA C3 Nehemiah");
 605                         break;
 606                 case 0x6a0:
 607                 case 0x6d0:
 608                         strcpy(cpu_model, "VIA C7 Esther");
 609                         break;
 610                 case 0x6f0:
 611                         strcpy(cpu_model, "VIA Nano");
 612                         break;
 613                 default:
 614                         strcpy(cpu_model, "VIA/IDT Unknown");
 615                 }
 616 #else
 617                 strcpy(cpu_model, "VIA ");
 618                 if ((cpu_id & 0xff0) == 0x6f0)
 619                         strcat(cpu_model, "Nano Processor");
 620                 else
 621                         strcat(cpu_model, "Unknown");
 622 #endif
 623                 break;
 624 #ifdef __i386__
 625         case CPU_VENDOR_IBM:
 626                 strcpy(cpu_model, "Blue Lightning CPU");
 627                 break;
 628         case CPU_VENDOR_NSC:
 629                 switch (cpu_id & 0xff0) {
 630                 case 0x540:
 631                         strcpy(cpu_model, "Geode SC1100");
 632                         cpu = CPU_GEODE1100;
 633                         break;
 634                 default:
 635                         strcpy(cpu_model, "Geode/NSC unknown");
 636                         break;
 637                 }
 638                 break;
 639 #endif
 640         default:
 641                 strcat(cpu_model, "Unknown");
 642                 break;
 643         }
 644
 645         /*
 646          * Replace cpu_model with cpu_brand minus leading spaces if
 647          * we have one.
 648          */
 649         brand = cpu_brand;
 650         while (*brand == ' ')
 651                 ++brand;
 652         if (*brand != '\0')
 653                 strcpy(cpu_model, brand);
 654
 655         printf("%s (", cpu_model);
 656         if (tsc_freq != 0) {
 657                 hw_clockrate = (tsc_freq + 5000) / 1000000;
 658                 printf("%jd.%02d-MHz ",
 659                     (intmax_t)(tsc_freq + 4999) / 1000000,
 660                     (u_int)((tsc_freq + 4999) / 10000) % 100);
 661         }
 662         switch(cpu_class) {
 663 #ifdef __i386__
 664         case CPUCLASS_286:
 665                 printf("286");
 666                 break;
 667         case CPUCLASS_386:
 668                 printf("386");
 669                 break;
 670 #if defined(I486_CPU)
 671         case CPUCLASS_486:
 672                 printf("486");
 673                 break;
 674 #endif
 675 #if defined(I586_CPU)
 676         case CPUCLASS_586:
 677                 printf("586");
 678                 break;
 679 #endif
 680 #if defined(I686_CPU)
 681         case CPUCLASS_686:
 682                 printf("686");
 683                 break;
 684 #endif
 685 #else
 686         case CPUCLASS_K8:
 687                 printf("K8");
 688                 break;
 689 #endif
 690         default:
 691                 printf("Unknown");      /* will panic below... */
 692         }
 693         printf("-class CPU)\n");
 694         if (*cpu_vendor)
 695                 printf("  Origin=\"%s\"", cpu_vendor);
 696         if (cpu_id)
 697                 printf("  Id=0x%x", cpu_id);
 698
 699         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 700             cpu_vendor_id == CPU_VENDOR_AMD ||
 701             cpu_vendor_id == CPU_VENDOR_CENTAUR ||
 702 #ifdef __i386__
 703             cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
 704             cpu_vendor_id == CPU_VENDOR_RISE ||
 705             cpu_vendor_id == CPU_VENDOR_NSC ||
 706             (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
 707 #endif
 708             0) {
 709                 printf("  Family=0x%x", CPUID_TO_FAMILY(cpu_id));
 710                 printf("  Model=0x%x", CPUID_TO_MODEL(cpu_id));
 711                 printf("  Stepping=%u", cpu_id & CPUID_STEPPING);
 712 #ifdef __i386__
 713                 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
 714                         printf("\n  DIR=0x%04x", cyrix_did);
 715 #endif
 716
 717                 /*
 718                  * AMD CPUID Specification
 719                  * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
 720                  *
 721                  * Intel Processor Identification and CPUID Instruction
 722                  * http://www.intel.com/assets/pdf/appnote/241618.pdf
 723                  */
 724                 if (cpu_high > 0) {
 725
 726                         /*
 727                          * Here we should probably set up flags indicating
 728                          * whether or not various features are available.
 729                          * The interesting ones are probably VME, PSE, PAE,
 730                          * and PGE.  The code already assumes without bothering
 731                          * to check that all CPUs >= Pentium have a TSC and
 732                          * MSRs.
 733                          */
 734                         printf("\n  Features=0x%b", cpu_feature,
 735                         "\020"
 736                         "\001FPU"       /* Integral FPU */
 737                         "\002VME"       /* Extended VM86 mode support */
 738                         "\003DE"        /* Debugging Extensions (CR4.DE) */
 739                         "\004PSE"       /* 4MByte page tables */
 740                         "\005TSC"       /* Timestamp counter */
 741                         "\006MSR"       /* Machine specific registers */
 742                         "\007PAE"       /* Physical address extension */
 743                         "\010MCE"       /* Machine Check support */
 744                         "\011CX8"       /* CMPEXCH8 instruction */
 745                         "\012APIC"      /* SMP local APIC */
 746                         "\013oldMTRR"   /* Previous implementation of MTRR */
 747                         "\014SEP"       /* Fast System Call */
 748                         "\015MTRR"      /* Memory Type Range Registers */
 749                         "\016PGE"       /* PG_G (global bit) support */
 750                         "\017MCA"       /* Machine Check Architecture */
 751                         "\020CMOV"      /* CMOV instruction */
 752                         "\021PAT"       /* Page attributes table */
 753                         "\022PSE36"     /* 36 bit address space support */
 754                         "\023PN"        /* Processor Serial number */
 755                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
 756                         "\025<b20>"
 757                         "\026DTS"       /* Debug Trace Store */
 758                         "\027ACPI"      /* ACPI support */
 759                         "\030MMX"       /* MMX instructions */
 760                         "\031FXSR"      /* FXSAVE/FXRSTOR */
 761                         "\032SSE"       /* Streaming SIMD Extensions */
 762                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
 763                         "\034SS"        /* Self snoop */
 764                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
 765                         "\036TM"        /* Thermal Monitor clock slowdown */
 766                         "\037IA64"      /* CPU can execute IA64 instructions */
 767                         "\040PBE"       /* Pending Break Enable */
 768                         );
 769
 770                         if (cpu_feature2 != 0) {
 771                                 printf("\n  Features2=0x%b", cpu_feature2,
 772                                 "\020"
 773                                 "\001SSE3"      /* SSE3 */
 774                                 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
 775                                 "\003DTES64"    /* 64-bit Debug Trace */
 776                                 "\004MON"       /* MONITOR/MWAIT Instructions */
 777                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
 778                                 "\006VMX"       /* Virtual Machine Extensions */
 779                                 "\007SMX"       /* Safer Mode Extensions */
 780                                 "\010EST"       /* Enhanced SpeedStep */
 781                                 "\011TM2"       /* Thermal Monitor 2 */
 782                                 "\012SSSE3"     /* SSSE3 */
 783                                 "\013CNXT-ID"   /* L1 context ID available */
 784                                 "\014<b11>"
 785                                 "\015FMA"       /* Fused Multiply Add */
 786                                 "\016CX16"      /* CMPXCHG16B Instruction */
 787                                 "\017xTPR"      /* Send Task Priority Messages*/
 788                                 "\020PDCM"      /* Perf/Debug Capability MSR */
 789                                 "\021<b16>"
 790                                 "\022PCID"      /* Process-context Identifiers*/
 791                                 "\023DCA"       /* Direct Cache Access */
 792                                 "\024SSE4.1"    /* SSE 4.1 */
 793                                 "\025SSE4.2"    /* SSE 4.2 */
 794                                 "\026x2APIC"    /* xAPIC Extensions */
 795                                 "\027MOVBE"     /* MOVBE Instruction */
 796                                 "\030POPCNT"    /* POPCNT Instruction */
 797                                 "\031TSCDLT"    /* TSC-Deadline Timer */
 798                                 "\032AESNI"     /* AES Crypto */
 799                                 "\033XSAVE"     /* XSAVE/XRSTOR States */
 800                                 "\034OSXSAVE"   /* OS-Enabled State Management*/
 801                                 "\035AVX"       /* Advanced Vector Extensions */
 802                                 "\036F16C"      /* Half-precision conversions */
 803                                 "\037RDRAND"    /* RDRAND Instruction */
 804                                 "\040HV"        /* Hypervisor */
 805                                 );
 806                         }
 807
 808                         if (amd_feature != 0) {
 809                                 printf("\n  AMD Features=0x%b", amd_feature,
 810                                 "\020"          /* in hex */
 811                                 "\001<s0>"      /* Same */
 812                                 "\002<s1>"      /* Same */
 813                                 "\003<s2>"      /* Same */
 814                                 "\004<s3>"      /* Same */
 815                                 "\005<s4>"      /* Same */
 816                                 "\006<s5>"      /* Same */
 817                                 "\007<s6>"      /* Same */
 818                                 "\010<s7>"      /* Same */
 819                                 "\011<s8>"      /* Same */
 820                                 "\012<s9>"      /* Same */
 821                                 "\013<b10>"     /* Undefined */
 822                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
 823                                 "\015<s12>"     /* Same */
 824                                 "\016<s13>"     /* Same */
 825                                 "\017<s14>"     /* Same */
 826                                 "\020<s15>"     /* Same */
 827                                 "\021<s16>"     /* Same */
 828                                 "\022<s17>"     /* Same */
 829                                 "\023<b18>"     /* Reserved, unknown */
 830                                 "\024MP"        /* Multiprocessor Capable */
 831                                 "\025NX"        /* Has EFER.NXE, NX */
 832                                 "\026<b21>"     /* Undefined */
 833                                 "\027MMX+"      /* AMD MMX Extensions */
 834                                 "\030<s23>"     /* Same */
 835                                 "\031<s24>"     /* Same */
 836                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
 837                                 "\033Page1GB"   /* 1-GB large page support */
 838                                 "\034RDTSCP"    /* RDTSCP */
 839                                 "\035<b28>"     /* Undefined */
 840                                 "\036LM"        /* 64 bit long mode */
 841                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
 842                                 "\0403DNow!"    /* AMD 3DNow! */
 843                                 );
 844                         }
 845
 846                         if (amd_feature2 != 0) {
 847                                 printf("\n  AMD Features2=0x%b", amd_feature2,
 848                                 "\020"
 849                                 "\001LAHF"      /* LAHF/SAHF in long mode */
 850                                 "\002CMP"       /* CMP legacy */
 851                                 "\003SVM"       /* Secure Virtual Mode */
 852                                 "\004ExtAPIC"   /* Extended APIC register */
 853                                 "\005CR8"       /* CR8 in legacy mode */
 854                                 "\006ABM"       /* LZCNT instruction */
 855                                 "\007SSE4A"     /* SSE4A */
 856                                 "\010MAS"       /* Misaligned SSE mode */
 857                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
 858                                 "\012OSVW"      /* OS visible workaround */
 859                                 "\013IBS"       /* Instruction based sampling */
 860                                 "\014XOP"       /* XOP extended instructions */
 861                                 "\015SKINIT"    /* SKINIT/STGI */
 862                                 "\016WDT"       /* Watchdog timer */
 863                                 "\017<b14>"
 864                                 "\020LWP"       /* Lightweight Profiling */
 865                                 "\021FMA4"      /* 4-operand FMA instructions */
 866                                 "\022TCE"       /* Translation Cache Extension */
 867                                 "\023<b18>"
 868                                 "\024NodeId"    /* NodeId MSR support */
 869                                 "\025<b20>"
 870                                 "\026TBM"       /* Trailing Bit Manipulation */
 871                                 "\027Topology"  /* Topology Extensions */
 872                                 "\030PCXC"      /* Core perf count */
 873                                 "\031PNXC"      /* NB perf count */
 874                                 "\032<b25>"
 875                                 "\033DBE"       /* Data Breakpoint extension */
 876                                 "\034PTSC"      /* Performance TSC */
 877                                 "\035PL2I"      /* L2I perf count */
 878                                 "\036<b29>"
 879                                 "\037<b30>"
 880                                 "\040<b31>"
 881                                 );
 882                         }
 883
 884                         if (cpu_stdext_feature != 0) {
 885                                 printf("\n  Structured Extended Features=0x%b",
 886                                     cpu_stdext_feature,
 887                                        "\020"
 888                                        /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
 889                                        "\001FSGSBASE"
 890                                        "\002TSCADJ"
 891                                        /* Bit Manipulation Instructions */
 892                                        "\004BMI1"
 893                                        /* Hardware Lock Elision */
 894                                        "\005HLE"
 895                                        /* Advanced Vector Instructions 2 */
 896                                        "\006AVX2"
 897                                        /* Supervisor Mode Execution Prot. */
 898                                        "\010SMEP"
 899                                        /* Bit Manipulation Instructions */
 900                                        "\011BMI2"
 901                                        "\012ERMS"
 902                                        /* Invalidate Processor Context ID */
 903                                        "\013INVPCID"
 904                                        /* Restricted Transactional Memory */
 905                                        "\014RTM"
 906                                        "\015PQM"
 907                                        "\016NFPUSG"
 908                                        "\020PQE"
 909                                        /* Intel Memory Protection Extensions */
 910                                        "\017MPX"
 911                                        /* AVX512 Foundation */
 912                                        "\021AVX512F"
 913                                        /* Enhanced NRBG */
 914                                        "\023RDSEED"
 915                                        /* ADCX + ADOX */
 916                                        "\024ADX"
 917                                        /* Supervisor Mode Access Prevention */
 918                                        "\025SMAP"
 919                                        "\030CLFLUSHOPT"
 920                                        "\032PROCTRACE"
 921                                        "\033AVX512PF"
 922                                        "\034AVX512ER"
 923                                        "\035AVX512CD"
 924                                        "\036SHA"
 925                                        );
 926                         }
 927
 928                         if (cpu_stdext_feature2 != 0) {
 929                                 printf("\n  Structured Extended Features2=0x%b",
 930                                     cpu_stdext_feature2,
 931                                        "\020"
 932                                        "\001PREFETCHWT1"
 933                                        "\004PKU"
 934                                        "\005OSPKE"
 935                                        );
 936                         }
 937
 938                         if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
 939                                 cpuid_count(0xd, 0x1, regs);
 940                                 if (regs[0] != 0) {
 941                                         printf("\n  XSAVE Features=0x%b",
 942                                             regs[0],
 943                                             "\020"
 944                                             "\001XSAVEOPT"
 945                                             "\002XSAVEC"
 946                                             "\003XINUSE"
 947                                             "\004XSAVES");
 948                                 }
 949                         }
 950
 951                         if (via_feature_rng != 0 || via_feature_xcrypt != 0)
 952                                 print_via_padlock_info();
 953
 954                         if (cpu_feature2 & CPUID2_VMX)
 955                                 print_vmx_info();
 956
 957                         if (amd_feature2 & AMDID2_SVM)
 958                                 print_svm_info();
 959
 960                         if ((cpu_feature & CPUID_HTT) &&
 961                             cpu_vendor_id == CPU_VENDOR_AMD)
 962                                 cpu_feature &= ~CPUID_HTT;
 963
 964                         /*
 965                          * If this CPU supports P-state invariant TSC then
 966                          * mention the capability.
 967                          */
 968                         if (tsc_is_invariant) {
 969                                 printf("\n  TSC: P-state invariant");
 970                                 if (tsc_perf_stat)
 971                                         printf(", performance statistics");
 972                         }
 973                 }
 974 #ifdef __i386__
 975         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
 976                 printf("  DIR=0x%04x", cyrix_did);
 977                 printf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
 978                 printf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
 979 #ifndef CYRIX_CACHE_REALLY_WORKS
 980                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
 981                         printf("\n  CPU cache: write-through mode");
 982 #endif
 983 #endif
 984         }
 985
 986         /* Avoid ugly blank lines: only print newline when we have to. */
 987         if (*cpu_vendor || cpu_id)
 988                 printf("\n");
 989
 990         if (bootverbose) {
 991                 if (cpu_vendor_id == CPU_VENDOR_AMD)
 992                         print_AMD_info();
 993                 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
 994                         print_INTEL_info();
 995 #ifdef __i386__
 996                 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
 997                         print_transmeta_info();
 998 #endif
 999         }
1000
1001         print_hypervisor_info();
1002 }
1003
1004 void
1005 panicifcpuunsupported(void)
1006 {
1007
1008 #ifdef __i386__
1009 #if !defined(lint)
1010 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1011 #error This kernel is not configured for one of the supported CPUs
1012 #endif
1013 #else /* lint */
1014 #endif /* lint */
1015 #else /* __amd64__ */
1016 #ifndef HAMMER
1017 #error "You need to specify a cpu type"
1018 #endif
1019 #endif
1020         /*
1021          * Now that we have told the user what they have,
1022          * let them know if that machine type isn't configured.
1023          */
1024         switch (cpu_class) {
1025 #ifdef __i386__
1026         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
1027         case CPUCLASS_386:
1028 #if !defined(I486_CPU)
1029         case CPUCLASS_486:
1030 #endif
1031 #if !defined(I586_CPU)
1032         case CPUCLASS_586:
1033 #endif
1034 #if !defined(I686_CPU)
1035         case CPUCLASS_686:
1036 #endif
1037 #else /* __amd64__ */
1038         case CPUCLASS_X86:
1039 #ifndef HAMMER
1040         case CPUCLASS_K8:
1041 #endif
1042 #endif
1043                 panic("CPU class not configured");
1044         default:
1045                 break;
1046         }
1047 }
1048
1049 #ifdef __i386__
1050 static  volatile u_int trap_by_rdmsr;
1051
1052 /*
1053  * Special exception 6 handler.
1054  * The rdmsr instruction generates invalid opcodes fault on 486-class
1055  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
1056  * function identblue() when this handler is called.  Stacked eip should
1057  * be advanced.
1058  */
1059 inthand_t       bluetrap6;
1060 #ifdef __GNUCLIKE_ASM
1061 __asm
1062 ("                                                                      \n\
1063         .text                                                           \n\
1064         .p2align 2,0x90                                                 \n\
1065         .type   " __XSTRING(CNAME(bluetrap6)) ",@function               \n\
1066 " __XSTRING(CNAME(bluetrap6)) ":                                        \n\
1067         ss                                                              \n\
1068         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1069         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1070         iret                                                            \n\
1071 ");
1072 #endif
1073
1074 /*
1075  * Special exception 13 handler.
1076  * Accessing non-existent MSR generates general protection fault.
1077  */
1078 inthand_t       bluetrap13;
1079 #ifdef __GNUCLIKE_ASM
1080 __asm
1081 ("                                                                      \n\
1082         .text                                                           \n\
1083         .p2align 2,0x90                                                 \n\
1084         .type   " __XSTRING(CNAME(bluetrap13)) ",@function              \n\
1085 " __XSTRING(CNAME(bluetrap13)) ":                                       \n\
1086         ss                                                              \n\
1087         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1088         popl    %eax            /* discard error code */                \n\
1089         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1090         iret                                                            \n\
1091 ");
1092 #endif
1093
1094 /*
1095  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1096  * support cpuid instruction.  This function should be called after
1097  * loading interrupt descriptor table register.
1098  *
1099  * I don't like this method that handles fault, but I couldn't get
1100  * information for any other methods.  Does blue giant know?
1101  */
1102 static int
1103 identblue(void)
1104 {
1105
1106         trap_by_rdmsr = 0;
1107
1108         /*
1109          * Cyrix 486-class CPU does not support rdmsr instruction.
1110          * The rdmsr instruction generates invalid opcode fault, and exception
1111          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
1112          * bluetrap6() set the magic number to trap_by_rdmsr.
1113          */
1114         setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1115             GSEL(GCODE_SEL, SEL_KPL));
1116
1117         /*
1118          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1119          * In this case, rdmsr generates general protection fault, and
1120          * exception will be trapped by bluetrap13().
1121          */
1122         setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1123             GSEL(GCODE_SEL, SEL_KPL));
1124
1125         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
1126
1127         if (trap_by_rdmsr == 0xa8c1d)
1128                 return IDENTBLUE_CYRIX486;
1129         else if (trap_by_rdmsr == 0xa89c4)
1130                 return IDENTBLUE_CYRIXM2;
1131         return IDENTBLUE_IBMCPU;
1132 }
1133
1134
1135 /*
1136  * identifycyrix() set lower 16 bits of cyrix_did as follows:
1137  *
1138  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
1139  * +-------+-------+---------------+
1140  * |  SID  |  RID  |   Device ID   |
1141  * |    (DIR 1)    |    (DIR 0)    |
1142  * +-------+-------+---------------+
1143  */
1144 static void
1145 identifycyrix(void)
1146 {
1147         register_t saveintr;
1148         int     ccr2_test = 0, dir_test = 0;
1149         u_char  ccr2, ccr3;
1150
1151         saveintr = intr_disable();
1152
1153         ccr2 = read_cyrix_reg(CCR2);
1154         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1155         read_cyrix_reg(CCR2);
1156         if (read_cyrix_reg(CCR2) != ccr2)
1157                 ccr2_test = 1;
1158         write_cyrix_reg(CCR2, ccr2);
1159
1160         ccr3 = read_cyrix_reg(CCR3);
1161         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1162         read_cyrix_reg(CCR3);
1163         if (read_cyrix_reg(CCR3) != ccr3)
1164                 dir_test = 1;                                   /* CPU supports DIRs. */
1165         write_cyrix_reg(CCR3, ccr3);
1166
1167         if (dir_test) {
1168                 /* Device ID registers are available. */
1169                 cyrix_did = read_cyrix_reg(DIR1) << 8;
1170                 cyrix_did += read_cyrix_reg(DIR0);
1171         } else if (ccr2_test)
1172                 cyrix_did = 0x0010;             /* 486S A-step */
1173         else
1174                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
1175
1176         intr_restore(saveintr);
1177 }
1178 #endif
1179
1180 /* Update TSC freq with the value indicated by the caller. */
1181 static void
1182 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1183 {
1184
1185         /* If there was an error during the transition, don't do anything. */
1186         if (status != 0)
1187                 return;
1188
1189         /* Total setting for this level gives the new frequency in MHz. */
1190         hw_clockrate = level->total_set.freq;
1191 }
1192
1193 static void
1194 hook_tsc_freq(void *arg __unused)
1195 {
1196
1197         if (tsc_is_invariant)
1198                 return;
1199
1200         tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1201             tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1202 }
1203
1204 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1205
1206 #ifndef XEN
1207 static const char *const vm_bnames[] = {
1208         "QEMU",                         /* QEMU */
1209         "Plex86",                       /* Plex86 */
1210         "Bochs",                        /* Bochs */
1211         "Xen",                          /* Xen */
1212         "BHYVE",                        /* bhyve */
1213         "Seabios",                      /* KVM */
1214         NULL
1215 };
1216
1217 static const char *const vm_pnames[] = {
1218         "VMware Virtual Platform",      /* VMWare VM */
1219         "Virtual Machine",              /* Microsoft VirtualPC */
1220         "VirtualBox",                   /* Sun xVM VirtualBox */
1221         "Parallels Virtual Platform",   /* Parallels VM */
1222         "KVM",                          /* KVM */
1223         NULL
1224 };
1225
1226 static void
1227 identify_hypervisor(void)
1228 {
1229         u_int regs[4];
1230         char *p;
1231         int i;
1232
1233         /*
1234          * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1235          * http://lkml.org/lkml/2008/10/1/246
1236          *
1237          * KB1009458: Mechanisms to determine if software is running in
1238          * a VMware virtual machine
1239          * http://kb.vmware.com/kb/1009458
1240          */
1241         if (cpu_feature2 & CPUID2_HV) {
1242                 vm_guest = VM_GUEST_VM;
1243                 do_cpuid(0x40000000, regs);
1244                 if (regs[0] >= 0x40000000) {
1245                         hv_high = regs[0];
1246                         ((u_int *)&hv_vendor)[0] = regs[1];
1247                         ((u_int *)&hv_vendor)[1] = regs[2];
1248                         ((u_int *)&hv_vendor)[2] = regs[3];
1249                         hv_vendor[12] = '\0';
1250                         if (strcmp(hv_vendor, "VMwareVMware") == 0)
1251                                 vm_guest = VM_GUEST_VMWARE;
1252                 }
1253                 return;
1254         }
1255
1256         /*
1257          * Examine SMBIOS strings for older hypervisors.
1258          */
1259         p = getenv("smbios.system.serial");
1260         if (p != NULL) {
1261                 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1262                         vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1263                         if (regs[1] == VMW_HVMAGIC) {
1264                                 vm_guest = VM_GUEST_VMWARE;
1265                                 freeenv(p);
1266                                 return;
1267                         }
1268                 }
1269                 freeenv(p);
1270         }
1271
1272         /*
1273          * XXX: Some of these entries may not be needed since they were
1274          * added to FreeBSD before the checks above.
1275          */
1276         p = getenv("smbios.bios.vendor");
1277         if (p != NULL) {
1278                 for (i = 0; vm_bnames[i] != NULL; i++)
1279                         if (strcmp(p, vm_bnames[i]) == 0) {
1280                                 vm_guest = VM_GUEST_VM;
1281                                 freeenv(p);
1282                                 return;
1283                         }
1284                 freeenv(p);
1285         }
1286         p = getenv("smbios.system.product");
1287         if (p != NULL) {
1288                 for (i = 0; vm_pnames[i] != NULL; i++)
1289                         if (strcmp(p, vm_pnames[i]) == 0) {
1290                                 vm_guest = VM_GUEST_VM;
1291                                 freeenv(p);
1292                                 return;
1293                         }
1294                 freeenv(p);
1295         }
1296 }
1297 #endif
1298
1299 /*
1300  * Clear "Limit CPUID Maxval" bit and return true if the caller should
1301  * get the largest standard CPUID function number again if it is set
1302  * from BIOS.  It is necessary for probing correct CPU topology later
1303  * and for the correct operation of the AVX-aware userspace.
1304  */
1305 bool
1306 intel_fix_cpuid(void)
1307 {
1308         uint64_t msr;
1309
1310         if (cpu_vendor_id != CPU_VENDOR_INTEL)
1311                 return (false);
1312         if ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1313             CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1314             (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1315             CPUID_TO_MODEL(cpu_id) >= 0xe)) {
1316                 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1317                 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1318                         msr &= ~IA32_MISC_EN_LIMCPUID;
1319                         wrmsr(MSR_IA32_MISC_ENABLE, msr);
1320                         return (true);
1321                 }
1322         }
1323         return (false);
1324 }
1325
1326 /*
1327  * Final stage of CPU identification.
1328  */
1329 #ifdef __i386__
1330 void
1331 finishidentcpu(void)
1332 #else
1333 void
1334 identify_cpu(void)
1335 #endif
1336 {
1337         u_int regs[4], cpu_stdext_disable;
1338 #ifdef __i386__
1339         u_char ccr3;
1340 #endif
1341
1342 #ifdef __amd64__
1343         do_cpuid(0, regs);
1344         cpu_high = regs[0];
1345         ((u_int *)&cpu_vendor)[0] = regs[1];
1346         ((u_int *)&cpu_vendor)[1] = regs[3];
1347         ((u_int *)&cpu_vendor)[2] = regs[2];
1348         cpu_vendor[12] = '\0';
1349
1350         do_cpuid(1, regs);
1351         cpu_id = regs[0];
1352         cpu_procinfo = regs[1];
1353         cpu_feature = regs[3];
1354         cpu_feature2 = regs[2];
1355 #endif
1356
1357 #ifndef XEN
1358         identify_hypervisor();
1359 #endif
1360         cpu_vendor_id = find_cpu_vendor_id();
1361
1362         if (intel_fix_cpuid()) {
1363                 do_cpuid(0, regs);
1364                 cpu_high = regs[0];
1365         }
1366
1367         if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1368                 do_cpuid(5, regs);
1369                 cpu_mon_mwait_flags = regs[2];
1370                 cpu_mon_min_size = regs[0] &  CPUID5_MON_MIN_SIZE;
1371                 cpu_mon_max_size = regs[1] &  CPUID5_MON_MAX_SIZE;
1372         }
1373
1374         if (cpu_high >= 7) {
1375                 cpuid_count(7, 0, regs);
1376                 cpu_stdext_feature = regs[1];
1377
1378                 /*
1379                  * Some hypervisors fail to filter out unsupported
1380                  * extended features.  For now, disable the
1381                  * extensions, activation of which requires setting a
1382                  * bit in CR4, and which VM monitors do not support.
1383                  */
1384                 if (cpu_feature2 & CPUID2_HV) {
1385                         cpu_stdext_disable = CPUID_STDEXT_FSGSBASE |
1386                             CPUID_STDEXT_SMEP;
1387                 } else
1388                         cpu_stdext_disable = 0;
1389                 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1390                 cpu_stdext_feature &= ~cpu_stdext_disable;
1391                 cpu_stdext_feature2 = regs[2];
1392         }
1393
1394 #ifdef __i386__
1395         if (cpu_high > 0 &&
1396             (cpu_vendor_id == CPU_VENDOR_INTEL ||
1397              cpu_vendor_id == CPU_VENDOR_AMD ||
1398              cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1399              cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1400              cpu_vendor_id == CPU_VENDOR_NSC)) {
1401                 do_cpuid(0x80000000, regs);
1402                 if (regs[0] >= 0x80000000)
1403                         cpu_exthigh = regs[0];
1404         }
1405 #else
1406         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1407             cpu_vendor_id == CPU_VENDOR_AMD ||
1408             cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1409                 do_cpuid(0x80000000, regs);
1410                 cpu_exthigh = regs[0];
1411         }
1412 #endif
1413         if (cpu_exthigh >= 0x80000001) {
1414                 do_cpuid(0x80000001, regs);
1415                 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1416                 amd_feature2 = regs[2];
1417         }
1418         if (cpu_exthigh >= 0x80000007) {
1419                 do_cpuid(0x80000007, regs);
1420                 amd_pminfo = regs[3];
1421         }
1422         if (cpu_exthigh >= 0x80000008) {
1423                 do_cpuid(0x80000008, regs);
1424                 cpu_maxphyaddr = regs[0] & 0xff;
1425                 cpu_procinfo2 = regs[2];
1426         } else {
1427                 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1428         }
1429
1430 #ifdef __i386__
1431         if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1432                 if (cpu == CPU_486) {
1433                         /*
1434                          * These conditions are equivalent to:
1435                          *     - CPU does not support cpuid instruction.
1436                          *     - Cyrix/IBM CPU is detected.
1437                          */
1438                         if (identblue() == IDENTBLUE_IBMCPU) {
1439                                 strcpy(cpu_vendor, "IBM");
1440                                 cpu_vendor_id = CPU_VENDOR_IBM;
1441                                 cpu = CPU_BLUE;
1442                                 return;
1443                         }
1444                 }
1445                 switch (cpu_id & 0xf00) {
1446                 case 0x600:
1447                         /*
1448                          * Cyrix's datasheet does not describe DIRs.
1449                          * Therefor, I assume it does not have them
1450                          * and use the result of the cpuid instruction.
1451                          * XXX they seem to have it for now at least. -Peter
1452                          */
1453                         identifycyrix();
1454                         cpu = CPU_M2;
1455                         break;
1456                 default:
1457                         identifycyrix();
1458                         /*
1459                          * This routine contains a trick.
1460                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1461                          */
1462                         switch (cyrix_did & 0x00f0) {
1463                         case 0x00:
1464                         case 0xf0:
1465                                 cpu = CPU_486DLC;
1466                                 break;
1467                         case 0x10:
1468                                 cpu = CPU_CY486DX;
1469                                 break;
1470                         case 0x20:
1471                                 if ((cyrix_did & 0x000f) < 8)
1472                                         cpu = CPU_M1;
1473                                 else
1474                                         cpu = CPU_M1SC;
1475                                 break;
1476                         case 0x30:
1477                                 cpu = CPU_M1;
1478                                 break;
1479                         case 0x40:
1480                                 /* MediaGX CPU */
1481                                 cpu = CPU_M1SC;
1482                                 break;
1483                         default:
1484                                 /* M2 and later CPUs are treated as M2. */
1485                                 cpu = CPU_M2;
1486
1487                                 /*
1488                                  * enable cpuid instruction.
1489                                  */
1490                                 ccr3 = read_cyrix_reg(CCR3);
1491                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1492                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1493                                 write_cyrix_reg(CCR3, ccr3);
1494
1495                                 do_cpuid(0, regs);
1496                                 cpu_high = regs[0];     /* eax */
1497                                 do_cpuid(1, regs);
1498                                 cpu_id = regs[0];       /* eax */
1499                                 cpu_feature = regs[3];  /* edx */
1500                                 break;
1501                         }
1502                 }
1503         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1504                 /*
1505                  * There are BlueLightning CPUs that do not change
1506                  * undefined flags by dividing 5 by 2.  In this case,
1507                  * the CPU identification routine in locore.s leaves
1508                  * cpu_vendor null string and puts CPU_486 into the
1509                  * cpu.
1510                  */
1511                 if (identblue() == IDENTBLUE_IBMCPU) {
1512                         strcpy(cpu_vendor, "IBM");
1513                         cpu_vendor_id = CPU_VENDOR_IBM;
1514                         cpu = CPU_BLUE;
1515                         return;
1516                 }
1517         }
1518 #else
1519         /* XXX */
1520         cpu = CPU_CLAWHAMMER;
1521 #endif
1522 }
1523
1524 static u_int
1525 find_cpu_vendor_id(void)
1526 {
1527         int     i;
1528
1529         for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++)
1530                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1531                         return (cpu_vendors[i].vendor_id);
1532         return (0);
1533 }
1534
1535 static void
1536 print_AMD_assoc(int i)
1537 {
1538         if (i == 255)
1539                 printf(", fully associative\n");
1540         else
1541                 printf(", %d-way associative\n", i);
1542 }
1543
1544 static void
1545 print_AMD_l2_assoc(int i)
1546 {
1547         switch (i & 0x0f) {
1548         case 0: printf(", disabled/not present\n"); break;
1549         case 1: printf(", direct mapped\n"); break;
1550         case 2: printf(", 2-way associative\n"); break;
1551         case 4: printf(", 4-way associative\n"); break;
1552         case 6: printf(", 8-way associative\n"); break;
1553         case 8: printf(", 16-way associative\n"); break;
1554         case 15: printf(", fully associative\n"); break;
1555         default: printf(", reserved configuration\n"); break;
1556         }
1557 }
1558
1559 static void
1560 print_AMD_info(void)
1561 {
1562 #ifdef __i386__
1563         uint64_t amd_whcr;
1564 #endif
1565         u_int regs[4];
1566
1567         if (cpu_exthigh >= 0x80000005) {
1568                 do_cpuid(0x80000005, regs);
1569                 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1570                 print_AMD_assoc(regs[0] >> 24);
1571
1572                 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1573                 print_AMD_assoc((regs[0] >> 8) & 0xff);
1574
1575                 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1576                 print_AMD_assoc(regs[1] >> 24);
1577
1578                 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1579                 print_AMD_assoc((regs[1] >> 8) & 0xff);
1580
1581                 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1582                 printf(", %d bytes/line", regs[2] & 0xff);
1583                 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1584                 print_AMD_assoc((regs[2] >> 16) & 0xff);
1585
1586                 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1587                 printf(", %d bytes/line", regs[3] & 0xff);
1588                 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1589                 print_AMD_assoc((regs[3] >> 16) & 0xff);
1590         }
1591
1592         if (cpu_exthigh >= 0x80000006) {
1593                 do_cpuid(0x80000006, regs);
1594                 if ((regs[0] >> 16) != 0) {
1595                         printf("L2 2MB data TLB: %d entries",
1596                             (regs[0] >> 16) & 0xfff);
1597                         print_AMD_l2_assoc(regs[0] >> 28);
1598                         printf("L2 2MB instruction TLB: %d entries",
1599                             regs[0] & 0xfff);
1600                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1601                 } else {
1602                         printf("L2 2MB unified TLB: %d entries",
1603                             regs[0] & 0xfff);
1604                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1605                 }
1606                 if ((regs[1] >> 16) != 0) {
1607                         printf("L2 4KB data TLB: %d entries",
1608                             (regs[1] >> 16) & 0xfff);
1609                         print_AMD_l2_assoc(regs[1] >> 28);
1610
1611                         printf("L2 4KB instruction TLB: %d entries",
1612                             (regs[1] >> 16) & 0xfff);
1613                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1614                 } else {
1615                         printf("L2 4KB unified TLB: %d entries",
1616                             (regs[1] >> 16) & 0xfff);
1617                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1618                 }
1619                 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1620                 printf(", %d bytes/line", regs[2] & 0xff);
1621                 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1622                 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1623         }
1624
1625 #ifdef __i386__
1626         if (((cpu_id & 0xf00) == 0x500)
1627             && (((cpu_id & 0x0f0) > 0x80)
1628                 || (((cpu_id & 0x0f0) == 0x80)
1629                     && (cpu_id & 0x00f) > 0x07))) {
1630                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1631                 amd_whcr = rdmsr(0xc0000082);
1632                 if (!(amd_whcr & (0x3ff << 22))) {
1633                         printf("Write Allocate Disable\n");
1634                 } else {
1635                         printf("Write Allocate Enable Limit: %dM bytes\n",
1636                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1637                         printf("Write Allocate 15-16M bytes: %s\n",
1638                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1639                 }
1640         } else if (((cpu_id & 0xf00) == 0x500)
1641                    && ((cpu_id & 0x0f0) > 0x50)) {
1642                 /* K6, K6-2(old core) */
1643                 amd_whcr = rdmsr(0xc0000082);
1644                 if (!(amd_whcr & (0x7f << 1))) {
1645                         printf("Write Allocate Disable\n");
1646                 } else {
1647                         printf("Write Allocate Enable Limit: %dM bytes\n",
1648                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1649                         printf("Write Allocate 15-16M bytes: %s\n",
1650                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
1651                         printf("Hardware Write Allocate Control: %s\n",
1652                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
1653                 }
1654         }
1655 #endif
1656         /*
1657          * Opteron Rev E shows a bug as in very rare occasions a read memory
1658          * barrier is not performed as expected if it is followed by a
1659          * non-atomic read-modify-write instruction.
1660          * As long as that bug pops up very rarely (intensive machine usage
1661          * on other operating systems generally generates one unexplainable
1662          * crash any 2 months) and as long as a model specific fix would be
1663          * impratical at this stage, print out a warning string if the broken
1664          * model and family are identified.
1665          */
1666         if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1667             CPUID_TO_MODEL(cpu_id) <= 0x3f)
1668                 printf("WARNING: This architecture revision has known SMP "
1669                     "hardware bugs which may cause random instability\n");
1670 }
1671
1672 static void
1673 print_INTEL_info(void)
1674 {
1675         u_int regs[4];
1676         u_int rounds, regnum;
1677         u_int nwaycode, nway;
1678
1679         if (cpu_high >= 2) {
1680                 rounds = 0;
1681                 do {
1682                         do_cpuid(0x2, regs);
1683                         if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1684                                 break;  /* we have a buggy CPU */
1685
1686                         for (regnum = 0; regnum <= 3; ++regnum) {
1687                                 if (regs[regnum] & (1<<31))
1688                                         continue;
1689                                 if (regnum != 0)
1690                                         print_INTEL_TLB(regs[regnum] & 0xff);
1691                                 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1692                                 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1693                                 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1694                         }
1695                 } while (--rounds > 0);
1696         }
1697
1698         if (cpu_exthigh >= 0x80000006) {
1699                 do_cpuid(0x80000006, regs);
1700                 nwaycode = (regs[2] >> 12) & 0x0f;
1701                 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1702                         nway = 1 << (nwaycode / 2);
1703                 else
1704                         nway = 0;
1705                 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1706                     (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1707         }
1708 }
1709
1710 static void
1711 print_INTEL_TLB(u_int data)
1712 {
1713         switch (data) {
1714         case 0x0:
1715         case 0x40:
1716         default:
1717                 break;
1718         case 0x1:
1719                 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1720                 break;
1721         case 0x2:
1722                 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1723                 break;
1724         case 0x3:
1725                 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1726                 break;
1727         case 0x4:
1728                 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1729                 break;
1730         case 0x6:
1731                 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1732                 break;
1733         case 0x8:
1734                 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
1735                 break;
1736         case 0x9:
1737                 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
1738                 break;
1739         case 0xa:
1740                 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
1741                 break;
1742         case 0xb:
1743                 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
1744                 break;
1745         case 0xc:
1746                 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
1747                 break;
1748         case 0xd:
1749                 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
1750                 break;
1751         case 0xe:
1752                 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
1753                 break;
1754         case 0x1d:
1755                 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
1756                 break;
1757         case 0x21:
1758                 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
1759                 break;
1760         case 0x22:
1761                 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1762                 break;
1763         case 0x23:
1764                 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1765                 break;
1766         case 0x24:
1767                 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
1768                 break;
1769         case 0x25:
1770                 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1771                 break;
1772         case 0x29:
1773                 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1774                 break;
1775         case 0x2c:
1776                 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
1777                 break;
1778         case 0x30:
1779                 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
1780                 break;
1781         case 0x39: /* De-listed in SDM rev. 54 */
1782                 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1783                 break;
1784         case 0x3b: /* De-listed in SDM rev. 54 */
1785                 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
1786                 break;
1787         case 0x3c: /* De-listed in SDM rev. 54 */
1788                 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1789                 break;
1790         case 0x41:
1791                 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
1792                 break;
1793         case 0x42:
1794                 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
1795                 break;
1796         case 0x43:
1797                 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
1798                 break;
1799         case 0x44:
1800                 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
1801                 break;
1802         case 0x45:
1803                 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
1804                 break;
1805         case 0x46:
1806                 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
1807                 break;
1808         case 0x47:
1809                 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
1810                 break;
1811         case 0x48:
1812                 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
1813                 break;
1814         case 0x49:
1815                 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
1816                     CPUID_TO_MODEL(cpu_id) == 0x6)
1817                         printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
1818                 else
1819                         printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
1820                 break;
1821         case 0x4a:
1822                 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
1823                 break;
1824         case 0x4b:
1825                 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
1826                 break;
1827         case 0x4c:
1828                 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
1829                 break;
1830         case 0x4d:
1831                 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
1832                 break;
1833         case 0x4e:
1834                 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
1835                 break;
1836         case 0x4f:
1837                 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
1838                 break;
1839         case 0x50:
1840                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
1841                 break;
1842         case 0x51:
1843                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
1844                 break;
1845         case 0x52:
1846                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
1847                 break;
1848         case 0x55:
1849                 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
1850                 break;
1851         case 0x56:
1852                 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
1853                 break;
1854         case 0x57:
1855                 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
1856                 break;
1857         case 0x59:
1858                 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
1859                 break;
1860         case 0x5a:
1861                 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
1862                 break;
1863         case 0x5b:
1864                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
1865                 break;
1866         case 0x5c:
1867                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
1868                 break;
1869         case 0x5d:
1870                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
1871                 break;
1872         case 0x60:
1873                 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1874                 break;
1875         case 0x61:
1876                 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
1877                 break;
1878         case 0x63:
1879                 printf("Data TLB: 1 GByte pages, 4-way set associative, 4 entries\n");
1880                 break;
1881         case 0x66:
1882                 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1883                 break;
1884         case 0x67:
1885                 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1886                 break;
1887         case 0x68:
1888                 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
1889                 break;
1890         case 0x70:
1891                 printf("Trace cache: 12K-uops, 8-way set associative\n");
1892                 break;
1893         case 0x71:
1894                 printf("Trace cache: 16K-uops, 8-way set associative\n");
1895                 break;
1896         case 0x72:
1897                 printf("Trace cache: 32K-uops, 8-way set associative\n");
1898                 break;
1899         case 0x76:
1900                 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
1901                 break;
1902         case 0x78:
1903                 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
1904                 break;
1905         case 0x79:
1906                 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1907                 break;
1908         case 0x7a:
1909                 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1910                 break;
1911         case 0x7b:
1912                 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1913                 break;
1914         case 0x7c:
1915                 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1916                 break;
1917         case 0x7d:
1918                 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
1919                 break;
1920         case 0x7f:
1921                 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
1922                 break;
1923         case 0x80:
1924                 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
1925                 break;
1926         case 0x82:
1927                 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
1928                 break;
1929         case 0x83:
1930                 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
1931                 break;
1932         case 0x84:
1933                 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
1934                 break;
1935         case 0x85:
1936                 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
1937                 break;
1938         case 0x86:
1939                 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
1940                 break;
1941         case 0x87:
1942                 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
1943                 break;
1944         case 0xa0:
1945                 printf("DTLB: 4k pages, fully associative, 32 entries\n");
1946                 break;
1947         case 0xb0:
1948                 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
1949                 break;
1950         case 0xb1:
1951                 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
1952                 break;
1953         case 0xb2:
1954                 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
1955                 break;
1956         case 0xb3:
1957                 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
1958                 break;
1959         case 0xb4:
1960                 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
1961                 break;
1962         case 0xb5:
1963                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
1964                 break;
1965         case 0xb6:
1966                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
1967                 break;
1968         case 0xba:
1969                 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
1970                 break;
1971         case 0xc0:
1972                 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
1973                 break;
1974         case 0xc1:
1975                 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
1976                 break;
1977         case 0xc2:
1978                 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
1979                 break;
1980         case 0xc3:
1981                 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
1982                 break;
1983         case 0xca:
1984                 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
1985                 break;
1986         case 0xd0:
1987                 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
1988                 break;
1989         case 0xd1:
1990                 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
1991                 break;
1992         case 0xd2:
1993                 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
1994                 break;
1995         case 0xd6:
1996                 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
1997                 break;
1998         case 0xd7:
1999                 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2000                 break;
2001         case 0xd8:
2002                 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2003                 break;
2004         case 0xdc:
2005                 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2006                 break;
2007         case 0xdd:
2008                 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2009                 break;
2010         case 0xde:
2011                 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2012                 break;
2013         case 0xe2:
2014                 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2015                 break;
2016         case 0xe3:
2017                 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2018                 break;
2019         case 0xe4:
2020                 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2021                 break;
2022         case 0xea:
2023                 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2024                 break;
2025         case 0xeb:
2026                 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2027                 break;
2028         case 0xec:
2029                 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2030                 break;
2031         case 0xf0:
2032                 printf("64-Byte prefetching\n");
2033                 break;
2034         case 0xf1:
2035                 printf("128-Byte prefetching\n");
2036                 break;
2037         }
2038 }
2039
2040 static void
2041 print_svm_info(void)
2042 {
2043         u_int features, regs[4];
2044         uint64_t msr;
2045         int comma;
2046
2047         printf("\n  SVM: ");
2048         do_cpuid(0x8000000A, regs);
2049         features = regs[3];
2050
2051         msr = rdmsr(MSR_VM_CR);
2052         if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2053                 printf("(disabled in BIOS) ");
2054
2055         if (!bootverbose) {
2056                 comma = 0;
2057                 if (features & (1 << 0)) {
2058                         printf("%sNP", comma ? "," : "");
2059                         comma = 1;
2060                 }
2061                 if (features & (1 << 3)) {
2062                         printf("%sNRIP", comma ? "," : "");
2063                         comma = 1;
2064                 }
2065                 if (features & (1 << 5)) {
2066                         printf("%sVClean", comma ? "," : "");
2067                         comma = 1;
2068                 }
2069                 if (features & (1 << 6)) {
2070                         printf("%sAFlush", comma ? "," : "");
2071                         comma = 1;
2072                 }
2073                 if (features & (1 << 7)) {
2074                         printf("%sDAssist", comma ? "," : "");
2075                         comma = 1;
2076                 }
2077                 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2078                 return;
2079         }
2080
2081         printf("Features=0x%b", features,
2082                "\020"
2083                "\001NP"                 /* Nested paging */
2084                "\002LbrVirt"            /* LBR virtualization */
2085                "\003SVML"               /* SVM lock */
2086                "\004NRIPS"              /* NRIP save */
2087                "\005TscRateMsr"         /* MSR based TSC rate control */
2088                "\006VmcbClean"          /* VMCB clean bits */
2089                "\007FlushByAsid"        /* Flush by ASID */
2090                "\010DecodeAssist"       /* Decode assist */
2091                "\011<b8>"
2092                "\012<b9>"
2093                "\013PauseFilter"        /* PAUSE intercept filter */
2094                "\014<b11>"
2095                "\015PauseFilterThreshold" /* PAUSE filter threshold */
2096                "\016AVIC"               /* virtual interrupt controller */
2097                 );
2098         printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2099 }
2100
2101 #ifdef __i386__
2102 static void
2103 print_transmeta_info(void)
2104 {
2105         u_int regs[4], nreg = 0;
2106
2107         do_cpuid(0x80860000, regs);
2108         nreg = regs[0];
2109         if (nreg >= 0x80860001) {
2110                 do_cpuid(0x80860001, regs);
2111                 printf("  Processor revision %u.%u.%u.%u\n",
2112                        (regs[1] >> 24) & 0xff,
2113                        (regs[1] >> 16) & 0xff,
2114                        (regs[1] >> 8) & 0xff,
2115                        regs[1] & 0xff);
2116         }
2117         if (nreg >= 0x80860002) {
2118                 do_cpuid(0x80860002, regs);
2119                 printf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
2120                        (regs[1] >> 24) & 0xff,
2121                        (regs[1] >> 16) & 0xff,
2122                        (regs[1] >> 8) & 0xff,
2123                        regs[1] & 0xff,
2124                        regs[2]);
2125         }
2126         if (nreg >= 0x80860006) {
2127                 char info[65];
2128                 do_cpuid(0x80860003, (u_int*) &info[0]);
2129                 do_cpuid(0x80860004, (u_int*) &info[16]);
2130                 do_cpuid(0x80860005, (u_int*) &info[32]);
2131                 do_cpuid(0x80860006, (u_int*) &info[48]);
2132                 info[64] = 0;
2133                 printf("  %s\n", info);
2134         }
2135 }
2136 #endif
2137
2138 static void
2139 print_via_padlock_info(void)
2140 {
2141         u_int regs[4];
2142
2143         do_cpuid(0xc0000001, regs);
2144         printf("\n  VIA Padlock Features=0x%b", regs[3],
2145         "\020"
2146         "\003RNG"               /* RNG */
2147         "\007AES"               /* ACE */
2148         "\011AES-CTR"           /* ACE2 */
2149         "\013SHA1,SHA256"       /* PHE */
2150         "\015RSA"               /* PMM */
2151         );
2152 }
2153
2154 static uint32_t
2155 vmx_settable(uint64_t basic, int msr, int true_msr)
2156 {
2157         uint64_t val;
2158
2159         if (basic & (1ULL << 55))
2160                 val = rdmsr(true_msr);
2161         else
2162                 val = rdmsr(msr);
2163
2164         /* Just report the controls that can be set to 1. */
2165         return (val >> 32);
2166 }
2167
2168 static void
2169 print_vmx_info(void)
2170 {
2171         uint64_t basic, msr;
2172         uint32_t entry, exit, mask, pin, proc, proc2;
2173         int comma;
2174
2175         printf("\n  VT-x: ");
2176         msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2177         if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2178                 printf("(disabled in BIOS) ");
2179         basic = rdmsr(MSR_VMX_BASIC);
2180         pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2181             MSR_VMX_TRUE_PINBASED_CTLS);
2182         proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2183             MSR_VMX_TRUE_PROCBASED_CTLS);
2184         if (proc & PROCBASED_SECONDARY_CONTROLS)
2185                 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2186                     MSR_VMX_PROCBASED_CTLS2);
2187         else
2188                 proc2 = 0;
2189         exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2190         entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2191
2192         if (!bootverbose) {
2193                 comma = 0;
2194                 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2195                     entry & VM_ENTRY_LOAD_PAT) {
2196                         printf("%sPAT", comma ? "," : "");
2197                         comma = 1;
2198                 }
2199                 if (proc & PROCBASED_HLT_EXITING) {
2200                         printf("%sHLT", comma ? "," : "");
2201                         comma = 1;
2202                 }
2203                 if (proc & PROCBASED_MTF) {
2204                         printf("%sMTF", comma ? "," : "");
2205                         comma = 1;
2206                 }
2207                 if (proc & PROCBASED_PAUSE_EXITING) {
2208                         printf("%sPAUSE", comma ? "," : "");
2209                         comma = 1;
2210                 }
2211                 if (proc2 & PROCBASED2_ENABLE_EPT) {
2212                         printf("%sEPT", comma ? "," : "");
2213                         comma = 1;
2214                 }
2215                 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2216                         printf("%sUG", comma ? "," : "");
2217                         comma = 1;
2218                 }
2219                 if (proc2 & PROCBASED2_ENABLE_VPID) {
2220                         printf("%sVPID", comma ? "," : "");
2221                         comma = 1;
2222                 }
2223                 if (proc & PROCBASED_USE_TPR_SHADOW &&
2224                     proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2225                     proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2226                     proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2227                     proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2228                         printf("%sVID", comma ? "," : "");
2229                         comma = 1;
2230                         if (pin & PINBASED_POSTED_INTERRUPT)
2231                                 printf(",PostIntr");
2232                 }
2233                 return;
2234         }
2235
2236         mask = basic >> 32;
2237         printf("Basic Features=0x%b", mask,
2238         "\020"
2239         "\02132PA"              /* 32-bit physical addresses */
2240         "\022SMM"               /* SMM dual-monitor */
2241         "\027INS/OUTS"          /* VM-exit info for INS and OUTS */
2242         "\030TRUE"              /* TRUE_CTLS MSRs */
2243         );
2244         printf("\n        Pin-Based Controls=0x%b", pin,
2245         "\020"
2246         "\001ExtINT"            /* External-interrupt exiting */
2247         "\004NMI"               /* NMI exiting */
2248         "\006VNMI"              /* Virtual NMIs */
2249         "\007PreTmr"            /* Activate VMX-preemption timer */
2250         "\010PostIntr"          /* Process posted interrupts */
2251         );
2252         printf("\n        Primary Processor Controls=0x%b", proc,
2253         "\020"
2254         "\003INTWIN"            /* Interrupt-window exiting */
2255         "\004TSCOff"            /* Use TSC offsetting */
2256         "\010HLT"               /* HLT exiting */
2257         "\012INVLPG"            /* INVLPG exiting */
2258         "\013MWAIT"             /* MWAIT exiting */
2259         "\014RDPMC"             /* RDPMC exiting */
2260         "\015RDTSC"             /* RDTSC exiting */
2261         "\020CR3-LD"            /* CR3-load exiting */
2262         "\021CR3-ST"            /* CR3-store exiting */
2263         "\024CR8-LD"            /* CR8-load exiting */
2264         "\025CR8-ST"            /* CR8-store exiting */
2265         "\026TPR"               /* Use TPR shadow */
2266         "\027NMIWIN"            /* NMI-window exiting */
2267         "\030MOV-DR"            /* MOV-DR exiting */
2268         "\031IO"                /* Unconditional I/O exiting */
2269         "\032IOmap"             /* Use I/O bitmaps */
2270         "\034MTF"               /* Monitor trap flag */
2271         "\035MSRmap"            /* Use MSR bitmaps */
2272         "\036MONITOR"           /* MONITOR exiting */
2273         "\037PAUSE"             /* PAUSE exiting */
2274         );
2275         if (proc & PROCBASED_SECONDARY_CONTROLS)
2276                 printf("\n        Secondary Processor Controls=0x%b", proc2,
2277                 "\020"
2278                 "\001APIC"              /* Virtualize APIC accesses */
2279                 "\002EPT"               /* Enable EPT */
2280                 "\003DT"                /* Descriptor-table exiting */
2281                 "\004RDTSCP"            /* Enable RDTSCP */
2282                 "\005x2APIC"            /* Virtualize x2APIC mode */
2283                 "\006VPID"              /* Enable VPID */
2284                 "\007WBINVD"            /* WBINVD exiting */
2285                 "\010UG"                /* Unrestricted guest */
2286                 "\011APIC-reg"          /* APIC-register virtualization */
2287                 "\012VID"               /* Virtual-interrupt delivery */
2288                 "\013PAUSE-loop"        /* PAUSE-loop exiting */
2289                 "\014RDRAND"            /* RDRAND exiting */
2290                 "\015INVPCID"           /* Enable INVPCID */
2291                 "\016VMFUNC"            /* Enable VM functions */
2292                 "\017VMCS"              /* VMCS shadowing */
2293                 "\020EPT#VE"            /* EPT-violation #VE */
2294                 "\021XSAVES"            /* Enable XSAVES/XRSTORS */
2295                 );
2296         printf("\n        Exit Controls=0x%b", mask,
2297         "\020"
2298         "\003DR"                /* Save debug controls */
2299                                 /* Ignore Host address-space size */
2300         "\015PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2301         "\020AckInt"            /* Acknowledge interrupt on exit */
2302         "\023PAT-SV"            /* Save MSR_PAT */
2303         "\024PAT-LD"            /* Load MSR_PAT */
2304         "\025EFER-SV"           /* Save MSR_EFER */
2305         "\026EFER-LD"           /* Load MSR_EFER */
2306         "\027PTMR-SV"           /* Save VMX-preemption timer value */
2307         );
2308         printf("\n        Entry Controls=0x%b", mask,
2309         "\020"
2310         "\003DR"                /* Save debug controls */
2311                                 /* Ignore IA-32e mode guest */
2312                                 /* Ignore Entry to SMM */
2313                                 /* Ignore Deactivate dual-monitor treatment */
2314         "\016PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2315         "\017PAT"               /* Load MSR_PAT */
2316         "\020EFER"              /* Load MSR_EFER */
2317         );
2318         if (proc & PROCBASED_SECONDARY_CONTROLS &&
2319             (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2320                 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2321                 mask = msr;
2322                 printf("\n        EPT Features=0x%b", mask,
2323                 "\020"
2324                 "\001XO"                /* Execute-only translations */
2325                 "\007PW4"               /* Page-walk length of 4 */
2326                 "\011UC"                /* EPT paging-structure mem can be UC */
2327                 "\017WB"                /* EPT paging-structure mem can be WB */
2328                 "\0212M"                /* EPT PDE can map a 2-Mbyte page */
2329                 "\0221G"                /* EPT PDPTE can map a 1-Gbyte page */
2330                 "\025INVEPT"            /* INVEPT is supported */
2331                 "\026AD"                /* Accessed and dirty flags for EPT */
2332                 "\032single"            /* INVEPT single-context type */
2333                 "\033all"               /* INVEPT all-context type */
2334                 );
2335                 mask = msr >> 32;
2336                 printf("\n        VPID Features=0x%b", mask,
2337                 "\020"
2338                 "\001INVVPID"           /* INVVPID is supported */
2339                 "\011individual"        /* INVVPID individual-address type */
2340                 "\012single"            /* INVVPID single-context type */
2341                 "\013all"               /* INVVPID all-context type */
2342                  /* INVVPID single-context-retaining-globals type */
2343                 "\014single-globals"
2344                 );
2345         }
2346 }
2347
2348 static void
2349 print_hypervisor_info(void)
2350 {
2351
2352         if (*hv_vendor)
2353                 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2354 }