sys/x86/x86/identcpu.c

   1 /*-
   2  * Copyright (c) 1992 Terrence R. Lambert.
   3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
   4  * Copyright (c) 1997 KATO Takenori.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * William Jolitz.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by the University of
  21  *      California, Berkeley and its contributors.
  22  * 4. Neither the name of the University nor the names of its contributors
  23  *    may be used to endorse or promote products derived from this software
  24  *    without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  36  * SUCH DAMAGE.
  37  *
  38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include "opt_cpu.h"
  45
  46 #include <sys/param.h>
  47 #include <sys/bus.h>
  48 #include <sys/cpu.h>
  49 #include <sys/eventhandler.h>
  50 #include <sys/limits.h>
  51 #include <sys/systm.h>
  52 #include <sys/kernel.h>
  53 #include <sys/sysctl.h>
  54 #include <sys/power.h>
  55
  56 #include <machine/asmacros.h>
  57 #include <machine/clock.h>
  58 #include <machine/cputypes.h>
  59 #include <machine/frame.h>
  60 #include <machine/intr_machdep.h>
  61 #include <machine/md_var.h>
  62 #include <machine/segments.h>
  63 #include <machine/specialreg.h>
  64
  65 #include <amd64/vmm/intel/vmx_controls.h>
  66 #include <x86/isa/icu.h>
  67 #include <x86/vmware.h>
  68
  69 #ifdef __i386__
  70 #define IDENTBLUE_CYRIX486      0
  71 #define IDENTBLUE_IBMCPU        1
  72 #define IDENTBLUE_CYRIXM2       2
  73
  74 static void identifycyrix(void);
  75 static void print_transmeta_info(void);
  76 #endif
  77 static u_int find_cpu_vendor_id(void);
  78 static void print_AMD_info(void);
  79 static void print_INTEL_info(void);
  80 static void print_INTEL_TLB(u_int data);
  81 static void print_hypervisor_info(void);
  82 static void print_svm_info(void);
  83 static void print_via_padlock_info(void);
  84 static void print_vmx_info(void);
  85
  86 int     cpu_class;
  87 char machine[] = MACHINE;
  88
  89 #ifdef __amd64__
  90 #ifdef SCTL_MASK32
  91 extern int adaptive_machine_arch;
  92 #endif
  93
  94 static int
  95 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
  96 {
  97 #ifdef SCTL_MASK32
  98         static const char machine32[] = "i386";
  99 #endif
 100         int error;
 101
 102 #ifdef SCTL_MASK32
 103         if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
 104                 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
 105         else
 106 #endif
 107                 error = SYSCTL_OUT(req, machine, sizeof(machine));
 108         return (error);
 109
 110 }
 111 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD,
 112     NULL, 0, sysctl_hw_machine, "A", "Machine class");
 113 #else
 114 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
 115     machine, 0, "Machine class");
 116 #endif
 117
 118 static char cpu_model[128];
 119 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
 120     cpu_model, 0, "Machine model");
 121
 122 static int hw_clockrate;
 123 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
 124     &hw_clockrate, 0, "CPU instruction clock rate");
 125
 126 u_int hv_high;
 127 char hv_vendor[16];
 128 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD, hv_vendor, 0,
 129     "Hypervisor vendor");
 130
 131 static eventhandler_tag tsc_post_tag;
 132
 133 static char cpu_brand[48];
 134
 135 #ifdef __i386__
 136 #define MAX_BRAND_INDEX 8
 137
 138 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
 139         NULL,                   /* No brand */
 140         "Intel Celeron",
 141         "Intel Pentium III",
 142         "Intel Pentium III Xeon",
 143         NULL,
 144         NULL,
 145         NULL,
 146         NULL,
 147         "Intel Pentium 4"
 148 };
 149 #endif
 150
 151 static struct {
 152         char    *cpu_name;
 153         int     cpu_class;
 154 } cpus[] = {
 155 #ifdef __i386__
 156         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
 157         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
 158         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
 159         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
 160         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
 161         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
 162         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
 163         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
 164         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
 165         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
 166         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
 167         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
 168         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
 169         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
 170         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
 171         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
 172         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
 173 #else
 174         { "Clawhammer",         CPUCLASS_K8 },          /* CPU_CLAWHAMMER */
 175         { "Sledgehammer",       CPUCLASS_K8 },          /* CPU_SLEDGEHAMMER */
 176 #endif
 177 };
 178
 179 static struct {
 180         char    *vendor;
 181         u_int   vendor_id;
 182 } cpu_vendors[] = {
 183         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
 184         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
 185         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
 186 #ifdef __i386__
 187         { NSC_VENDOR_ID,        CPU_VENDOR_NSC },       /* Geode by NSC */
 188         { CYRIX_VENDOR_ID,      CPU_VENDOR_CYRIX },     /* CyrixInstead */
 189         { TRANSMETA_VENDOR_ID,  CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
 190         { SIS_VENDOR_ID,        CPU_VENDOR_SIS },       /* SiS SiS SiS  */
 191         { UMC_VENDOR_ID,        CPU_VENDOR_UMC },       /* UMC UMC UMC  */
 192         { NEXGEN_VENDOR_ID,     CPU_VENDOR_NEXGEN },    /* NexGenDriven */
 193         { RISE_VENDOR_ID,       CPU_VENDOR_RISE },      /* RiseRiseRise */
 194 #if 0
 195         /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
 196         { "TransmetaCPU",       CPU_VENDOR_TRANSMETA },
 197 #endif
 198 #endif
 199 };
 200
 201 void
 202 printcpuinfo(void)
 203 {
 204         u_int regs[4], i;
 205         char *brand;
 206
 207         cpu_class = cpus[cpu].cpu_class;
 208         printf("CPU: ");
 209         strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
 210
 211         /* Check for extended CPUID information and a processor name. */
 212         if (cpu_exthigh >= 0x80000004) {
 213                 brand = cpu_brand;
 214                 for (i = 0x80000002; i < 0x80000005; i++) {
 215                         do_cpuid(i, regs);
 216                         memcpy(brand, regs, sizeof(regs));
 217                         brand += sizeof(regs);
 218                 }
 219         }
 220
 221         switch (cpu_vendor_id) {
 222         case CPU_VENDOR_INTEL:
 223 #ifdef __i386__
 224                 if ((cpu_id & 0xf00) > 0x300) {
 225                         u_int brand_index;
 226
 227                         cpu_model[0] = '\0';
 228
 229                         switch (cpu_id & 0x3000) {
 230                         case 0x1000:
 231                                 strcpy(cpu_model, "Overdrive ");
 232                                 break;
 233                         case 0x2000:
 234                                 strcpy(cpu_model, "Dual ");
 235                                 break;
 236                         }
 237
 238                         switch (cpu_id & 0xf00) {
 239                         case 0x400:
 240                                 strcat(cpu_model, "i486 ");
 241                                 /* Check the particular flavor of 486 */
 242                                 switch (cpu_id & 0xf0) {
 243                                 case 0x00:
 244                                 case 0x10:
 245                                         strcat(cpu_model, "DX");
 246                                         break;
 247                                 case 0x20:
 248                                         strcat(cpu_model, "SX");
 249                                         break;
 250                                 case 0x30:
 251                                         strcat(cpu_model, "DX2");
 252                                         break;
 253                                 case 0x40:
 254                                         strcat(cpu_model, "SL");
 255                                         break;
 256                                 case 0x50:
 257                                         strcat(cpu_model, "SX2");
 258                                         break;
 259                                 case 0x70:
 260                                         strcat(cpu_model,
 261                                             "DX2 Write-Back Enhanced");
 262                                         break;
 263                                 case 0x80:
 264                                         strcat(cpu_model, "DX4");
 265                                         break;
 266                                 }
 267                                 break;
 268                         case 0x500:
 269                                 /* Check the particular flavor of 586 */
 270                                 strcat(cpu_model, "Pentium");
 271                                 switch (cpu_id & 0xf0) {
 272                                 case 0x00:
 273                                         strcat(cpu_model, " A-step");
 274                                         break;
 275                                 case 0x10:
 276                                         strcat(cpu_model, "/P5");
 277                                         break;
 278                                 case 0x20:
 279                                         strcat(cpu_model, "/P54C");
 280                                         break;
 281                                 case 0x30:
 282                                         strcat(cpu_model, "/P24T");
 283                                         break;
 284                                 case 0x40:
 285                                         strcat(cpu_model, "/P55C");
 286                                         break;
 287                                 case 0x70:
 288                                         strcat(cpu_model, "/P54C");
 289                                         break;
 290                                 case 0x80:
 291                                         strcat(cpu_model, "/P55C (quarter-micron)");
 292                                         break;
 293                                 default:
 294                                         /* nothing */
 295                                         break;
 296                                 }
 297 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 298                                 /*
 299                                  * XXX - If/when Intel fixes the bug, this
 300                                  * should also check the version of the
 301                                  * CPU, not just that it's a Pentium.
 302                                  */
 303                                 has_f00f_bug = 1;
 304 #endif
 305                                 break;
 306                         case 0x600:
 307                                 /* Check the particular flavor of 686 */
 308                                 switch (cpu_id & 0xf0) {
 309                                 case 0x00:
 310                                         strcat(cpu_model, "Pentium Pro A-step");
 311                                         break;
 312                                 case 0x10:
 313                                         strcat(cpu_model, "Pentium Pro");
 314                                         break;
 315                                 case 0x30:
 316                                 case 0x50:
 317                                 case 0x60:
 318                                         strcat(cpu_model,
 319                                 "Pentium II/Pentium II Xeon/Celeron");
 320                                         cpu = CPU_PII;
 321                                         break;
 322                                 case 0x70:
 323                                 case 0x80:
 324                                 case 0xa0:
 325                                 case 0xb0:
 326                                         strcat(cpu_model,
 327                                         "Pentium III/Pentium III Xeon/Celeron");
 328                                         cpu = CPU_PIII;
 329                                         break;
 330                                 default:
 331                                         strcat(cpu_model, "Unknown 80686");
 332                                         break;
 333                                 }
 334                                 break;
 335                         case 0xf00:
 336                                 strcat(cpu_model, "Pentium 4");
 337                                 cpu = CPU_P4;
 338                                 break;
 339                         default:
 340                                 strcat(cpu_model, "unknown");
 341                                 break;
 342                         }
 343
 344                         /*
 345                          * If we didn't get a brand name from the extended
 346                          * CPUID, try to look it up in the brand table.
 347                          */
 348                         if (cpu_high > 0 && *cpu_brand == '\0') {
 349                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
 350                                 if (brand_index <= MAX_BRAND_INDEX &&
 351                                     cpu_brandtable[brand_index] != NULL)
 352                                         strcpy(cpu_brand,
 353                                             cpu_brandtable[brand_index]);
 354                         }
 355                 }
 356 #else
 357                 /* Please make up your mind folks! */
 358                 strcat(cpu_model, "EM64T");
 359 #endif
 360                 break;
 361         case CPU_VENDOR_AMD:
 362                 /*
 363                  * Values taken from AMD Processor Recognition
 364                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
 365                  * (also describes ``Features'' encodings.
 366                  */
 367                 strcpy(cpu_model, "AMD ");
 368 #ifdef __i386__
 369                 switch (cpu_id & 0xFF0) {
 370                 case 0x410:
 371                         strcat(cpu_model, "Standard Am486DX");
 372                         break;
 373                 case 0x430:
 374                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
 375                         break;
 376                 case 0x470:
 377                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
 378                         break;
 379                 case 0x480:
 380                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
 381                         break;
 382                 case 0x490:
 383                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
 384                         break;
 385                 case 0x4E0:
 386                         strcat(cpu_model, "Am5x86 Write-Through");
 387                         break;
 388                 case 0x4F0:
 389                         strcat(cpu_model, "Am5x86 Write-Back");
 390                         break;
 391                 case 0x500:
 392                         strcat(cpu_model, "K5 model 0");
 393                         break;
 394                 case 0x510:
 395                         strcat(cpu_model, "K5 model 1");
 396                         break;
 397                 case 0x520:
 398                         strcat(cpu_model, "K5 PR166 (model 2)");
 399                         break;
 400                 case 0x530:
 401                         strcat(cpu_model, "K5 PR200 (model 3)");
 402                         break;
 403                 case 0x560:
 404                         strcat(cpu_model, "K6");
 405                         break;
 406                 case 0x570:
 407                         strcat(cpu_model, "K6 266 (model 1)");
 408                         break;
 409                 case 0x580:
 410                         strcat(cpu_model, "K6-2");
 411                         break;
 412                 case 0x590:
 413                         strcat(cpu_model, "K6-III");
 414                         break;
 415                 case 0x5a0:
 416                         strcat(cpu_model, "Geode LX");
 417                         break;
 418                 default:
 419                         strcat(cpu_model, "Unknown");
 420                         break;
 421                 }
 422 #else
 423                 if ((cpu_id & 0xf00) == 0xf00)
 424                         strcat(cpu_model, "AMD64 Processor");
 425                 else
 426                         strcat(cpu_model, "Unknown");
 427 #endif
 428                 break;
 429 #ifdef __i386__
 430         case CPU_VENDOR_CYRIX:
 431                 strcpy(cpu_model, "Cyrix ");
 432                 switch (cpu_id & 0xff0) {
 433                 case 0x440:
 434                         strcat(cpu_model, "MediaGX");
 435                         break;
 436                 case 0x520:
 437                         strcat(cpu_model, "6x86");
 438                         break;
 439                 case 0x540:
 440                         cpu_class = CPUCLASS_586;
 441                         strcat(cpu_model, "GXm");
 442                         break;
 443                 case 0x600:
 444                         strcat(cpu_model, "6x86MX");
 445                         break;
 446                 default:
 447                         /*
 448                          * Even though CPU supports the cpuid
 449                          * instruction, it can be disabled.
 450                          * Therefore, this routine supports all Cyrix
 451                          * CPUs.
 452                          */
 453                         switch (cyrix_did & 0xf0) {
 454                         case 0x00:
 455                                 switch (cyrix_did & 0x0f) {
 456                                 case 0x00:
 457                                         strcat(cpu_model, "486SLC");
 458                                         break;
 459                                 case 0x01:
 460                                         strcat(cpu_model, "486DLC");
 461                                         break;
 462                                 case 0x02:
 463                                         strcat(cpu_model, "486SLC2");
 464                                         break;
 465                                 case 0x03:
 466                                         strcat(cpu_model, "486DLC2");
 467                                         break;
 468                                 case 0x04:
 469                                         strcat(cpu_model, "486SRx");
 470                                         break;
 471                                 case 0x05:
 472                                         strcat(cpu_model, "486DRx");
 473                                         break;
 474                                 case 0x06:
 475                                         strcat(cpu_model, "486SRx2");
 476                                         break;
 477                                 case 0x07:
 478                                         strcat(cpu_model, "486DRx2");
 479                                         break;
 480                                 case 0x08:
 481                                         strcat(cpu_model, "486SRu");
 482                                         break;
 483                                 case 0x09:
 484                                         strcat(cpu_model, "486DRu");
 485                                         break;
 486                                 case 0x0a:
 487                                         strcat(cpu_model, "486SRu2");
 488                                         break;
 489                                 case 0x0b:
 490                                         strcat(cpu_model, "486DRu2");
 491                                         break;
 492                                 default:
 493                                         strcat(cpu_model, "Unknown");
 494                                         break;
 495                                 }
 496                                 break;
 497                         case 0x10:
 498                                 switch (cyrix_did & 0x0f) {
 499                                 case 0x00:
 500                                         strcat(cpu_model, "486S");
 501                                         break;
 502                                 case 0x01:
 503                                         strcat(cpu_model, "486S2");
 504                                         break;
 505                                 case 0x02:
 506                                         strcat(cpu_model, "486Se");
 507                                         break;
 508                                 case 0x03:
 509                                         strcat(cpu_model, "486S2e");
 510                                         break;
 511                                 case 0x0a:
 512                                         strcat(cpu_model, "486DX");
 513                                         break;
 514                                 case 0x0b:
 515                                         strcat(cpu_model, "486DX2");
 516                                         break;
 517                                 case 0x0f:
 518                                         strcat(cpu_model, "486DX4");
 519                                         break;
 520                                 default:
 521                                         strcat(cpu_model, "Unknown");
 522                                         break;
 523                                 }
 524                                 break;
 525                         case 0x20:
 526                                 if ((cyrix_did & 0x0f) < 8)
 527                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
 528                                 else
 529                                         strcat(cpu_model, "5x86");
 530                                 break;
 531                         case 0x30:
 532                                 strcat(cpu_model, "6x86");
 533                                 break;
 534                         case 0x40:
 535                                 if ((cyrix_did & 0xf000) == 0x3000) {
 536                                         cpu_class = CPUCLASS_586;
 537                                         strcat(cpu_model, "GXm");
 538                                 } else
 539                                         strcat(cpu_model, "MediaGX");
 540                                 break;
 541                         case 0x50:
 542                                 strcat(cpu_model, "6x86MX");
 543                                 break;
 544                         case 0xf0:
 545                                 switch (cyrix_did & 0x0f) {
 546                                 case 0x0d:
 547                                         strcat(cpu_model, "Overdrive CPU");
 548                                         break;
 549                                 case 0x0e:
 550                                         strcpy(cpu_model, "Texas Instruments 486SXL");
 551                                         break;
 552                                 case 0x0f:
 553                                         strcat(cpu_model, "486SLC/DLC");
 554                                         break;
 555                                 default:
 556                                         strcat(cpu_model, "Unknown");
 557                                         break;
 558                                 }
 559                                 break;
 560                         default:
 561                                 strcat(cpu_model, "Unknown");
 562                                 break;
 563                         }
 564                         break;
 565                 }
 566                 break;
 567         case CPU_VENDOR_RISE:
 568                 strcpy(cpu_model, "Rise ");
 569                 switch (cpu_id & 0xff0) {
 570                 case 0x500:     /* 6401 and 6441 (Kirin) */
 571                 case 0x520:     /* 6510 (Lynx) */
 572                         strcat(cpu_model, "mP6");
 573                         break;
 574                 default:
 575                         strcat(cpu_model, "Unknown");
 576                 }
 577                 break;
 578 #endif
 579         case CPU_VENDOR_CENTAUR:
 580 #ifdef __i386__
 581                 switch (cpu_id & 0xff0) {
 582                 case 0x540:
 583                         strcpy(cpu_model, "IDT WinChip C6");
 584                         break;
 585                 case 0x580:
 586                         strcpy(cpu_model, "IDT WinChip 2");
 587                         break;
 588                 case 0x590:
 589                         strcpy(cpu_model, "IDT WinChip 3");
 590                         break;
 591                 case 0x660:
 592                         strcpy(cpu_model, "VIA C3 Samuel");
 593                         break;
 594                 case 0x670:
 595                         if (cpu_id & 0x8)
 596                                 strcpy(cpu_model, "VIA C3 Ezra");
 597                         else
 598                                 strcpy(cpu_model, "VIA C3 Samuel 2");
 599                         break;
 600                 case 0x680:
 601                         strcpy(cpu_model, "VIA C3 Ezra-T");
 602                         break;
 603                 case 0x690:
 604                         strcpy(cpu_model, "VIA C3 Nehemiah");
 605                         break;
 606                 case 0x6a0:
 607                 case 0x6d0:
 608                         strcpy(cpu_model, "VIA C7 Esther");
 609                         break;
 610                 case 0x6f0:
 611                         strcpy(cpu_model, "VIA Nano");
 612                         break;
 613                 default:
 614                         strcpy(cpu_model, "VIA/IDT Unknown");
 615                 }
 616 #else
 617                 strcpy(cpu_model, "VIA ");
 618                 if ((cpu_id & 0xff0) == 0x6f0)
 619                         strcat(cpu_model, "Nano Processor");
 620                 else
 621                         strcat(cpu_model, "Unknown");
 622 #endif
 623                 break;
 624 #ifdef __i386__
 625         case CPU_VENDOR_IBM:
 626                 strcpy(cpu_model, "Blue Lightning CPU");
 627                 break;
 628         case CPU_VENDOR_NSC:
 629                 switch (cpu_id & 0xff0) {
 630                 case 0x540:
 631                         strcpy(cpu_model, "Geode SC1100");
 632                         cpu = CPU_GEODE1100;
 633                         break;
 634                 default:
 635                         strcpy(cpu_model, "Geode/NSC unknown");
 636                         break;
 637                 }
 638                 break;
 639 #endif
 640         default:
 641                 strcat(cpu_model, "Unknown");
 642                 break;
 643         }
 644
 645         /*
 646          * Replace cpu_model with cpu_brand minus leading spaces if
 647          * we have one.
 648          */
 649         brand = cpu_brand;
 650         while (*brand == ' ')
 651                 ++brand;
 652         if (*brand != '\0')
 653                 strcpy(cpu_model, brand);
 654
 655         printf("%s (", cpu_model);
 656         if (tsc_freq != 0) {
 657                 hw_clockrate = (tsc_freq + 5000) / 1000000;
 658                 printf("%jd.%02d-MHz ",
 659                     (intmax_t)(tsc_freq + 4999) / 1000000,
 660                     (u_int)((tsc_freq + 4999) / 10000) % 100);
 661         }
 662         switch(cpu_class) {
 663 #ifdef __i386__
 664         case CPUCLASS_286:
 665                 printf("286");
 666                 break;
 667         case CPUCLASS_386:
 668                 printf("386");
 669                 break;
 670 #if defined(I486_CPU)
 671         case CPUCLASS_486:
 672                 printf("486");
 673                 break;
 674 #endif
 675 #if defined(I586_CPU)
 676         case CPUCLASS_586:
 677                 printf("586");
 678                 break;
 679 #endif
 680 #if defined(I686_CPU)
 681         case CPUCLASS_686:
 682                 printf("686");
 683                 break;
 684 #endif
 685 #else
 686         case CPUCLASS_K8:
 687                 printf("K8");
 688                 break;
 689 #endif
 690         default:
 691                 printf("Unknown");      /* will panic below... */
 692         }
 693         printf("-class CPU)\n");
 694         if (*cpu_vendor)
 695                 printf("  Origin=\"%s\"", cpu_vendor);
 696         if (cpu_id)
 697                 printf("  Id=0x%x", cpu_id);
 698
 699         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 700             cpu_vendor_id == CPU_VENDOR_AMD ||
 701             cpu_vendor_id == CPU_VENDOR_CENTAUR ||
 702 #ifdef __i386__
 703             cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
 704             cpu_vendor_id == CPU_VENDOR_RISE ||
 705             cpu_vendor_id == CPU_VENDOR_NSC ||
 706             (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
 707 #endif
 708             0) {
 709                 printf("  Family=0x%x", CPUID_TO_FAMILY(cpu_id));
 710                 printf("  Model=0x%x", CPUID_TO_MODEL(cpu_id));
 711                 printf("  Stepping=%u", cpu_id & CPUID_STEPPING);
 712 #ifdef __i386__
 713                 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
 714                         printf("\n  DIR=0x%04x", cyrix_did);
 715 #endif
 716
 717                 /*
 718                  * AMD CPUID Specification
 719                  * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
 720                  *
 721                  * Intel Processor Identification and CPUID Instruction
 722                  * http://www.intel.com/assets/pdf/appnote/241618.pdf
 723                  */
 724                 if (cpu_high > 0) {
 725
 726                         /*
 727                          * Here we should probably set up flags indicating
 728                          * whether or not various features are available.
 729                          * The interesting ones are probably VME, PSE, PAE,
 730                          * and PGE.  The code already assumes without bothering
 731                          * to check that all CPUs >= Pentium have a TSC and
 732                          * MSRs.
 733                          */
 734                         printf("\n  Features=0x%b", cpu_feature,
 735                         "\020"
 736                         "\001FPU"       /* Integral FPU */
 737                         "\002VME"       /* Extended VM86 mode support */
 738                         "\003DE"        /* Debugging Extensions (CR4.DE) */
 739                         "\004PSE"       /* 4MByte page tables */
 740                         "\005TSC"       /* Timestamp counter */
 741                         "\006MSR"       /* Machine specific registers */
 742                         "\007PAE"       /* Physical address extension */
 743                         "\010MCE"       /* Machine Check support */
 744                         "\011CX8"       /* CMPEXCH8 instruction */
 745                         "\012APIC"      /* SMP local APIC */
 746                         "\013oldMTRR"   /* Previous implementation of MTRR */
 747                         "\014SEP"       /* Fast System Call */
 748                         "\015MTRR"      /* Memory Type Range Registers */
 749                         "\016PGE"       /* PG_G (global bit) support */
 750                         "\017MCA"       /* Machine Check Architecture */
 751                         "\020CMOV"      /* CMOV instruction */
 752                         "\021PAT"       /* Page attributes table */
 753                         "\022PSE36"     /* 36 bit address space support */
 754                         "\023PN"        /* Processor Serial number */
 755                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
 756                         "\025<b20>"
 757                         "\026DTS"       /* Debug Trace Store */
 758                         "\027ACPI"      /* ACPI support */
 759                         "\030MMX"       /* MMX instructions */
 760                         "\031FXSR"      /* FXSAVE/FXRSTOR */
 761                         "\032SSE"       /* Streaming SIMD Extensions */
 762                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
 763                         "\034SS"        /* Self snoop */
 764                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
 765                         "\036TM"        /* Thermal Monitor clock slowdown */
 766                         "\037IA64"      /* CPU can execute IA64 instructions */
 767                         "\040PBE"       /* Pending Break Enable */
 768                         );
 769
 770                         if (cpu_feature2 != 0) {
 771                                 printf("\n  Features2=0x%b", cpu_feature2,
 772                                 "\020"
 773                                 "\001SSE3"      /* SSE3 */
 774                                 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
 775                                 "\003DTES64"    /* 64-bit Debug Trace */
 776                                 "\004MON"       /* MONITOR/MWAIT Instructions */
 777                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
 778                                 "\006VMX"       /* Virtual Machine Extensions */
 779                                 "\007SMX"       /* Safer Mode Extensions */
 780                                 "\010EST"       /* Enhanced SpeedStep */
 781                                 "\011TM2"       /* Thermal Monitor 2 */
 782                                 "\012SSSE3"     /* SSSE3 */
 783                                 "\013CNXT-ID"   /* L1 context ID available */
 784                                 "\014SDBG"      /* IA32 silicon debug */
 785                                 "\015FMA"       /* Fused Multiply Add */
 786                                 "\016CX16"      /* CMPXCHG16B Instruction */
 787                                 "\017xTPR"      /* Send Task Priority Messages*/
 788                                 "\020PDCM"      /* Perf/Debug Capability MSR */
 789                                 "\021<b16>"
 790                                 "\022PCID"      /* Process-context Identifiers*/
 791                                 "\023DCA"       /* Direct Cache Access */
 792                                 "\024SSE4.1"    /* SSE 4.1 */
 793                                 "\025SSE4.2"    /* SSE 4.2 */
 794                                 "\026x2APIC"    /* xAPIC Extensions */
 795                                 "\027MOVBE"     /* MOVBE Instruction */
 796                                 "\030POPCNT"    /* POPCNT Instruction */
 797                                 "\031TSCDLT"    /* TSC-Deadline Timer */
 798                                 "\032AESNI"     /* AES Crypto */
 799                                 "\033XSAVE"     /* XSAVE/XRSTOR States */
 800                                 "\034OSXSAVE"   /* OS-Enabled State Management*/
 801                                 "\035AVX"       /* Advanced Vector Extensions */
 802                                 "\036F16C"      /* Half-precision conversions */
 803                                 "\037RDRAND"    /* RDRAND Instruction */
 804                                 "\040HV"        /* Hypervisor */
 805                                 );
 806                         }
 807
 808                         if (amd_feature != 0) {
 809                                 printf("\n  AMD Features=0x%b", amd_feature,
 810                                 "\020"          /* in hex */
 811                                 "\001<s0>"      /* Same */
 812                                 "\002<s1>"      /* Same */
 813                                 "\003<s2>"      /* Same */
 814                                 "\004<s3>"      /* Same */
 815                                 "\005<s4>"      /* Same */
 816                                 "\006<s5>"      /* Same */
 817                                 "\007<s6>"      /* Same */
 818                                 "\010<s7>"      /* Same */
 819                                 "\011<s8>"      /* Same */
 820                                 "\012<s9>"      /* Same */
 821                                 "\013<b10>"     /* Undefined */
 822                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
 823                                 "\015<s12>"     /* Same */
 824                                 "\016<s13>"     /* Same */
 825                                 "\017<s14>"     /* Same */
 826                                 "\020<s15>"     /* Same */
 827                                 "\021<s16>"     /* Same */
 828                                 "\022<s17>"     /* Same */
 829                                 "\023<b18>"     /* Reserved, unknown */
 830                                 "\024MP"        /* Multiprocessor Capable */
 831                                 "\025NX"        /* Has EFER.NXE, NX */
 832                                 "\026<b21>"     /* Undefined */
 833                                 "\027MMX+"      /* AMD MMX Extensions */
 834                                 "\030<s23>"     /* Same */
 835                                 "\031<s24>"     /* Same */
 836                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
 837                                 "\033Page1GB"   /* 1-GB large page support */
 838                                 "\034RDTSCP"    /* RDTSCP */
 839                                 "\035<b28>"     /* Undefined */
 840                                 "\036LM"        /* 64 bit long mode */
 841                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
 842                                 "\0403DNow!"    /* AMD 3DNow! */
 843                                 );
 844                         }
 845
 846                         if (amd_feature2 != 0) {
 847                                 printf("\n  AMD Features2=0x%b", amd_feature2,
 848                                 "\020"
 849                                 "\001LAHF"      /* LAHF/SAHF in long mode */
 850                                 "\002CMP"       /* CMP legacy */
 851                                 "\003SVM"       /* Secure Virtual Mode */
 852                                 "\004ExtAPIC"   /* Extended APIC register */
 853                                 "\005CR8"       /* CR8 in legacy mode */
 854                                 "\006ABM"       /* LZCNT instruction */
 855                                 "\007SSE4A"     /* SSE4A */
 856                                 "\010MAS"       /* Misaligned SSE mode */
 857                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
 858                                 "\012OSVW"      /* OS visible workaround */
 859                                 "\013IBS"       /* Instruction based sampling */
 860                                 "\014XOP"       /* XOP extended instructions */
 861                                 "\015SKINIT"    /* SKINIT/STGI */
 862                                 "\016WDT"       /* Watchdog timer */
 863                                 "\017<b14>"
 864                                 "\020LWP"       /* Lightweight Profiling */
 865                                 "\021FMA4"      /* 4-operand FMA instructions */
 866                                 "\022TCE"       /* Translation Cache Extension */
 867                                 "\023<b18>"
 868                                 "\024NodeId"    /* NodeId MSR support */
 869                                 "\025<b20>"
 870                                 "\026TBM"       /* Trailing Bit Manipulation */
 871                                 "\027Topology"  /* Topology Extensions */
 872                                 "\030PCXC"      /* Core perf count */
 873                                 "\031PNXC"      /* NB perf count */
 874                                 "\032<b25>"
 875                                 "\033DBE"       /* Data Breakpoint extension */
 876                                 "\034PTSC"      /* Performance TSC */
 877                                 "\035PL2I"      /* L2I perf count */
 878                                 "\036MWAITX"    /* MONITORX/MWAITX instructions */
 879                                 "\037<b30>"
 880                                 "\040<b31>"
 881                                 );
 882                         }
 883
 884                         if (cpu_stdext_feature != 0) {
 885                                 printf("\n  Structured Extended Features=0x%b",
 886                                     cpu_stdext_feature,
 887                                        "\020"
 888                                        /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
 889                                        "\001FSGSBASE"
 890                                        "\002TSCADJ"
 891                                        "\003SGX"
 892                                        /* Bit Manipulation Instructions */
 893                                        "\004BMI1"
 894                                        /* Hardware Lock Elision */
 895                                        "\005HLE"
 896                                        /* Advanced Vector Instructions 2 */
 897                                        "\006AVX2"
 898                                        /* FDP_EXCPTN_ONLY */
 899                                        "\007FDPEXC"
 900                                        /* Supervisor Mode Execution Prot. */
 901                                        "\010SMEP"
 902                                        /* Bit Manipulation Instructions */
 903                                        "\011BMI2"
 904                                        "\012ERMS"
 905                                        /* Invalidate Processor Context ID */
 906                                        "\013INVPCID"
 907                                        /* Restricted Transactional Memory */
 908                                        "\014RTM"
 909                                        "\015PQM"
 910                                        "\016NFPUSG"
 911                                        /* Intel Memory Protection Extensions */
 912                                        "\017MPX"
 913                                        "\020PQE"
 914                                        /* AVX512 Foundation */
 915                                        "\021AVX512F"
 916                                        /* Enhanced NRBG */
 917                                        "\023RDSEED"
 918                                        /* ADCX + ADOX */
 919                                        "\024ADX"
 920                                        /* Supervisor Mode Access Prevention */
 921                                        "\025SMAP"
 922                                        "\030CLFLUSHOPT"
 923                                        "\032PROCTRACE"
 924                                        "\033AVX512PF"
 925                                        "\034AVX512ER"
 926                                        "\035AVX512CD"
 927                                        "\036SHA"
 928                                        );
 929                         }
 930
 931                         if (cpu_stdext_feature2 != 0) {
 932                                 printf("\n  Structured Extended Features2=0x%b",
 933                                     cpu_stdext_feature2,
 934                                        "\020"
 935                                        "\001PREFETCHWT1"
 936                                        "\003UMIP"
 937                                        "\004PKU"
 938                                        "\005OSPKE"
 939                                        "\027RDPID"
 940                                        "\037SGXLC"
 941                                        );
 942                         }
 943
 944                         if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
 945                                 cpuid_count(0xd, 0x1, regs);
 946                                 if (regs[0] != 0) {
 947                                         printf("\n  XSAVE Features=0x%b",
 948                                             regs[0],
 949                                             "\020"
 950                                             "\001XSAVEOPT"
 951                                             "\002XSAVEC"
 952                                             "\003XINUSE"
 953                                             "\004XSAVES");
 954                                 }
 955                         }
 956
 957                         if (via_feature_rng != 0 || via_feature_xcrypt != 0)
 958                                 print_via_padlock_info();
 959
 960                         if (cpu_feature2 & CPUID2_VMX)
 961                                 print_vmx_info();
 962
 963                         if (amd_feature2 & AMDID2_SVM)
 964                                 print_svm_info();
 965
 966                         if ((cpu_feature & CPUID_HTT) &&
 967                             cpu_vendor_id == CPU_VENDOR_AMD)
 968                                 cpu_feature &= ~CPUID_HTT;
 969
 970                         /*
 971                          * If this CPU supports P-state invariant TSC then
 972                          * mention the capability.
 973                          */
 974                         if (tsc_is_invariant) {
 975                                 printf("\n  TSC: P-state invariant");
 976                                 if (tsc_perf_stat)
 977                                         printf(", performance statistics");
 978                         }
 979                 }
 980 #ifdef __i386__
 981         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
 982                 printf("  DIR=0x%04x", cyrix_did);
 983                 printf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
 984                 printf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
 985 #ifndef CYRIX_CACHE_REALLY_WORKS
 986                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
 987                         printf("\n  CPU cache: write-through mode");
 988 #endif
 989 #endif
 990         }
 991
 992         /* Avoid ugly blank lines: only print newline when we have to. */
 993         if (*cpu_vendor || cpu_id)
 994                 printf("\n");
 995
 996         if (bootverbose) {
 997                 if (cpu_vendor_id == CPU_VENDOR_AMD)
 998                         print_AMD_info();
 999                 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1000                         print_INTEL_info();
1001 #ifdef __i386__
1002                 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1003                         print_transmeta_info();
1004 #endif
1005         }
1006
1007         print_hypervisor_info();
1008 }
1009
1010 void
1011 panicifcpuunsupported(void)
1012 {
1013
1014 #ifdef __i386__
1015 #if !defined(lint)
1016 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1017 #error This kernel is not configured for one of the supported CPUs
1018 #endif
1019 #else /* lint */
1020 #endif /* lint */
1021 #else /* __amd64__ */
1022 #ifndef HAMMER
1023 #error "You need to specify a cpu type"
1024 #endif
1025 #endif
1026         /*
1027          * Now that we have told the user what they have,
1028          * let them know if that machine type isn't configured.
1029          */
1030         switch (cpu_class) {
1031 #ifdef __i386__
1032         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
1033         case CPUCLASS_386:
1034 #if !defined(I486_CPU)
1035         case CPUCLASS_486:
1036 #endif
1037 #if !defined(I586_CPU)
1038         case CPUCLASS_586:
1039 #endif
1040 #if !defined(I686_CPU)
1041         case CPUCLASS_686:
1042 #endif
1043 #else /* __amd64__ */
1044         case CPUCLASS_X86:
1045 #ifndef HAMMER
1046         case CPUCLASS_K8:
1047 #endif
1048 #endif
1049                 panic("CPU class not configured");
1050         default:
1051                 break;
1052         }
1053 }
1054
1055 #ifdef __i386__
1056 static  volatile u_int trap_by_rdmsr;
1057
1058 /*
1059  * Special exception 6 handler.
1060  * The rdmsr instruction generates invalid opcodes fault on 486-class
1061  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
1062  * function identblue() when this handler is called.  Stacked eip should
1063  * be advanced.
1064  */
1065 inthand_t       bluetrap6;
1066 #ifdef __GNUCLIKE_ASM
1067 __asm
1068 ("                                                                      \n\
1069         .text                                                           \n\
1070         .p2align 2,0x90                                                 \n\
1071         .type   " __XSTRING(CNAME(bluetrap6)) ",@function               \n\
1072 " __XSTRING(CNAME(bluetrap6)) ":                                        \n\
1073         ss                                                              \n\
1074         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1075         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1076         iret                                                            \n\
1077 ");
1078 #endif
1079
1080 /*
1081  * Special exception 13 handler.
1082  * Accessing non-existent MSR generates general protection fault.
1083  */
1084 inthand_t       bluetrap13;
1085 #ifdef __GNUCLIKE_ASM
1086 __asm
1087 ("                                                                      \n\
1088         .text                                                           \n\
1089         .p2align 2,0x90                                                 \n\
1090         .type   " __XSTRING(CNAME(bluetrap13)) ",@function              \n\
1091 " __XSTRING(CNAME(bluetrap13)) ":                                       \n\
1092         ss                                                              \n\
1093         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1094         popl    %eax            /* discard error code */                \n\
1095         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1096         iret                                                            \n\
1097 ");
1098 #endif
1099
1100 /*
1101  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1102  * support cpuid instruction.  This function should be called after
1103  * loading interrupt descriptor table register.
1104  *
1105  * I don't like this method that handles fault, but I couldn't get
1106  * information for any other methods.  Does blue giant know?
1107  */
1108 static int
1109 identblue(void)
1110 {
1111
1112         trap_by_rdmsr = 0;
1113
1114         /*
1115          * Cyrix 486-class CPU does not support rdmsr instruction.
1116          * The rdmsr instruction generates invalid opcode fault, and exception
1117          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
1118          * bluetrap6() set the magic number to trap_by_rdmsr.
1119          */
1120         setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1121             GSEL(GCODE_SEL, SEL_KPL));
1122
1123         /*
1124          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1125          * In this case, rdmsr generates general protection fault, and
1126          * exception will be trapped by bluetrap13().
1127          */
1128         setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1129             GSEL(GCODE_SEL, SEL_KPL));
1130
1131         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
1132
1133         if (trap_by_rdmsr == 0xa8c1d)
1134                 return IDENTBLUE_CYRIX486;
1135         else if (trap_by_rdmsr == 0xa89c4)
1136                 return IDENTBLUE_CYRIXM2;
1137         return IDENTBLUE_IBMCPU;
1138 }
1139
1140
1141 /*
1142  * identifycyrix() set lower 16 bits of cyrix_did as follows:
1143  *
1144  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
1145  * +-------+-------+---------------+
1146  * |  SID  |  RID  |   Device ID   |
1147  * |    (DIR 1)    |    (DIR 0)    |
1148  * +-------+-------+---------------+
1149  */
1150 static void
1151 identifycyrix(void)
1152 {
1153         register_t saveintr;
1154         int     ccr2_test = 0, dir_test = 0;
1155         u_char  ccr2, ccr3;
1156
1157         saveintr = intr_disable();
1158
1159         ccr2 = read_cyrix_reg(CCR2);
1160         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1161         read_cyrix_reg(CCR2);
1162         if (read_cyrix_reg(CCR2) != ccr2)
1163                 ccr2_test = 1;
1164         write_cyrix_reg(CCR2, ccr2);
1165
1166         ccr3 = read_cyrix_reg(CCR3);
1167         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1168         read_cyrix_reg(CCR3);
1169         if (read_cyrix_reg(CCR3) != ccr3)
1170                 dir_test = 1;                                   /* CPU supports DIRs. */
1171         write_cyrix_reg(CCR3, ccr3);
1172
1173         if (dir_test) {
1174                 /* Device ID registers are available. */
1175                 cyrix_did = read_cyrix_reg(DIR1) << 8;
1176                 cyrix_did += read_cyrix_reg(DIR0);
1177         } else if (ccr2_test)
1178                 cyrix_did = 0x0010;             /* 486S A-step */
1179         else
1180                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
1181
1182         intr_restore(saveintr);
1183 }
1184 #endif
1185
1186 /* Update TSC freq with the value indicated by the caller. */
1187 static void
1188 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1189 {
1190
1191         /* If there was an error during the transition, don't do anything. */
1192         if (status != 0)
1193                 return;
1194
1195         /* Total setting for this level gives the new frequency in MHz. */
1196         hw_clockrate = level->total_set.freq;
1197 }
1198
1199 static void
1200 hook_tsc_freq(void *arg __unused)
1201 {
1202
1203         if (tsc_is_invariant)
1204                 return;
1205
1206         tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1207             tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1208 }
1209
1210 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1211
1212 #ifndef XEN
1213 static const char *const vm_bnames[] = {
1214         "QEMU",                         /* QEMU */
1215         "Plex86",                       /* Plex86 */
1216         "Bochs",                        /* Bochs */
1217         "Xen",                          /* Xen */
1218         "BHYVE",                        /* bhyve */
1219         "Seabios",                      /* KVM */
1220         NULL
1221 };
1222
1223 static const char *const vm_pnames[] = {
1224         "VMware Virtual Platform",      /* VMWare VM */
1225         "Virtual Machine",              /* Microsoft VirtualPC */
1226         "VirtualBox",                   /* Sun xVM VirtualBox */
1227         "Parallels Virtual Platform",   /* Parallels VM */
1228         "KVM",                          /* KVM */
1229         NULL
1230 };
1231
1232 static void
1233 identify_hypervisor(void)
1234 {
1235         u_int regs[4];
1236         char *p;
1237         int i;
1238
1239         /*
1240          * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1241          * http://lkml.org/lkml/2008/10/1/246
1242          *
1243          * KB1009458: Mechanisms to determine if software is running in
1244          * a VMware virtual machine
1245          * http://kb.vmware.com/kb/1009458
1246          */
1247         if (cpu_feature2 & CPUID2_HV) {
1248                 vm_guest = VM_GUEST_VM;
1249                 do_cpuid(0x40000000, regs);
1250                 if (regs[0] >= 0x40000000) {
1251                         hv_high = regs[0];
1252                         ((u_int *)&hv_vendor)[0] = regs[1];
1253                         ((u_int *)&hv_vendor)[1] = regs[2];
1254                         ((u_int *)&hv_vendor)[2] = regs[3];
1255                         hv_vendor[12] = '\0';
1256                         if (strcmp(hv_vendor, "VMwareVMware") == 0)
1257                                 vm_guest = VM_GUEST_VMWARE;
1258                         else if (strcmp(hv_vendor, "Microsoft Hv") == 0)
1259                                 vm_guest = VM_GUEST_HV;
1260                 }
1261                 return;
1262         }
1263
1264         /*
1265          * Examine SMBIOS strings for older hypervisors.
1266          */
1267         p = getenv("smbios.system.serial");
1268         if (p != NULL) {
1269                 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1270                         vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1271                         if (regs[1] == VMW_HVMAGIC) {
1272                                 vm_guest = VM_GUEST_VMWARE;
1273                                 freeenv(p);
1274                                 return;
1275                         }
1276                 }
1277                 freeenv(p);
1278         }
1279
1280         /*
1281          * XXX: Some of these entries may not be needed since they were
1282          * added to FreeBSD before the checks above.
1283          */
1284         p = getenv("smbios.bios.vendor");
1285         if (p != NULL) {
1286                 for (i = 0; vm_bnames[i] != NULL; i++)
1287                         if (strcmp(p, vm_bnames[i]) == 0) {
1288                                 vm_guest = VM_GUEST_VM;
1289                                 freeenv(p);
1290                                 return;
1291                         }
1292                 freeenv(p);
1293         }
1294         p = getenv("smbios.system.product");
1295         if (p != NULL) {
1296                 for (i = 0; vm_pnames[i] != NULL; i++)
1297                         if (strcmp(p, vm_pnames[i]) == 0) {
1298                                 vm_guest = VM_GUEST_VM;
1299                                 freeenv(p);
1300                                 return;
1301                         }
1302                 freeenv(p);
1303         }
1304 }
1305 #endif
1306
1307 bool
1308 fix_cpuid(void)
1309 {
1310         uint64_t msr;
1311
1312         /*
1313          * Clear "Limit CPUID Maxval" bit and return true if the caller should
1314          * get the largest standard CPUID function number again if it is set
1315          * from BIOS.  It is necessary for probing correct CPU topology later
1316          * and for the correct operation of the AVX-aware userspace.
1317          */
1318         if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1319             ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1320             CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1321             (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1322             CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1323                 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1324                 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1325                         msr &= ~IA32_MISC_EN_LIMCPUID;
1326                         wrmsr(MSR_IA32_MISC_ENABLE, msr);
1327                         return (true);
1328                 }
1329         }
1330
1331         /*
1332          * Re-enable AMD Topology Extension that could be disabled by BIOS
1333          * on some notebook processors.  Without the extension it's really
1334          * hard to determine the correct CPU cache topology.
1335          * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1336          * Models 60h-6Fh Processors, Publication # 50742.
1337          */
1338         if (cpu_vendor_id == CPU_VENDOR_AMD && CPUID_TO_FAMILY(cpu_id) == 0x15) {
1339                 msr = rdmsr(MSR_EXTFEATURES);
1340                 if ((msr & ((uint64_t)1 << 54)) == 0) {
1341                         msr |= (uint64_t)1 << 54;
1342                         wrmsr(MSR_EXTFEATURES, msr);
1343                         return (true);
1344                 }
1345         }
1346         return (false);
1347 }
1348
1349 /*
1350  * Final stage of CPU identification.
1351  */
1352 #ifdef __i386__
1353 void
1354 finishidentcpu(void)
1355 #else
1356 void
1357 identify_cpu(void)
1358 #endif
1359 {
1360         u_int regs[4], cpu_stdext_disable;
1361 #ifdef __i386__
1362         u_char ccr3;
1363 #endif
1364
1365 #ifdef __amd64__
1366         do_cpuid(0, regs);
1367         cpu_high = regs[0];
1368         ((u_int *)&cpu_vendor)[0] = regs[1];
1369         ((u_int *)&cpu_vendor)[1] = regs[3];
1370         ((u_int *)&cpu_vendor)[2] = regs[2];
1371         cpu_vendor[12] = '\0';
1372
1373         do_cpuid(1, regs);
1374         cpu_id = regs[0];
1375         cpu_procinfo = regs[1];
1376         cpu_feature = regs[3];
1377         cpu_feature2 = regs[2];
1378 #endif
1379
1380 #ifndef XEN
1381         identify_hypervisor();
1382 #endif
1383         cpu_vendor_id = find_cpu_vendor_id();
1384
1385         if (fix_cpuid()) {
1386                 do_cpuid(0, regs);
1387                 cpu_high = regs[0];
1388         }
1389
1390         if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1391                 do_cpuid(5, regs);
1392                 cpu_mon_mwait_flags = regs[2];
1393                 cpu_mon_min_size = regs[0] &  CPUID5_MON_MIN_SIZE;
1394                 cpu_mon_max_size = regs[1] &  CPUID5_MON_MAX_SIZE;
1395         }
1396
1397         if (cpu_high >= 7) {
1398                 cpuid_count(7, 0, regs);
1399                 cpu_stdext_feature = regs[1];
1400
1401                 /*
1402                  * Some hypervisors fail to filter out unsupported
1403                  * extended features.  For now, disable the
1404                  * extensions, activation of which requires setting a
1405                  * bit in CR4, and which VM monitors do not support.
1406                  */
1407                 if (cpu_feature2 & CPUID2_HV) {
1408                         cpu_stdext_disable = CPUID_STDEXT_FSGSBASE |
1409                             CPUID_STDEXT_SMEP;
1410                 } else
1411                         cpu_stdext_disable = 0;
1412                 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1413                 cpu_stdext_feature &= ~cpu_stdext_disable;
1414                 cpu_stdext_feature2 = regs[2];
1415         }
1416
1417 #ifdef __i386__
1418         if (cpu_high > 0 &&
1419             (cpu_vendor_id == CPU_VENDOR_INTEL ||
1420              cpu_vendor_id == CPU_VENDOR_AMD ||
1421              cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1422              cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1423              cpu_vendor_id == CPU_VENDOR_NSC)) {
1424                 do_cpuid(0x80000000, regs);
1425                 if (regs[0] >= 0x80000000)
1426                         cpu_exthigh = regs[0];
1427         }
1428 #else
1429         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1430             cpu_vendor_id == CPU_VENDOR_AMD ||
1431             cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1432                 do_cpuid(0x80000000, regs);
1433                 cpu_exthigh = regs[0];
1434         }
1435 #endif
1436         if (cpu_exthigh >= 0x80000001) {
1437                 do_cpuid(0x80000001, regs);
1438                 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1439                 amd_feature2 = regs[2];
1440         }
1441         if (cpu_exthigh >= 0x80000007) {
1442                 do_cpuid(0x80000007, regs);
1443                 amd_pminfo = regs[3];
1444         }
1445         if (cpu_exthigh >= 0x80000008) {
1446                 do_cpuid(0x80000008, regs);
1447                 cpu_maxphyaddr = regs[0] & 0xff;
1448                 cpu_procinfo2 = regs[2];
1449         } else {
1450                 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1451         }
1452
1453 #ifdef __i386__
1454         if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1455                 if (cpu == CPU_486) {
1456                         /*
1457                          * These conditions are equivalent to:
1458                          *     - CPU does not support cpuid instruction.
1459                          *     - Cyrix/IBM CPU is detected.
1460                          */
1461                         if (identblue() == IDENTBLUE_IBMCPU) {
1462                                 strcpy(cpu_vendor, "IBM");
1463                                 cpu_vendor_id = CPU_VENDOR_IBM;
1464                                 cpu = CPU_BLUE;
1465                                 return;
1466                         }
1467                 }
1468                 switch (cpu_id & 0xf00) {
1469                 case 0x600:
1470                         /*
1471                          * Cyrix's datasheet does not describe DIRs.
1472                          * Therefor, I assume it does not have them
1473                          * and use the result of the cpuid instruction.
1474                          * XXX they seem to have it for now at least. -Peter
1475                          */
1476                         identifycyrix();
1477                         cpu = CPU_M2;
1478                         break;
1479                 default:
1480                         identifycyrix();
1481                         /*
1482                          * This routine contains a trick.
1483                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1484                          */
1485                         switch (cyrix_did & 0x00f0) {
1486                         case 0x00:
1487                         case 0xf0:
1488                                 cpu = CPU_486DLC;
1489                                 break;
1490                         case 0x10:
1491                                 cpu = CPU_CY486DX;
1492                                 break;
1493                         case 0x20:
1494                                 if ((cyrix_did & 0x000f) < 8)
1495                                         cpu = CPU_M1;
1496                                 else
1497                                         cpu = CPU_M1SC;
1498                                 break;
1499                         case 0x30:
1500                                 cpu = CPU_M1;
1501                                 break;
1502                         case 0x40:
1503                                 /* MediaGX CPU */
1504                                 cpu = CPU_M1SC;
1505                                 break;
1506                         default:
1507                                 /* M2 and later CPUs are treated as M2. */
1508                                 cpu = CPU_M2;
1509
1510                                 /*
1511                                  * enable cpuid instruction.
1512                                  */
1513                                 ccr3 = read_cyrix_reg(CCR3);
1514                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1515                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1516                                 write_cyrix_reg(CCR3, ccr3);
1517
1518                                 do_cpuid(0, regs);
1519                                 cpu_high = regs[0];     /* eax */
1520                                 do_cpuid(1, regs);
1521                                 cpu_id = regs[0];       /* eax */
1522                                 cpu_feature = regs[3];  /* edx */
1523                                 break;
1524                         }
1525                 }
1526         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1527                 /*
1528                  * There are BlueLightning CPUs that do not change
1529                  * undefined flags by dividing 5 by 2.  In this case,
1530                  * the CPU identification routine in locore.s leaves
1531                  * cpu_vendor null string and puts CPU_486 into the
1532                  * cpu.
1533                  */
1534                 if (identblue() == IDENTBLUE_IBMCPU) {
1535                         strcpy(cpu_vendor, "IBM");
1536                         cpu_vendor_id = CPU_VENDOR_IBM;
1537                         cpu = CPU_BLUE;
1538                         return;
1539                 }
1540         }
1541 #else
1542         /* XXX */
1543         cpu = CPU_CLAWHAMMER;
1544 #endif
1545 }
1546
1547 static u_int
1548 find_cpu_vendor_id(void)
1549 {
1550         int     i;
1551
1552         for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++)
1553                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1554                         return (cpu_vendors[i].vendor_id);
1555         return (0);
1556 }
1557
1558 static void
1559 print_AMD_assoc(int i)
1560 {
1561         if (i == 255)
1562                 printf(", fully associative\n");
1563         else
1564                 printf(", %d-way associative\n", i);
1565 }
1566
1567 static void
1568 print_AMD_l2_assoc(int i)
1569 {
1570         switch (i & 0x0f) {
1571         case 0: printf(", disabled/not present\n"); break;
1572         case 1: printf(", direct mapped\n"); break;
1573         case 2: printf(", 2-way associative\n"); break;
1574         case 4: printf(", 4-way associative\n"); break;
1575         case 6: printf(", 8-way associative\n"); break;
1576         case 8: printf(", 16-way associative\n"); break;
1577         case 15: printf(", fully associative\n"); break;
1578         default: printf(", reserved configuration\n"); break;
1579         }
1580 }
1581
1582 static void
1583 print_AMD_info(void)
1584 {
1585 #ifdef __i386__
1586         uint64_t amd_whcr;
1587 #endif
1588         u_int regs[4];
1589
1590         if (cpu_exthigh >= 0x80000005) {
1591                 do_cpuid(0x80000005, regs);
1592                 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1593                 print_AMD_assoc(regs[0] >> 24);
1594
1595                 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1596                 print_AMD_assoc((regs[0] >> 8) & 0xff);
1597
1598                 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1599                 print_AMD_assoc(regs[1] >> 24);
1600
1601                 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1602                 print_AMD_assoc((regs[1] >> 8) & 0xff);
1603
1604                 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1605                 printf(", %d bytes/line", regs[2] & 0xff);
1606                 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1607                 print_AMD_assoc((regs[2] >> 16) & 0xff);
1608
1609                 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1610                 printf(", %d bytes/line", regs[3] & 0xff);
1611                 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1612                 print_AMD_assoc((regs[3] >> 16) & 0xff);
1613         }
1614
1615         if (cpu_exthigh >= 0x80000006) {
1616                 do_cpuid(0x80000006, regs);
1617                 if ((regs[0] >> 16) != 0) {
1618                         printf("L2 2MB data TLB: %d entries",
1619                             (regs[0] >> 16) & 0xfff);
1620                         print_AMD_l2_assoc(regs[0] >> 28);
1621                         printf("L2 2MB instruction TLB: %d entries",
1622                             regs[0] & 0xfff);
1623                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1624                 } else {
1625                         printf("L2 2MB unified TLB: %d entries",
1626                             regs[0] & 0xfff);
1627                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1628                 }
1629                 if ((regs[1] >> 16) != 0) {
1630                         printf("L2 4KB data TLB: %d entries",
1631                             (regs[1] >> 16) & 0xfff);
1632                         print_AMD_l2_assoc(regs[1] >> 28);
1633
1634                         printf("L2 4KB instruction TLB: %d entries",
1635                             (regs[1] >> 16) & 0xfff);
1636                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1637                 } else {
1638                         printf("L2 4KB unified TLB: %d entries",
1639                             (regs[1] >> 16) & 0xfff);
1640                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1641                 }
1642                 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1643                 printf(", %d bytes/line", regs[2] & 0xff);
1644                 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1645                 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1646         }
1647
1648 #ifdef __i386__
1649         if (((cpu_id & 0xf00) == 0x500)
1650             && (((cpu_id & 0x0f0) > 0x80)
1651                 || (((cpu_id & 0x0f0) == 0x80)
1652                     && (cpu_id & 0x00f) > 0x07))) {
1653                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1654                 amd_whcr = rdmsr(0xc0000082);
1655                 if (!(amd_whcr & (0x3ff << 22))) {
1656                         printf("Write Allocate Disable\n");
1657                 } else {
1658                         printf("Write Allocate Enable Limit: %dM bytes\n",
1659                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1660                         printf("Write Allocate 15-16M bytes: %s\n",
1661                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1662                 }
1663         } else if (((cpu_id & 0xf00) == 0x500)
1664                    && ((cpu_id & 0x0f0) > 0x50)) {
1665                 /* K6, K6-2(old core) */
1666                 amd_whcr = rdmsr(0xc0000082);
1667                 if (!(amd_whcr & (0x7f << 1))) {
1668                         printf("Write Allocate Disable\n");
1669                 } else {
1670                         printf("Write Allocate Enable Limit: %dM bytes\n",
1671                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1672                         printf("Write Allocate 15-16M bytes: %s\n",
1673                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
1674                         printf("Hardware Write Allocate Control: %s\n",
1675                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
1676                 }
1677         }
1678 #endif
1679         /*
1680          * Opteron Rev E shows a bug as in very rare occasions a read memory
1681          * barrier is not performed as expected if it is followed by a
1682          * non-atomic read-modify-write instruction.
1683          * As long as that bug pops up very rarely (intensive machine usage
1684          * on other operating systems generally generates one unexplainable
1685          * crash any 2 months) and as long as a model specific fix would be
1686          * impractical at this stage, print out a warning string if the broken
1687          * model and family are identified.
1688          */
1689         if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1690             CPUID_TO_MODEL(cpu_id) <= 0x3f)
1691                 printf("WARNING: This architecture revision has known SMP "
1692                     "hardware bugs which may cause random instability\n");
1693 }
1694
1695 static void
1696 print_INTEL_info(void)
1697 {
1698         u_int regs[4];
1699         u_int rounds, regnum;
1700         u_int nwaycode, nway;
1701
1702         if (cpu_high >= 2) {
1703                 rounds = 0;
1704                 do {
1705                         do_cpuid(0x2, regs);
1706                         if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1707                                 break;  /* we have a buggy CPU */
1708
1709                         for (regnum = 0; regnum <= 3; ++regnum) {
1710                                 if (regs[regnum] & (1<<31))
1711                                         continue;
1712                                 if (regnum != 0)
1713                                         print_INTEL_TLB(regs[regnum] & 0xff);
1714                                 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1715                                 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1716                                 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1717                         }
1718                 } while (--rounds > 0);
1719         }
1720
1721         if (cpu_exthigh >= 0x80000006) {
1722                 do_cpuid(0x80000006, regs);
1723                 nwaycode = (regs[2] >> 12) & 0x0f;
1724                 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1725                         nway = 1 << (nwaycode / 2);
1726                 else
1727                         nway = 0;
1728                 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1729                     (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1730         }
1731 }
1732
1733 static void
1734 print_INTEL_TLB(u_int data)
1735 {
1736         switch (data) {
1737         case 0x0:
1738         case 0x40:
1739         default:
1740                 break;
1741         case 0x1:
1742                 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1743                 break;
1744         case 0x2:
1745                 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1746                 break;
1747         case 0x3:
1748                 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1749                 break;
1750         case 0x4:
1751                 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1752                 break;
1753         case 0x6:
1754                 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1755                 break;
1756         case 0x8:
1757                 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
1758                 break;
1759         case 0x9:
1760                 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
1761                 break;
1762         case 0xa:
1763                 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
1764                 break;
1765         case 0xb:
1766                 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
1767                 break;
1768         case 0xc:
1769                 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
1770                 break;
1771         case 0xd:
1772                 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
1773                 break;
1774         case 0xe:
1775                 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
1776                 break;
1777         case 0x1d:
1778                 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
1779                 break;
1780         case 0x21:
1781                 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
1782                 break;
1783         case 0x22:
1784                 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1785                 break;
1786         case 0x23:
1787                 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1788                 break;
1789         case 0x24:
1790                 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
1791                 break;
1792         case 0x25:
1793                 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1794                 break;
1795         case 0x29:
1796                 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1797                 break;
1798         case 0x2c:
1799                 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
1800                 break;
1801         case 0x30:
1802                 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
1803                 break;
1804         case 0x39: /* De-listed in SDM rev. 54 */
1805                 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1806                 break;
1807         case 0x3b: /* De-listed in SDM rev. 54 */
1808                 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
1809                 break;
1810         case 0x3c: /* De-listed in SDM rev. 54 */
1811                 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1812                 break;
1813         case 0x41:
1814                 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
1815                 break;
1816         case 0x42:
1817                 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
1818                 break;
1819         case 0x43:
1820                 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
1821                 break;
1822         case 0x44:
1823                 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
1824                 break;
1825         case 0x45:
1826                 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
1827                 break;
1828         case 0x46:
1829                 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
1830                 break;
1831         case 0x47:
1832                 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
1833                 break;
1834         case 0x48:
1835                 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
1836                 break;
1837         case 0x49:
1838                 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
1839                     CPUID_TO_MODEL(cpu_id) == 0x6)
1840                         printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
1841                 else
1842                         printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
1843                 break;
1844         case 0x4a:
1845                 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
1846                 break;
1847         case 0x4b:
1848                 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
1849                 break;
1850         case 0x4c:
1851                 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
1852                 break;
1853         case 0x4d:
1854                 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
1855                 break;
1856         case 0x4e:
1857                 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
1858                 break;
1859         case 0x4f:
1860                 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
1861                 break;
1862         case 0x50:
1863                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
1864                 break;
1865         case 0x51:
1866                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
1867                 break;
1868         case 0x52:
1869                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
1870                 break;
1871         case 0x55:
1872                 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
1873                 break;
1874         case 0x56:
1875                 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
1876                 break;
1877         case 0x57:
1878                 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
1879                 break;
1880         case 0x59:
1881                 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
1882                 break;
1883         case 0x5a:
1884                 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
1885                 break;
1886         case 0x5b:
1887                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
1888                 break;
1889         case 0x5c:
1890                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
1891                 break;
1892         case 0x5d:
1893                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
1894                 break;
1895         case 0x60:
1896                 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1897                 break;
1898         case 0x61:
1899                 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
1900                 break;
1901         case 0x63:
1902                 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
1903                 break;
1904         case 0x64:
1905                 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
1906                 break;
1907         case 0x66:
1908                 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1909                 break;
1910         case 0x67:
1911                 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1912                 break;
1913         case 0x68:
1914                 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
1915                 break;
1916         case 0x6a:
1917                 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
1918                 break;
1919         case 0x6b:
1920                 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
1921                 break;
1922         case 0x6c:
1923                 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
1924                 break;
1925         case 0x6d:
1926                 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
1927                 break;
1928         case 0x70:
1929                 printf("Trace cache: 12K-uops, 8-way set associative\n");
1930                 break;
1931         case 0x71:
1932                 printf("Trace cache: 16K-uops, 8-way set associative\n");
1933                 break;
1934         case 0x72:
1935                 printf("Trace cache: 32K-uops, 8-way set associative\n");
1936                 break;
1937         case 0x76:
1938                 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
1939                 break;
1940         case 0x78:
1941                 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
1942                 break;
1943         case 0x79:
1944                 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1945                 break;
1946         case 0x7a:
1947                 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1948                 break;
1949         case 0x7b:
1950                 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1951                 break;
1952         case 0x7c:
1953                 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1954                 break;
1955         case 0x7d:
1956                 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
1957                 break;
1958         case 0x7f:
1959                 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
1960                 break;
1961         case 0x80:
1962                 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
1963                 break;
1964         case 0x82:
1965                 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
1966                 break;
1967         case 0x83:
1968                 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
1969                 break;
1970         case 0x84:
1971                 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
1972                 break;
1973         case 0x85:
1974                 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
1975                 break;
1976         case 0x86:
1977                 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
1978                 break;
1979         case 0x87:
1980                 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
1981                 break;
1982         case 0xa0:
1983                 printf("DTLB: 4k pages, fully associative, 32 entries\n");
1984                 break;
1985         case 0xb0:
1986                 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
1987                 break;
1988         case 0xb1:
1989                 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
1990                 break;
1991         case 0xb2:
1992                 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
1993                 break;
1994         case 0xb3:
1995                 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
1996                 break;
1997         case 0xb4:
1998                 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
1999                 break;
2000         case 0xb5:
2001                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2002                 break;
2003         case 0xb6:
2004                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2005                 break;
2006         case 0xba:
2007                 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2008                 break;
2009         case 0xc0:
2010                 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2011                 break;
2012         case 0xc1:
2013                 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2014                 break;
2015         case 0xc2:
2016                 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2017                 break;
2018         case 0xc3:
2019                 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2020                 break;
2021         case 0xc4:
2022                 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2023                 break;
2024         case 0xca:
2025                 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2026                 break;
2027         case 0xd0:
2028                 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2029                 break;
2030         case 0xd1:
2031                 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2032                 break;
2033         case 0xd2:
2034                 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2035                 break;
2036         case 0xd6:
2037                 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2038                 break;
2039         case 0xd7:
2040                 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2041                 break;
2042         case 0xd8:
2043                 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2044                 break;
2045         case 0xdc:
2046                 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2047                 break;
2048         case 0xdd:
2049                 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2050                 break;
2051         case 0xde:
2052                 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2053                 break;
2054         case 0xe2:
2055                 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2056                 break;
2057         case 0xe3:
2058                 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2059                 break;
2060         case 0xe4:
2061                 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2062                 break;
2063         case 0xea:
2064                 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2065                 break;
2066         case 0xeb:
2067                 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2068                 break;
2069         case 0xec:
2070                 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2071                 break;
2072         case 0xf0:
2073                 printf("64-Byte prefetching\n");
2074                 break;
2075         case 0xf1:
2076                 printf("128-Byte prefetching\n");
2077                 break;
2078         }
2079 }
2080
2081 static void
2082 print_svm_info(void)
2083 {
2084         u_int features, regs[4];
2085         uint64_t msr;
2086         int comma;
2087
2088         printf("\n  SVM: ");
2089         do_cpuid(0x8000000A, regs);
2090         features = regs[3];
2091
2092         msr = rdmsr(MSR_VM_CR);
2093         if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2094                 printf("(disabled in BIOS) ");
2095
2096         if (!bootverbose) {
2097                 comma = 0;
2098                 if (features & (1 << 0)) {
2099                         printf("%sNP", comma ? "," : "");
2100                         comma = 1;
2101                 }
2102                 if (features & (1 << 3)) {
2103                         printf("%sNRIP", comma ? "," : "");
2104                         comma = 1;
2105                 }
2106                 if (features & (1 << 5)) {
2107                         printf("%sVClean", comma ? "," : "");
2108                         comma = 1;
2109                 }
2110                 if (features & (1 << 6)) {
2111                         printf("%sAFlush", comma ? "," : "");
2112                         comma = 1;
2113                 }
2114                 if (features & (1 << 7)) {
2115                         printf("%sDAssist", comma ? "," : "");
2116                         comma = 1;
2117                 }
2118                 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2119                 return;
2120         }
2121
2122         printf("Features=0x%b", features,
2123                "\020"
2124                "\001NP"                 /* Nested paging */
2125                "\002LbrVirt"            /* LBR virtualization */
2126                "\003SVML"               /* SVM lock */
2127                "\004NRIPS"              /* NRIP save */
2128                "\005TscRateMsr"         /* MSR based TSC rate control */
2129                "\006VmcbClean"          /* VMCB clean bits */
2130                "\007FlushByAsid"        /* Flush by ASID */
2131                "\010DecodeAssist"       /* Decode assist */
2132                "\011<b8>"
2133                "\012<b9>"
2134                "\013PauseFilter"        /* PAUSE intercept filter */
2135                "\014<b11>"
2136                "\015PauseFilterThreshold" /* PAUSE filter threshold */
2137                "\016AVIC"               /* virtual interrupt controller */
2138                 );
2139         printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2140 }
2141
2142 #ifdef __i386__
2143 static void
2144 print_transmeta_info(void)
2145 {
2146         u_int regs[4], nreg = 0;
2147
2148         do_cpuid(0x80860000, regs);
2149         nreg = regs[0];
2150         if (nreg >= 0x80860001) {
2151                 do_cpuid(0x80860001, regs);
2152                 printf("  Processor revision %u.%u.%u.%u\n",
2153                        (regs[1] >> 24) & 0xff,
2154                        (regs[1] >> 16) & 0xff,
2155                        (regs[1] >> 8) & 0xff,
2156                        regs[1] & 0xff);
2157         }
2158         if (nreg >= 0x80860002) {
2159                 do_cpuid(0x80860002, regs);
2160                 printf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
2161                        (regs[1] >> 24) & 0xff,
2162                        (regs[1] >> 16) & 0xff,
2163                        (regs[1] >> 8) & 0xff,
2164                        regs[1] & 0xff,
2165                        regs[2]);
2166         }
2167         if (nreg >= 0x80860006) {
2168                 char info[65];
2169                 do_cpuid(0x80860003, (u_int*) &info[0]);
2170                 do_cpuid(0x80860004, (u_int*) &info[16]);
2171                 do_cpuid(0x80860005, (u_int*) &info[32]);
2172                 do_cpuid(0x80860006, (u_int*) &info[48]);
2173                 info[64] = 0;
2174                 printf("  %s\n", info);
2175         }
2176 }
2177 #endif
2178
2179 static void
2180 print_via_padlock_info(void)
2181 {
2182         u_int regs[4];
2183
2184         do_cpuid(0xc0000001, regs);
2185         printf("\n  VIA Padlock Features=0x%b", regs[3],
2186         "\020"
2187         "\003RNG"               /* RNG */
2188         "\007AES"               /* ACE */
2189         "\011AES-CTR"           /* ACE2 */
2190         "\013SHA1,SHA256"       /* PHE */
2191         "\015RSA"               /* PMM */
2192         );
2193 }
2194
2195 static uint32_t
2196 vmx_settable(uint64_t basic, int msr, int true_msr)
2197 {
2198         uint64_t val;
2199
2200         if (basic & (1ULL << 55))
2201                 val = rdmsr(true_msr);
2202         else
2203                 val = rdmsr(msr);
2204
2205         /* Just report the controls that can be set to 1. */
2206         return (val >> 32);
2207 }
2208
2209 static void
2210 print_vmx_info(void)
2211 {
2212         uint64_t basic, msr;
2213         uint32_t entry, exit, mask, pin, proc, proc2;
2214         int comma;
2215
2216         printf("\n  VT-x: ");
2217         msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2218         if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2219                 printf("(disabled in BIOS) ");
2220         basic = rdmsr(MSR_VMX_BASIC);
2221         pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2222             MSR_VMX_TRUE_PINBASED_CTLS);
2223         proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2224             MSR_VMX_TRUE_PROCBASED_CTLS);
2225         if (proc & PROCBASED_SECONDARY_CONTROLS)
2226                 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2227                     MSR_VMX_PROCBASED_CTLS2);
2228         else
2229                 proc2 = 0;
2230         exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2231         entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2232
2233         if (!bootverbose) {
2234                 comma = 0;
2235                 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2236                     entry & VM_ENTRY_LOAD_PAT) {
2237                         printf("%sPAT", comma ? "," : "");
2238                         comma = 1;
2239                 }
2240                 if (proc & PROCBASED_HLT_EXITING) {
2241                         printf("%sHLT", comma ? "," : "");
2242                         comma = 1;
2243                 }
2244                 if (proc & PROCBASED_MTF) {
2245                         printf("%sMTF", comma ? "," : "");
2246                         comma = 1;
2247                 }
2248                 if (proc & PROCBASED_PAUSE_EXITING) {
2249                         printf("%sPAUSE", comma ? "," : "");
2250                         comma = 1;
2251                 }
2252                 if (proc2 & PROCBASED2_ENABLE_EPT) {
2253                         printf("%sEPT", comma ? "," : "");
2254                         comma = 1;
2255                 }
2256                 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2257                         printf("%sUG", comma ? "," : "");
2258                         comma = 1;
2259                 }
2260                 if (proc2 & PROCBASED2_ENABLE_VPID) {
2261                         printf("%sVPID", comma ? "," : "");
2262                         comma = 1;
2263                 }
2264                 if (proc & PROCBASED_USE_TPR_SHADOW &&
2265                     proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2266                     proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2267                     proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2268                     proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2269                         printf("%sVID", comma ? "," : "");
2270                         comma = 1;
2271                         if (pin & PINBASED_POSTED_INTERRUPT)
2272                                 printf(",PostIntr");
2273                 }
2274                 return;
2275         }
2276
2277         mask = basic >> 32;
2278         printf("Basic Features=0x%b", mask,
2279         "\020"
2280         "\02132PA"              /* 32-bit physical addresses */
2281         "\022SMM"               /* SMM dual-monitor */
2282         "\027INS/OUTS"          /* VM-exit info for INS and OUTS */
2283         "\030TRUE"              /* TRUE_CTLS MSRs */
2284         );
2285         printf("\n        Pin-Based Controls=0x%b", pin,
2286         "\020"
2287         "\001ExtINT"            /* External-interrupt exiting */
2288         "\004NMI"               /* NMI exiting */
2289         "\006VNMI"              /* Virtual NMIs */
2290         "\007PreTmr"            /* Activate VMX-preemption timer */
2291         "\010PostIntr"          /* Process posted interrupts */
2292         );
2293         printf("\n        Primary Processor Controls=0x%b", proc,
2294         "\020"
2295         "\003INTWIN"            /* Interrupt-window exiting */
2296         "\004TSCOff"            /* Use TSC offsetting */
2297         "\010HLT"               /* HLT exiting */
2298         "\012INVLPG"            /* INVLPG exiting */
2299         "\013MWAIT"             /* MWAIT exiting */
2300         "\014RDPMC"             /* RDPMC exiting */
2301         "\015RDTSC"             /* RDTSC exiting */
2302         "\020CR3-LD"            /* CR3-load exiting */
2303         "\021CR3-ST"            /* CR3-store exiting */
2304         "\024CR8-LD"            /* CR8-load exiting */
2305         "\025CR8-ST"            /* CR8-store exiting */
2306         "\026TPR"               /* Use TPR shadow */
2307         "\027NMIWIN"            /* NMI-window exiting */
2308         "\030MOV-DR"            /* MOV-DR exiting */
2309         "\031IO"                /* Unconditional I/O exiting */
2310         "\032IOmap"             /* Use I/O bitmaps */
2311         "\034MTF"               /* Monitor trap flag */
2312         "\035MSRmap"            /* Use MSR bitmaps */
2313         "\036MONITOR"           /* MONITOR exiting */
2314         "\037PAUSE"             /* PAUSE exiting */
2315         );
2316         if (proc & PROCBASED_SECONDARY_CONTROLS)
2317                 printf("\n        Secondary Processor Controls=0x%b", proc2,
2318                 "\020"
2319                 "\001APIC"              /* Virtualize APIC accesses */
2320                 "\002EPT"               /* Enable EPT */
2321                 "\003DT"                /* Descriptor-table exiting */
2322                 "\004RDTSCP"            /* Enable RDTSCP */
2323                 "\005x2APIC"            /* Virtualize x2APIC mode */
2324                 "\006VPID"              /* Enable VPID */
2325                 "\007WBINVD"            /* WBINVD exiting */
2326                 "\010UG"                /* Unrestricted guest */
2327                 "\011APIC-reg"          /* APIC-register virtualization */
2328                 "\012VID"               /* Virtual-interrupt delivery */
2329                 "\013PAUSE-loop"        /* PAUSE-loop exiting */
2330                 "\014RDRAND"            /* RDRAND exiting */
2331                 "\015INVPCID"           /* Enable INVPCID */
2332                 "\016VMFUNC"            /* Enable VM functions */
2333                 "\017VMCS"              /* VMCS shadowing */
2334                 "\020EPT#VE"            /* EPT-violation #VE */
2335                 "\021XSAVES"            /* Enable XSAVES/XRSTORS */
2336                 );
2337         printf("\n        Exit Controls=0x%b", mask,
2338         "\020"
2339         "\003DR"                /* Save debug controls */
2340                                 /* Ignore Host address-space size */
2341         "\015PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2342         "\020AckInt"            /* Acknowledge interrupt on exit */
2343         "\023PAT-SV"            /* Save MSR_PAT */
2344         "\024PAT-LD"            /* Load MSR_PAT */
2345         "\025EFER-SV"           /* Save MSR_EFER */
2346         "\026EFER-LD"           /* Load MSR_EFER */
2347         "\027PTMR-SV"           /* Save VMX-preemption timer value */
2348         );
2349         printf("\n        Entry Controls=0x%b", mask,
2350         "\020"
2351         "\003DR"                /* Save debug controls */
2352                                 /* Ignore IA-32e mode guest */
2353                                 /* Ignore Entry to SMM */
2354                                 /* Ignore Deactivate dual-monitor treatment */
2355         "\016PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2356         "\017PAT"               /* Load MSR_PAT */
2357         "\020EFER"              /* Load MSR_EFER */
2358         );
2359         if (proc & PROCBASED_SECONDARY_CONTROLS &&
2360             (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2361                 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2362                 mask = msr;
2363                 printf("\n        EPT Features=0x%b", mask,
2364                 "\020"
2365                 "\001XO"                /* Execute-only translations */
2366                 "\007PW4"               /* Page-walk length of 4 */
2367                 "\011UC"                /* EPT paging-structure mem can be UC */
2368                 "\017WB"                /* EPT paging-structure mem can be WB */
2369                 "\0212M"                /* EPT PDE can map a 2-Mbyte page */
2370                 "\0221G"                /* EPT PDPTE can map a 1-Gbyte page */
2371                 "\025INVEPT"            /* INVEPT is supported */
2372                 "\026AD"                /* Accessed and dirty flags for EPT */
2373                 "\032single"            /* INVEPT single-context type */
2374                 "\033all"               /* INVEPT all-context type */
2375                 );
2376                 mask = msr >> 32;
2377                 printf("\n        VPID Features=0x%b", mask,
2378                 "\020"
2379                 "\001INVVPID"           /* INVVPID is supported */
2380                 "\011individual"        /* INVVPID individual-address type */
2381                 "\012single"            /* INVVPID single-context type */
2382                 "\013all"               /* INVVPID all-context type */
2383                  /* INVVPID single-context-retaining-globals type */
2384                 "\014single-globals"
2385                 );
2386         }
2387 }
2388
2389 static void
2390 print_hypervisor_info(void)
2391 {
2392
2393         if (*hv_vendor)
2394                 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2395 }