2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
7 * This code is derived from software contributed to Berkeley by
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
46 #include <sys/param.h>
49 #include <sys/eventhandler.h>
50 #include <sys/limits.h>
51 #include <sys/systm.h>
52 #include <sys/kernel.h>
53 #include <sys/sysctl.h>
54 #include <sys/power.h>
56 #include <machine/asmacros.h>
57 #include <machine/clock.h>
58 #include <machine/cputypes.h>
59 #include <machine/frame.h>
60 #include <machine/intr_machdep.h>
61 #include <machine/md_var.h>
62 #include <machine/segments.h>
63 #include <machine/specialreg.h>
65 #include <amd64/vmm/intel/vmx_controls.h>
66 #include <x86/isa/icu.h>
67 #include <x86/vmware.h>
70 #define IDENTBLUE_CYRIX486 0
71 #define IDENTBLUE_IBMCPU 1
72 #define IDENTBLUE_CYRIXM2 2
74 static void identifycyrix(void);
75 static void print_transmeta_info(void);
77 static u_int find_cpu_vendor_id(void);
78 static void print_AMD_info(void);
79 static void print_INTEL_info(void);
80 static void print_INTEL_TLB(u_int data);
81 static void print_hypervisor_info(void);
82 static void print_svm_info(void);
83 static void print_via_padlock_info(void);
84 static void print_vmx_info(void);
87 char machine[] = MACHINE;
91 extern int adaptive_machine_arch;
95 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
98 static const char machine32[] = "i386";
103 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
104 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
107 error = SYSCTL_OUT(req, machine, sizeof(machine));
111 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD,
112 NULL, 0, sysctl_hw_machine, "A", "Machine class");
114 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
115 machine, 0, "Machine class");
118 static char cpu_model[128];
119 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
120 cpu_model, 0, "Machine model");
122 static int hw_clockrate;
123 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
124 &hw_clockrate, 0, "CPU instruction clock rate");
128 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD, hv_vendor, 0,
129 "Hypervisor vendor");
131 static eventhandler_tag tsc_post_tag;
133 static char cpu_brand[48];
136 #define MAX_BRAND_INDEX 8
138 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
142 "Intel Pentium III Xeon",
156 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
157 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
158 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
159 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
160 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
161 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
162 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
163 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
164 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
165 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
166 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
167 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
168 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
169 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
170 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
171 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
172 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
174 { "Clawhammer", CPUCLASS_K8 }, /* CPU_CLAWHAMMER */
175 { "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */
183 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */
184 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */
185 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */
187 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */
188 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */
189 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
190 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */
191 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */
192 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */
193 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */
195 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
196 { "TransmetaCPU", CPU_VENDOR_TRANSMETA },
207 cpu_class = cpus[cpu].cpu_class;
209 strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
211 /* Check for extended CPUID information and a processor name. */
212 if (cpu_exthigh >= 0x80000004) {
214 for (i = 0x80000002; i < 0x80000005; i++) {
216 memcpy(brand, regs, sizeof(regs));
217 brand += sizeof(regs);
221 switch (cpu_vendor_id) {
222 case CPU_VENDOR_INTEL:
224 if ((cpu_id & 0xf00) > 0x300) {
229 switch (cpu_id & 0x3000) {
231 strcpy(cpu_model, "Overdrive ");
234 strcpy(cpu_model, "Dual ");
238 switch (cpu_id & 0xf00) {
240 strcat(cpu_model, "i486 ");
241 /* Check the particular flavor of 486 */
242 switch (cpu_id & 0xf0) {
245 strcat(cpu_model, "DX");
248 strcat(cpu_model, "SX");
251 strcat(cpu_model, "DX2");
254 strcat(cpu_model, "SL");
257 strcat(cpu_model, "SX2");
261 "DX2 Write-Back Enhanced");
264 strcat(cpu_model, "DX4");
269 /* Check the particular flavor of 586 */
270 strcat(cpu_model, "Pentium");
271 switch (cpu_id & 0xf0) {
273 strcat(cpu_model, " A-step");
276 strcat(cpu_model, "/P5");
279 strcat(cpu_model, "/P54C");
282 strcat(cpu_model, "/P24T");
285 strcat(cpu_model, "/P55C");
288 strcat(cpu_model, "/P54C");
291 strcat(cpu_model, "/P55C (quarter-micron)");
297 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
299 * XXX - If/when Intel fixes the bug, this
300 * should also check the version of the
301 * CPU, not just that it's a Pentium.
307 /* Check the particular flavor of 686 */
308 switch (cpu_id & 0xf0) {
310 strcat(cpu_model, "Pentium Pro A-step");
313 strcat(cpu_model, "Pentium Pro");
319 "Pentium II/Pentium II Xeon/Celeron");
327 "Pentium III/Pentium III Xeon/Celeron");
331 strcat(cpu_model, "Unknown 80686");
336 strcat(cpu_model, "Pentium 4");
340 strcat(cpu_model, "unknown");
345 * If we didn't get a brand name from the extended
346 * CPUID, try to look it up in the brand table.
348 if (cpu_high > 0 && *cpu_brand == '\0') {
349 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
350 if (brand_index <= MAX_BRAND_INDEX &&
351 cpu_brandtable[brand_index] != NULL)
353 cpu_brandtable[brand_index]);
357 /* Please make up your mind folks! */
358 strcat(cpu_model, "EM64T");
363 * Values taken from AMD Processor Recognition
364 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
365 * (also describes ``Features'' encodings.
367 strcpy(cpu_model, "AMD ");
369 switch (cpu_id & 0xFF0) {
371 strcat(cpu_model, "Standard Am486DX");
374 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
377 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
380 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
383 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
386 strcat(cpu_model, "Am5x86 Write-Through");
389 strcat(cpu_model, "Am5x86 Write-Back");
392 strcat(cpu_model, "K5 model 0");
395 strcat(cpu_model, "K5 model 1");
398 strcat(cpu_model, "K5 PR166 (model 2)");
401 strcat(cpu_model, "K5 PR200 (model 3)");
404 strcat(cpu_model, "K6");
407 strcat(cpu_model, "K6 266 (model 1)");
410 strcat(cpu_model, "K6-2");
413 strcat(cpu_model, "K6-III");
416 strcat(cpu_model, "Geode LX");
419 strcat(cpu_model, "Unknown");
423 if ((cpu_id & 0xf00) == 0xf00)
424 strcat(cpu_model, "AMD64 Processor");
426 strcat(cpu_model, "Unknown");
430 case CPU_VENDOR_CYRIX:
431 strcpy(cpu_model, "Cyrix ");
432 switch (cpu_id & 0xff0) {
434 strcat(cpu_model, "MediaGX");
437 strcat(cpu_model, "6x86");
440 cpu_class = CPUCLASS_586;
441 strcat(cpu_model, "GXm");
444 strcat(cpu_model, "6x86MX");
448 * Even though CPU supports the cpuid
449 * instruction, it can be disabled.
450 * Therefore, this routine supports all Cyrix
453 switch (cyrix_did & 0xf0) {
455 switch (cyrix_did & 0x0f) {
457 strcat(cpu_model, "486SLC");
460 strcat(cpu_model, "486DLC");
463 strcat(cpu_model, "486SLC2");
466 strcat(cpu_model, "486DLC2");
469 strcat(cpu_model, "486SRx");
472 strcat(cpu_model, "486DRx");
475 strcat(cpu_model, "486SRx2");
478 strcat(cpu_model, "486DRx2");
481 strcat(cpu_model, "486SRu");
484 strcat(cpu_model, "486DRu");
487 strcat(cpu_model, "486SRu2");
490 strcat(cpu_model, "486DRu2");
493 strcat(cpu_model, "Unknown");
498 switch (cyrix_did & 0x0f) {
500 strcat(cpu_model, "486S");
503 strcat(cpu_model, "486S2");
506 strcat(cpu_model, "486Se");
509 strcat(cpu_model, "486S2e");
512 strcat(cpu_model, "486DX");
515 strcat(cpu_model, "486DX2");
518 strcat(cpu_model, "486DX4");
521 strcat(cpu_model, "Unknown");
526 if ((cyrix_did & 0x0f) < 8)
527 strcat(cpu_model, "6x86"); /* Where did you get it? */
529 strcat(cpu_model, "5x86");
532 strcat(cpu_model, "6x86");
535 if ((cyrix_did & 0xf000) == 0x3000) {
536 cpu_class = CPUCLASS_586;
537 strcat(cpu_model, "GXm");
539 strcat(cpu_model, "MediaGX");
542 strcat(cpu_model, "6x86MX");
545 switch (cyrix_did & 0x0f) {
547 strcat(cpu_model, "Overdrive CPU");
550 strcpy(cpu_model, "Texas Instruments 486SXL");
553 strcat(cpu_model, "486SLC/DLC");
556 strcat(cpu_model, "Unknown");
561 strcat(cpu_model, "Unknown");
567 case CPU_VENDOR_RISE:
568 strcpy(cpu_model, "Rise ");
569 switch (cpu_id & 0xff0) {
570 case 0x500: /* 6401 and 6441 (Kirin) */
571 case 0x520: /* 6510 (Lynx) */
572 strcat(cpu_model, "mP6");
575 strcat(cpu_model, "Unknown");
579 case CPU_VENDOR_CENTAUR:
581 switch (cpu_id & 0xff0) {
583 strcpy(cpu_model, "IDT WinChip C6");
586 strcpy(cpu_model, "IDT WinChip 2");
589 strcpy(cpu_model, "IDT WinChip 3");
592 strcpy(cpu_model, "VIA C3 Samuel");
596 strcpy(cpu_model, "VIA C3 Ezra");
598 strcpy(cpu_model, "VIA C3 Samuel 2");
601 strcpy(cpu_model, "VIA C3 Ezra-T");
604 strcpy(cpu_model, "VIA C3 Nehemiah");
608 strcpy(cpu_model, "VIA C7 Esther");
611 strcpy(cpu_model, "VIA Nano");
614 strcpy(cpu_model, "VIA/IDT Unknown");
617 strcpy(cpu_model, "VIA ");
618 if ((cpu_id & 0xff0) == 0x6f0)
619 strcat(cpu_model, "Nano Processor");
621 strcat(cpu_model, "Unknown");
626 strcpy(cpu_model, "Blue Lightning CPU");
629 switch (cpu_id & 0xff0) {
631 strcpy(cpu_model, "Geode SC1100");
635 strcpy(cpu_model, "Geode/NSC unknown");
641 strcat(cpu_model, "Unknown");
646 * Replace cpu_model with cpu_brand minus leading spaces if
650 while (*brand == ' ')
653 strcpy(cpu_model, brand);
655 printf("%s (", cpu_model);
657 hw_clockrate = (tsc_freq + 5000) / 1000000;
658 printf("%jd.%02d-MHz ",
659 (intmax_t)(tsc_freq + 4999) / 1000000,
660 (u_int)((tsc_freq + 4999) / 10000) % 100);
670 #if defined(I486_CPU)
675 #if defined(I586_CPU)
680 #if defined(I686_CPU)
691 printf("Unknown"); /* will panic below... */
693 printf("-class CPU)\n");
695 printf(" Origin=\"%s\"", cpu_vendor);
697 printf(" Id=0x%x", cpu_id);
699 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
700 cpu_vendor_id == CPU_VENDOR_AMD ||
701 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
703 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
704 cpu_vendor_id == CPU_VENDOR_RISE ||
705 cpu_vendor_id == CPU_VENDOR_NSC ||
706 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
709 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id));
710 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id));
711 printf(" Stepping=%u", cpu_id & CPUID_STEPPING);
713 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
714 printf("\n DIR=0x%04x", cyrix_did);
718 * AMD CPUID Specification
719 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
721 * Intel Processor Identification and CPUID Instruction
722 * http://www.intel.com/assets/pdf/appnote/241618.pdf
727 * Here we should probably set up flags indicating
728 * whether or not various features are available.
729 * The interesting ones are probably VME, PSE, PAE,
730 * and PGE. The code already assumes without bothering
731 * to check that all CPUs >= Pentium have a TSC and
734 printf("\n Features=0x%b", cpu_feature,
736 "\001FPU" /* Integral FPU */
737 "\002VME" /* Extended VM86 mode support */
738 "\003DE" /* Debugging Extensions (CR4.DE) */
739 "\004PSE" /* 4MByte page tables */
740 "\005TSC" /* Timestamp counter */
741 "\006MSR" /* Machine specific registers */
742 "\007PAE" /* Physical address extension */
743 "\010MCE" /* Machine Check support */
744 "\011CX8" /* CMPEXCH8 instruction */
745 "\012APIC" /* SMP local APIC */
746 "\013oldMTRR" /* Previous implementation of MTRR */
747 "\014SEP" /* Fast System Call */
748 "\015MTRR" /* Memory Type Range Registers */
749 "\016PGE" /* PG_G (global bit) support */
750 "\017MCA" /* Machine Check Architecture */
751 "\020CMOV" /* CMOV instruction */
752 "\021PAT" /* Page attributes table */
753 "\022PSE36" /* 36 bit address space support */
754 "\023PN" /* Processor Serial number */
755 "\024CLFLUSH" /* Has the CLFLUSH instruction */
757 "\026DTS" /* Debug Trace Store */
758 "\027ACPI" /* ACPI support */
759 "\030MMX" /* MMX instructions */
760 "\031FXSR" /* FXSAVE/FXRSTOR */
761 "\032SSE" /* Streaming SIMD Extensions */
762 "\033SSE2" /* Streaming SIMD Extensions #2 */
763 "\034SS" /* Self snoop */
764 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
765 "\036TM" /* Thermal Monitor clock slowdown */
766 "\037IA64" /* CPU can execute IA64 instructions */
767 "\040PBE" /* Pending Break Enable */
770 if (cpu_feature2 != 0) {
771 printf("\n Features2=0x%b", cpu_feature2,
773 "\001SSE3" /* SSE3 */
774 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
775 "\003DTES64" /* 64-bit Debug Trace */
776 "\004MON" /* MONITOR/MWAIT Instructions */
777 "\005DS_CPL" /* CPL Qualified Debug Store */
778 "\006VMX" /* Virtual Machine Extensions */
779 "\007SMX" /* Safer Mode Extensions */
780 "\010EST" /* Enhanced SpeedStep */
781 "\011TM2" /* Thermal Monitor 2 */
782 "\012SSSE3" /* SSSE3 */
783 "\013CNXT-ID" /* L1 context ID available */
784 "\014SDBG" /* IA32 silicon debug */
785 "\015FMA" /* Fused Multiply Add */
786 "\016CX16" /* CMPXCHG16B Instruction */
787 "\017xTPR" /* Send Task Priority Messages*/
788 "\020PDCM" /* Perf/Debug Capability MSR */
790 "\022PCID" /* Process-context Identifiers*/
791 "\023DCA" /* Direct Cache Access */
792 "\024SSE4.1" /* SSE 4.1 */
793 "\025SSE4.2" /* SSE 4.2 */
794 "\026x2APIC" /* xAPIC Extensions */
795 "\027MOVBE" /* MOVBE Instruction */
796 "\030POPCNT" /* POPCNT Instruction */
797 "\031TSCDLT" /* TSC-Deadline Timer */
798 "\032AESNI" /* AES Crypto */
799 "\033XSAVE" /* XSAVE/XRSTOR States */
800 "\034OSXSAVE" /* OS-Enabled State Management*/
801 "\035AVX" /* Advanced Vector Extensions */
802 "\036F16C" /* Half-precision conversions */
803 "\037RDRAND" /* RDRAND Instruction */
804 "\040HV" /* Hypervisor */
808 if (amd_feature != 0) {
809 printf("\n AMD Features=0x%b", amd_feature,
811 "\001<s0>" /* Same */
812 "\002<s1>" /* Same */
813 "\003<s2>" /* Same */
814 "\004<s3>" /* Same */
815 "\005<s4>" /* Same */
816 "\006<s5>" /* Same */
817 "\007<s6>" /* Same */
818 "\010<s7>" /* Same */
819 "\011<s8>" /* Same */
820 "\012<s9>" /* Same */
821 "\013<b10>" /* Undefined */
822 "\014SYSCALL" /* Have SYSCALL/SYSRET */
823 "\015<s12>" /* Same */
824 "\016<s13>" /* Same */
825 "\017<s14>" /* Same */
826 "\020<s15>" /* Same */
827 "\021<s16>" /* Same */
828 "\022<s17>" /* Same */
829 "\023<b18>" /* Reserved, unknown */
830 "\024MP" /* Multiprocessor Capable */
831 "\025NX" /* Has EFER.NXE, NX */
832 "\026<b21>" /* Undefined */
833 "\027MMX+" /* AMD MMX Extensions */
834 "\030<s23>" /* Same */
835 "\031<s24>" /* Same */
836 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */
837 "\033Page1GB" /* 1-GB large page support */
838 "\034RDTSCP" /* RDTSCP */
839 "\035<b28>" /* Undefined */
840 "\036LM" /* 64 bit long mode */
841 "\0373DNow!+" /* AMD 3DNow! Extensions */
842 "\0403DNow!" /* AMD 3DNow! */
846 if (amd_feature2 != 0) {
847 printf("\n AMD Features2=0x%b", amd_feature2,
849 "\001LAHF" /* LAHF/SAHF in long mode */
850 "\002CMP" /* CMP legacy */
851 "\003SVM" /* Secure Virtual Mode */
852 "\004ExtAPIC" /* Extended APIC register */
853 "\005CR8" /* CR8 in legacy mode */
854 "\006ABM" /* LZCNT instruction */
855 "\007SSE4A" /* SSE4A */
856 "\010MAS" /* Misaligned SSE mode */
857 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
858 "\012OSVW" /* OS visible workaround */
859 "\013IBS" /* Instruction based sampling */
860 "\014XOP" /* XOP extended instructions */
861 "\015SKINIT" /* SKINIT/STGI */
862 "\016WDT" /* Watchdog timer */
864 "\020LWP" /* Lightweight Profiling */
865 "\021FMA4" /* 4-operand FMA instructions */
866 "\022TCE" /* Translation Cache Extension */
868 "\024NodeId" /* NodeId MSR support */
870 "\026TBM" /* Trailing Bit Manipulation */
871 "\027Topology" /* Topology Extensions */
872 "\030PCXC" /* Core perf count */
873 "\031PNXC" /* NB perf count */
875 "\033DBE" /* Data Breakpoint extension */
876 "\034PTSC" /* Performance TSC */
877 "\035PL2I" /* L2I perf count */
884 if (cpu_stdext_feature != 0) {
885 printf("\n Structured Extended Features=0x%b",
888 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
891 /* Bit Manipulation Instructions */
893 /* Hardware Lock Elision */
895 /* Advanced Vector Instructions 2 */
897 /* FDP_EXCPTN_ONLY */
899 /* Supervisor Mode Execution Prot. */
901 /* Bit Manipulation Instructions */
904 /* Invalidate Processor Context ID */
906 /* Restricted Transactional Memory */
911 /* Intel Memory Protection Extensions */
913 /* AVX512 Foundation */
919 /* Supervisor Mode Access Prevention */
930 if (cpu_stdext_feature2 != 0) {
931 printf("\n Structured Extended Features2=0x%b",
940 if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
941 cpuid_count(0xd, 0x1, regs);
943 printf("\n XSAVE Features=0x%b",
953 if (via_feature_rng != 0 || via_feature_xcrypt != 0)
954 print_via_padlock_info();
956 if (cpu_feature2 & CPUID2_VMX)
959 if (amd_feature2 & AMDID2_SVM)
962 if ((cpu_feature & CPUID_HTT) &&
963 cpu_vendor_id == CPU_VENDOR_AMD)
964 cpu_feature &= ~CPUID_HTT;
967 * If this CPU supports P-state invariant TSC then
968 * mention the capability.
970 if (tsc_is_invariant) {
971 printf("\n TSC: P-state invariant");
973 printf(", performance statistics");
977 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
978 printf(" DIR=0x%04x", cyrix_did);
979 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
980 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
981 #ifndef CYRIX_CACHE_REALLY_WORKS
982 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
983 printf("\n CPU cache: write-through mode");
988 /* Avoid ugly blank lines: only print newline when we have to. */
989 if (*cpu_vendor || cpu_id)
993 if (cpu_vendor_id == CPU_VENDOR_AMD)
995 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
998 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
999 print_transmeta_info();
1003 print_hypervisor_info();
1007 panicifcpuunsupported(void)
1012 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1013 #error This kernel is not configured for one of the supported CPUs
1017 #else /* __amd64__ */
1019 #error "You need to specify a cpu type"
1023 * Now that we have told the user what they have,
1024 * let them know if that machine type isn't configured.
1026 switch (cpu_class) {
1028 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
1030 #if !defined(I486_CPU)
1033 #if !defined(I586_CPU)
1036 #if !defined(I686_CPU)
1039 #else /* __amd64__ */
1045 panic("CPU class not configured");
1052 static volatile u_int trap_by_rdmsr;
1055 * Special exception 6 handler.
1056 * The rdmsr instruction generates invalid opcodes fault on 486-class
1057 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
1058 * function identblue() when this handler is called. Stacked eip should
1061 inthand_t bluetrap6;
1062 #ifdef __GNUCLIKE_ASM
1067 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\
1068 " __XSTRING(CNAME(bluetrap6)) ": \n\
1070 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1071 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1077 * Special exception 13 handler.
1078 * Accessing non-existent MSR generates general protection fault.
1080 inthand_t bluetrap13;
1081 #ifdef __GNUCLIKE_ASM
1086 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\
1087 " __XSTRING(CNAME(bluetrap13)) ": \n\
1089 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1090 popl %eax /* discard error code */ \n\
1091 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1097 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1098 * support cpuid instruction. This function should be called after
1099 * loading interrupt descriptor table register.
1101 * I don't like this method that handles fault, but I couldn't get
1102 * information for any other methods. Does blue giant know?
1111 * Cyrix 486-class CPU does not support rdmsr instruction.
1112 * The rdmsr instruction generates invalid opcode fault, and exception
1113 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
1114 * bluetrap6() set the magic number to trap_by_rdmsr.
1116 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1117 GSEL(GCODE_SEL, SEL_KPL));
1120 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1121 * In this case, rdmsr generates general protection fault, and
1122 * exception will be trapped by bluetrap13().
1124 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1125 GSEL(GCODE_SEL, SEL_KPL));
1127 rdmsr(0x1002); /* Cyrix CPU generates fault. */
1129 if (trap_by_rdmsr == 0xa8c1d)
1130 return IDENTBLUE_CYRIX486;
1131 else if (trap_by_rdmsr == 0xa89c4)
1132 return IDENTBLUE_CYRIXM2;
1133 return IDENTBLUE_IBMCPU;
1138 * identifycyrix() set lower 16 bits of cyrix_did as follows:
1140 * F E D C B A 9 8 7 6 5 4 3 2 1 0
1141 * +-------+-------+---------------+
1142 * | SID | RID | Device ID |
1143 * | (DIR 1) | (DIR 0) |
1144 * +-------+-------+---------------+
1149 register_t saveintr;
1150 int ccr2_test = 0, dir_test = 0;
1153 saveintr = intr_disable();
1155 ccr2 = read_cyrix_reg(CCR2);
1156 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1157 read_cyrix_reg(CCR2);
1158 if (read_cyrix_reg(CCR2) != ccr2)
1160 write_cyrix_reg(CCR2, ccr2);
1162 ccr3 = read_cyrix_reg(CCR3);
1163 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1164 read_cyrix_reg(CCR3);
1165 if (read_cyrix_reg(CCR3) != ccr3)
1166 dir_test = 1; /* CPU supports DIRs. */
1167 write_cyrix_reg(CCR3, ccr3);
1170 /* Device ID registers are available. */
1171 cyrix_did = read_cyrix_reg(DIR1) << 8;
1172 cyrix_did += read_cyrix_reg(DIR0);
1173 } else if (ccr2_test)
1174 cyrix_did = 0x0010; /* 486S A-step */
1176 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
1178 intr_restore(saveintr);
1182 /* Update TSC freq with the value indicated by the caller. */
1184 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1187 /* If there was an error during the transition, don't do anything. */
1191 /* Total setting for this level gives the new frequency in MHz. */
1192 hw_clockrate = level->total_set.freq;
1196 hook_tsc_freq(void *arg __unused)
1199 if (tsc_is_invariant)
1202 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1203 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1206 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1209 static const char *const vm_bnames[] = {
1211 "Plex86", /* Plex86 */
1212 "Bochs", /* Bochs */
1214 "BHYVE", /* bhyve */
1215 "Seabios", /* KVM */
1219 static const char *const vm_pnames[] = {
1220 "VMware Virtual Platform", /* VMWare VM */
1221 "Virtual Machine", /* Microsoft VirtualPC */
1222 "VirtualBox", /* Sun xVM VirtualBox */
1223 "Parallels Virtual Platform", /* Parallels VM */
1229 identify_hypervisor(void)
1236 * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1237 * http://lkml.org/lkml/2008/10/1/246
1239 * KB1009458: Mechanisms to determine if software is running in
1240 * a VMware virtual machine
1241 * http://kb.vmware.com/kb/1009458
1243 if (cpu_feature2 & CPUID2_HV) {
1244 vm_guest = VM_GUEST_VM;
1245 do_cpuid(0x40000000, regs);
1246 if (regs[0] >= 0x40000000) {
1248 ((u_int *)&hv_vendor)[0] = regs[1];
1249 ((u_int *)&hv_vendor)[1] = regs[2];
1250 ((u_int *)&hv_vendor)[2] = regs[3];
1251 hv_vendor[12] = '\0';
1252 if (strcmp(hv_vendor, "VMwareVMware") == 0)
1253 vm_guest = VM_GUEST_VMWARE;
1259 * Examine SMBIOS strings for older hypervisors.
1261 p = getenv("smbios.system.serial");
1263 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1264 vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1265 if (regs[1] == VMW_HVMAGIC) {
1266 vm_guest = VM_GUEST_VMWARE;
1275 * XXX: Some of these entries may not be needed since they were
1276 * added to FreeBSD before the checks above.
1278 p = getenv("smbios.bios.vendor");
1280 for (i = 0; vm_bnames[i] != NULL; i++)
1281 if (strcmp(p, vm_bnames[i]) == 0) {
1282 vm_guest = VM_GUEST_VM;
1288 p = getenv("smbios.system.product");
1290 for (i = 0; vm_pnames[i] != NULL; i++)
1291 if (strcmp(p, vm_pnames[i]) == 0) {
1292 vm_guest = VM_GUEST_VM;
1302 * Clear "Limit CPUID Maxval" bit and return true if the caller should
1303 * get the largest standard CPUID function number again if it is set
1304 * from BIOS. It is necessary for probing correct CPU topology later
1305 * and for the correct operation of the AVX-aware userspace.
1308 intel_fix_cpuid(void)
1312 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1314 if ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1315 CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1316 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1317 CPUID_TO_MODEL(cpu_id) >= 0xe)) {
1318 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1319 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1320 msr &= ~IA32_MISC_EN_LIMCPUID;
1321 wrmsr(MSR_IA32_MISC_ENABLE, msr);
1329 * Final stage of CPU identification.
1333 finishidentcpu(void)
1339 u_int regs[4], cpu_stdext_disable;
1347 ((u_int *)&cpu_vendor)[0] = regs[1];
1348 ((u_int *)&cpu_vendor)[1] = regs[3];
1349 ((u_int *)&cpu_vendor)[2] = regs[2];
1350 cpu_vendor[12] = '\0';
1354 cpu_procinfo = regs[1];
1355 cpu_feature = regs[3];
1356 cpu_feature2 = regs[2];
1360 identify_hypervisor();
1362 cpu_vendor_id = find_cpu_vendor_id();
1364 if (intel_fix_cpuid()) {
1369 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1371 cpu_mon_mwait_flags = regs[2];
1372 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE;
1373 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE;
1376 if (cpu_high >= 7) {
1377 cpuid_count(7, 0, regs);
1378 cpu_stdext_feature = regs[1];
1381 * Some hypervisors fail to filter out unsupported
1382 * extended features. For now, disable the
1383 * extensions, activation of which requires setting a
1384 * bit in CR4, and which VM monitors do not support.
1386 if (cpu_feature2 & CPUID2_HV) {
1387 cpu_stdext_disable = CPUID_STDEXT_FSGSBASE |
1390 cpu_stdext_disable = 0;
1391 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1392 cpu_stdext_feature &= ~cpu_stdext_disable;
1393 cpu_stdext_feature2 = regs[2];
1398 (cpu_vendor_id == CPU_VENDOR_INTEL ||
1399 cpu_vendor_id == CPU_VENDOR_AMD ||
1400 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1401 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1402 cpu_vendor_id == CPU_VENDOR_NSC)) {
1403 do_cpuid(0x80000000, regs);
1404 if (regs[0] >= 0x80000000)
1405 cpu_exthigh = regs[0];
1408 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1409 cpu_vendor_id == CPU_VENDOR_AMD ||
1410 cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1411 do_cpuid(0x80000000, regs);
1412 cpu_exthigh = regs[0];
1415 if (cpu_exthigh >= 0x80000001) {
1416 do_cpuid(0x80000001, regs);
1417 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1418 amd_feature2 = regs[2];
1420 if (cpu_exthigh >= 0x80000007) {
1421 do_cpuid(0x80000007, regs);
1422 amd_pminfo = regs[3];
1424 if (cpu_exthigh >= 0x80000008) {
1425 do_cpuid(0x80000008, regs);
1426 cpu_maxphyaddr = regs[0] & 0xff;
1427 cpu_procinfo2 = regs[2];
1429 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1433 if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1434 if (cpu == CPU_486) {
1436 * These conditions are equivalent to:
1437 * - CPU does not support cpuid instruction.
1438 * - Cyrix/IBM CPU is detected.
1440 if (identblue() == IDENTBLUE_IBMCPU) {
1441 strcpy(cpu_vendor, "IBM");
1442 cpu_vendor_id = CPU_VENDOR_IBM;
1447 switch (cpu_id & 0xf00) {
1450 * Cyrix's datasheet does not describe DIRs.
1451 * Therefor, I assume it does not have them
1452 * and use the result of the cpuid instruction.
1453 * XXX they seem to have it for now at least. -Peter
1461 * This routine contains a trick.
1462 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1464 switch (cyrix_did & 0x00f0) {
1473 if ((cyrix_did & 0x000f) < 8)
1486 /* M2 and later CPUs are treated as M2. */
1490 * enable cpuid instruction.
1492 ccr3 = read_cyrix_reg(CCR3);
1493 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1494 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1495 write_cyrix_reg(CCR3, ccr3);
1498 cpu_high = regs[0]; /* eax */
1500 cpu_id = regs[0]; /* eax */
1501 cpu_feature = regs[3]; /* edx */
1505 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1507 * There are BlueLightning CPUs that do not change
1508 * undefined flags by dividing 5 by 2. In this case,
1509 * the CPU identification routine in locore.s leaves
1510 * cpu_vendor null string and puts CPU_486 into the
1513 if (identblue() == IDENTBLUE_IBMCPU) {
1514 strcpy(cpu_vendor, "IBM");
1515 cpu_vendor_id = CPU_VENDOR_IBM;
1522 cpu = CPU_CLAWHAMMER;
1527 find_cpu_vendor_id(void)
1531 for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++)
1532 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1533 return (cpu_vendors[i].vendor_id);
1538 print_AMD_assoc(int i)
1541 printf(", fully associative\n");
1543 printf(", %d-way associative\n", i);
1547 print_AMD_l2_assoc(int i)
1550 case 0: printf(", disabled/not present\n"); break;
1551 case 1: printf(", direct mapped\n"); break;
1552 case 2: printf(", 2-way associative\n"); break;
1553 case 4: printf(", 4-way associative\n"); break;
1554 case 6: printf(", 8-way associative\n"); break;
1555 case 8: printf(", 16-way associative\n"); break;
1556 case 15: printf(", fully associative\n"); break;
1557 default: printf(", reserved configuration\n"); break;
1562 print_AMD_info(void)
1569 if (cpu_exthigh >= 0x80000005) {
1570 do_cpuid(0x80000005, regs);
1571 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1572 print_AMD_assoc(regs[0] >> 24);
1574 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1575 print_AMD_assoc((regs[0] >> 8) & 0xff);
1577 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1578 print_AMD_assoc(regs[1] >> 24);
1580 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1581 print_AMD_assoc((regs[1] >> 8) & 0xff);
1583 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1584 printf(", %d bytes/line", regs[2] & 0xff);
1585 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1586 print_AMD_assoc((regs[2] >> 16) & 0xff);
1588 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1589 printf(", %d bytes/line", regs[3] & 0xff);
1590 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1591 print_AMD_assoc((regs[3] >> 16) & 0xff);
1594 if (cpu_exthigh >= 0x80000006) {
1595 do_cpuid(0x80000006, regs);
1596 if ((regs[0] >> 16) != 0) {
1597 printf("L2 2MB data TLB: %d entries",
1598 (regs[0] >> 16) & 0xfff);
1599 print_AMD_l2_assoc(regs[0] >> 28);
1600 printf("L2 2MB instruction TLB: %d entries",
1602 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1604 printf("L2 2MB unified TLB: %d entries",
1606 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1608 if ((regs[1] >> 16) != 0) {
1609 printf("L2 4KB data TLB: %d entries",
1610 (regs[1] >> 16) & 0xfff);
1611 print_AMD_l2_assoc(regs[1] >> 28);
1613 printf("L2 4KB instruction TLB: %d entries",
1614 (regs[1] >> 16) & 0xfff);
1615 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1617 printf("L2 4KB unified TLB: %d entries",
1618 (regs[1] >> 16) & 0xfff);
1619 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1621 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1622 printf(", %d bytes/line", regs[2] & 0xff);
1623 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1624 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1628 if (((cpu_id & 0xf00) == 0x500)
1629 && (((cpu_id & 0x0f0) > 0x80)
1630 || (((cpu_id & 0x0f0) == 0x80)
1631 && (cpu_id & 0x00f) > 0x07))) {
1632 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1633 amd_whcr = rdmsr(0xc0000082);
1634 if (!(amd_whcr & (0x3ff << 22))) {
1635 printf("Write Allocate Disable\n");
1637 printf("Write Allocate Enable Limit: %dM bytes\n",
1638 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1639 printf("Write Allocate 15-16M bytes: %s\n",
1640 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1642 } else if (((cpu_id & 0xf00) == 0x500)
1643 && ((cpu_id & 0x0f0) > 0x50)) {
1644 /* K6, K6-2(old core) */
1645 amd_whcr = rdmsr(0xc0000082);
1646 if (!(amd_whcr & (0x7f << 1))) {
1647 printf("Write Allocate Disable\n");
1649 printf("Write Allocate Enable Limit: %dM bytes\n",
1650 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1651 printf("Write Allocate 15-16M bytes: %s\n",
1652 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1653 printf("Hardware Write Allocate Control: %s\n",
1654 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1659 * Opteron Rev E shows a bug as in very rare occasions a read memory
1660 * barrier is not performed as expected if it is followed by a
1661 * non-atomic read-modify-write instruction.
1662 * As long as that bug pops up very rarely (intensive machine usage
1663 * on other operating systems generally generates one unexplainable
1664 * crash any 2 months) and as long as a model specific fix would be
1665 * impratical at this stage, print out a warning string if the broken
1666 * model and family are identified.
1668 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1669 CPUID_TO_MODEL(cpu_id) <= 0x3f)
1670 printf("WARNING: This architecture revision has known SMP "
1671 "hardware bugs which may cause random instability\n");
1675 print_INTEL_info(void)
1678 u_int rounds, regnum;
1679 u_int nwaycode, nway;
1681 if (cpu_high >= 2) {
1684 do_cpuid(0x2, regs);
1685 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1686 break; /* we have a buggy CPU */
1688 for (regnum = 0; regnum <= 3; ++regnum) {
1689 if (regs[regnum] & (1<<31))
1692 print_INTEL_TLB(regs[regnum] & 0xff);
1693 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1694 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1695 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1697 } while (--rounds > 0);
1700 if (cpu_exthigh >= 0x80000006) {
1701 do_cpuid(0x80000006, regs);
1702 nwaycode = (regs[2] >> 12) & 0x0f;
1703 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1704 nway = 1 << (nwaycode / 2);
1707 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1708 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1713 print_INTEL_TLB(u_int data)
1721 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1724 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1727 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1730 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1733 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1736 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
1739 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
1742 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
1745 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
1748 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
1751 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
1754 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
1757 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
1760 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
1763 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1766 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1769 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
1772 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1775 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1778 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
1781 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
1783 case 0x39: /* De-listed in SDM rev. 54 */
1784 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1786 case 0x3b: /* De-listed in SDM rev. 54 */
1787 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
1789 case 0x3c: /* De-listed in SDM rev. 54 */
1790 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1793 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
1796 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
1799 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
1802 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
1805 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
1808 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
1811 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
1814 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
1817 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
1818 CPUID_TO_MODEL(cpu_id) == 0x6)
1819 printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
1821 printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
1824 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
1827 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
1830 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
1833 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
1836 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
1839 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
1842 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
1845 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
1848 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
1851 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
1854 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
1857 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
1860 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
1863 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
1866 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
1869 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
1872 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
1875 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1878 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
1881 printf("Data TLB: 1 GByte pages, 4-way set associative, 4 entries\n");
1884 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1887 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1890 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
1893 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
1896 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
1899 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
1902 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
1905 printf("Trace cache: 12K-uops, 8-way set associative\n");
1908 printf("Trace cache: 16K-uops, 8-way set associative\n");
1911 printf("Trace cache: 32K-uops, 8-way set associative\n");
1914 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
1917 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
1920 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1923 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1926 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1929 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1932 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
1935 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
1938 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
1941 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
1944 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
1947 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
1950 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
1953 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
1956 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
1959 printf("DTLB: 4k pages, fully associative, 32 entries\n");
1962 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
1965 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
1968 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
1971 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
1974 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
1977 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
1980 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
1983 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
1986 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
1989 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
1992 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
1995 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
1998 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2001 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2004 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2007 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2010 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2013 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2016 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2019 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2022 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2025 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2028 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2031 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2034 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2037 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2040 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2043 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2046 printf("64-Byte prefetching\n");
2049 printf("128-Byte prefetching\n");
2055 print_svm_info(void)
2057 u_int features, regs[4];
2062 do_cpuid(0x8000000A, regs);
2065 msr = rdmsr(MSR_VM_CR);
2066 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2067 printf("(disabled in BIOS) ");
2071 if (features & (1 << 0)) {
2072 printf("%sNP", comma ? "," : "");
2075 if (features & (1 << 3)) {
2076 printf("%sNRIP", comma ? "," : "");
2079 if (features & (1 << 5)) {
2080 printf("%sVClean", comma ? "," : "");
2083 if (features & (1 << 6)) {
2084 printf("%sAFlush", comma ? "," : "");
2087 if (features & (1 << 7)) {
2088 printf("%sDAssist", comma ? "," : "");
2091 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2095 printf("Features=0x%b", features,
2097 "\001NP" /* Nested paging */
2098 "\002LbrVirt" /* LBR virtualization */
2099 "\003SVML" /* SVM lock */
2100 "\004NRIPS" /* NRIP save */
2101 "\005TscRateMsr" /* MSR based TSC rate control */
2102 "\006VmcbClean" /* VMCB clean bits */
2103 "\007FlushByAsid" /* Flush by ASID */
2104 "\010DecodeAssist" /* Decode assist */
2107 "\013PauseFilter" /* PAUSE intercept filter */
2109 "\015PauseFilterThreshold" /* PAUSE filter threshold */
2110 "\016AVIC" /* virtual interrupt controller */
2112 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2117 print_transmeta_info(void)
2119 u_int regs[4], nreg = 0;
2121 do_cpuid(0x80860000, regs);
2123 if (nreg >= 0x80860001) {
2124 do_cpuid(0x80860001, regs);
2125 printf(" Processor revision %u.%u.%u.%u\n",
2126 (regs[1] >> 24) & 0xff,
2127 (regs[1] >> 16) & 0xff,
2128 (regs[1] >> 8) & 0xff,
2131 if (nreg >= 0x80860002) {
2132 do_cpuid(0x80860002, regs);
2133 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
2134 (regs[1] >> 24) & 0xff,
2135 (regs[1] >> 16) & 0xff,
2136 (regs[1] >> 8) & 0xff,
2140 if (nreg >= 0x80860006) {
2142 do_cpuid(0x80860003, (u_int*) &info[0]);
2143 do_cpuid(0x80860004, (u_int*) &info[16]);
2144 do_cpuid(0x80860005, (u_int*) &info[32]);
2145 do_cpuid(0x80860006, (u_int*) &info[48]);
2147 printf(" %s\n", info);
2153 print_via_padlock_info(void)
2157 do_cpuid(0xc0000001, regs);
2158 printf("\n VIA Padlock Features=0x%b", regs[3],
2162 "\011AES-CTR" /* ACE2 */
2163 "\013SHA1,SHA256" /* PHE */
2169 vmx_settable(uint64_t basic, int msr, int true_msr)
2173 if (basic & (1ULL << 55))
2174 val = rdmsr(true_msr);
2178 /* Just report the controls that can be set to 1. */
2183 print_vmx_info(void)
2185 uint64_t basic, msr;
2186 uint32_t entry, exit, mask, pin, proc, proc2;
2189 printf("\n VT-x: ");
2190 msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2191 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2192 printf("(disabled in BIOS) ");
2193 basic = rdmsr(MSR_VMX_BASIC);
2194 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2195 MSR_VMX_TRUE_PINBASED_CTLS);
2196 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2197 MSR_VMX_TRUE_PROCBASED_CTLS);
2198 if (proc & PROCBASED_SECONDARY_CONTROLS)
2199 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2200 MSR_VMX_PROCBASED_CTLS2);
2203 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2204 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2208 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2209 entry & VM_ENTRY_LOAD_PAT) {
2210 printf("%sPAT", comma ? "," : "");
2213 if (proc & PROCBASED_HLT_EXITING) {
2214 printf("%sHLT", comma ? "," : "");
2217 if (proc & PROCBASED_MTF) {
2218 printf("%sMTF", comma ? "," : "");
2221 if (proc & PROCBASED_PAUSE_EXITING) {
2222 printf("%sPAUSE", comma ? "," : "");
2225 if (proc2 & PROCBASED2_ENABLE_EPT) {
2226 printf("%sEPT", comma ? "," : "");
2229 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2230 printf("%sUG", comma ? "," : "");
2233 if (proc2 & PROCBASED2_ENABLE_VPID) {
2234 printf("%sVPID", comma ? "," : "");
2237 if (proc & PROCBASED_USE_TPR_SHADOW &&
2238 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2239 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2240 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2241 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2242 printf("%sVID", comma ? "," : "");
2244 if (pin & PINBASED_POSTED_INTERRUPT)
2245 printf(",PostIntr");
2251 printf("Basic Features=0x%b", mask,
2253 "\02132PA" /* 32-bit physical addresses */
2254 "\022SMM" /* SMM dual-monitor */
2255 "\027INS/OUTS" /* VM-exit info for INS and OUTS */
2256 "\030TRUE" /* TRUE_CTLS MSRs */
2258 printf("\n Pin-Based Controls=0x%b", pin,
2260 "\001ExtINT" /* External-interrupt exiting */
2261 "\004NMI" /* NMI exiting */
2262 "\006VNMI" /* Virtual NMIs */
2263 "\007PreTmr" /* Activate VMX-preemption timer */
2264 "\010PostIntr" /* Process posted interrupts */
2266 printf("\n Primary Processor Controls=0x%b", proc,
2268 "\003INTWIN" /* Interrupt-window exiting */
2269 "\004TSCOff" /* Use TSC offsetting */
2270 "\010HLT" /* HLT exiting */
2271 "\012INVLPG" /* INVLPG exiting */
2272 "\013MWAIT" /* MWAIT exiting */
2273 "\014RDPMC" /* RDPMC exiting */
2274 "\015RDTSC" /* RDTSC exiting */
2275 "\020CR3-LD" /* CR3-load exiting */
2276 "\021CR3-ST" /* CR3-store exiting */
2277 "\024CR8-LD" /* CR8-load exiting */
2278 "\025CR8-ST" /* CR8-store exiting */
2279 "\026TPR" /* Use TPR shadow */
2280 "\027NMIWIN" /* NMI-window exiting */
2281 "\030MOV-DR" /* MOV-DR exiting */
2282 "\031IO" /* Unconditional I/O exiting */
2283 "\032IOmap" /* Use I/O bitmaps */
2284 "\034MTF" /* Monitor trap flag */
2285 "\035MSRmap" /* Use MSR bitmaps */
2286 "\036MONITOR" /* MONITOR exiting */
2287 "\037PAUSE" /* PAUSE exiting */
2289 if (proc & PROCBASED_SECONDARY_CONTROLS)
2290 printf("\n Secondary Processor Controls=0x%b", proc2,
2292 "\001APIC" /* Virtualize APIC accesses */
2293 "\002EPT" /* Enable EPT */
2294 "\003DT" /* Descriptor-table exiting */
2295 "\004RDTSCP" /* Enable RDTSCP */
2296 "\005x2APIC" /* Virtualize x2APIC mode */
2297 "\006VPID" /* Enable VPID */
2298 "\007WBINVD" /* WBINVD exiting */
2299 "\010UG" /* Unrestricted guest */
2300 "\011APIC-reg" /* APIC-register virtualization */
2301 "\012VID" /* Virtual-interrupt delivery */
2302 "\013PAUSE-loop" /* PAUSE-loop exiting */
2303 "\014RDRAND" /* RDRAND exiting */
2304 "\015INVPCID" /* Enable INVPCID */
2305 "\016VMFUNC" /* Enable VM functions */
2306 "\017VMCS" /* VMCS shadowing */
2307 "\020EPT#VE" /* EPT-violation #VE */
2308 "\021XSAVES" /* Enable XSAVES/XRSTORS */
2310 printf("\n Exit Controls=0x%b", mask,
2312 "\003DR" /* Save debug controls */
2313 /* Ignore Host address-space size */
2314 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2315 "\020AckInt" /* Acknowledge interrupt on exit */
2316 "\023PAT-SV" /* Save MSR_PAT */
2317 "\024PAT-LD" /* Load MSR_PAT */
2318 "\025EFER-SV" /* Save MSR_EFER */
2319 "\026EFER-LD" /* Load MSR_EFER */
2320 "\027PTMR-SV" /* Save VMX-preemption timer value */
2322 printf("\n Entry Controls=0x%b", mask,
2324 "\003DR" /* Save debug controls */
2325 /* Ignore IA-32e mode guest */
2326 /* Ignore Entry to SMM */
2327 /* Ignore Deactivate dual-monitor treatment */
2328 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2329 "\017PAT" /* Load MSR_PAT */
2330 "\020EFER" /* Load MSR_EFER */
2332 if (proc & PROCBASED_SECONDARY_CONTROLS &&
2333 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2334 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2336 printf("\n EPT Features=0x%b", mask,
2338 "\001XO" /* Execute-only translations */
2339 "\007PW4" /* Page-walk length of 4 */
2340 "\011UC" /* EPT paging-structure mem can be UC */
2341 "\017WB" /* EPT paging-structure mem can be WB */
2342 "\0212M" /* EPT PDE can map a 2-Mbyte page */
2343 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */
2344 "\025INVEPT" /* INVEPT is supported */
2345 "\026AD" /* Accessed and dirty flags for EPT */
2346 "\032single" /* INVEPT single-context type */
2347 "\033all" /* INVEPT all-context type */
2350 printf("\n VPID Features=0x%b", mask,
2352 "\001INVVPID" /* INVVPID is supported */
2353 "\011individual" /* INVVPID individual-address type */
2354 "\012single" /* INVVPID single-context type */
2355 "\013all" /* INVVPID all-context type */
2356 /* INVVPID single-context-retaining-globals type */
2357 "\014single-globals"
2363 print_hypervisor_info(void)
2367 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);