sys/x86/x86/identcpu.c

   1 /*-
   2  * Copyright (c) 1992 Terrence R. Lambert.
   3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
   4  * Copyright (c) 1997 KATO Takenori.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * William Jolitz.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by the University of
  21  *      California, Berkeley and its contributors.
  22  * 4. Neither the name of the University nor the names of its contributors
  23  *    may be used to endorse or promote products derived from this software
  24  *    without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  36  * SUCH DAMAGE.
  37  *
  38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include "opt_cpu.h"
  45
  46 #include <sys/param.h>
  47 #include <sys/bus.h>
  48 #include <sys/cpu.h>
  49 #include <sys/eventhandler.h>
  50 #include <sys/systm.h>
  51 #include <sys/kernel.h>
  52 #include <sys/sysctl.h>
  53 #include <sys/power.h>
  54
  55 #include <machine/asmacros.h>
  56 #include <machine/clock.h>
  57 #include <machine/cputypes.h>
  58 #include <machine/frame.h>
  59 #include <machine/intr_machdep.h>
  60 #include <machine/md_var.h>
  61 #include <machine/segments.h>
  62 #include <machine/specialreg.h>
  63
  64 #include <amd64/vmm/intel/vmx_controls.h>
  65 #include <x86/isa/icu.h>
  66
  67 #ifdef __i386__
  68 #define IDENTBLUE_CYRIX486      0
  69 #define IDENTBLUE_IBMCPU        1
  70 #define IDENTBLUE_CYRIXM2       2
  71
  72 static void identifycyrix(void);
  73 static void print_transmeta_info(void);
  74 #endif
  75 static u_int find_cpu_vendor_id(void);
  76 static void print_AMD_info(void);
  77 static void print_INTEL_info(void);
  78 static void print_INTEL_TLB(u_int data);
  79 static void print_via_padlock_info(void);
  80 static void print_vmx_info(void);
  81
  82 int     cpu_class;
  83 char machine[] = MACHINE;
  84
  85 #ifdef __amd64__
  86 #ifdef SCTL_MASK32
  87 extern int adaptive_machine_arch;
  88 #endif
  89
  90 static int
  91 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
  92 {
  93 #ifdef SCTL_MASK32
  94         static const char machine32[] = "i386";
  95 #endif
  96         int error;
  97
  98 #ifdef SCTL_MASK32
  99         if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
 100                 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
 101         else
 102 #endif
 103                 error = SYSCTL_OUT(req, machine, sizeof(machine));
 104         return (error);
 105
 106 }
 107 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD,
 108     NULL, 0, sysctl_hw_machine, "A", "Machine class");
 109 #else
 110 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
 111     machine, 0, "Machine class");
 112 #endif
 113
 114 static char cpu_model[128];
 115 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
 116     cpu_model, 0, "Machine model");
 117
 118 static int hw_clockrate;
 119 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
 120     &hw_clockrate, 0, "CPU instruction clock rate");
 121
 122 static eventhandler_tag tsc_post_tag;
 123
 124 static char cpu_brand[48];
 125
 126 #ifdef __i386__
 127 #define MAX_BRAND_INDEX 8
 128
 129 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
 130         NULL,                   /* No brand */
 131         "Intel Celeron",
 132         "Intel Pentium III",
 133         "Intel Pentium III Xeon",
 134         NULL,
 135         NULL,
 136         NULL,
 137         NULL,
 138         "Intel Pentium 4"
 139 };
 140 #endif
 141
 142 static struct {
 143         char    *cpu_name;
 144         int     cpu_class;
 145 } cpus[] = {
 146 #ifdef __i386__
 147         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
 148         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
 149         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
 150         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
 151         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
 152         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
 153         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
 154         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
 155         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
 156         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
 157         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
 158         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
 159         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
 160         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
 161         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
 162         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
 163         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
 164 #else
 165         { "Clawhammer",         CPUCLASS_K8 },          /* CPU_CLAWHAMMER */
 166         { "Sledgehammer",       CPUCLASS_K8 },          /* CPU_SLEDGEHAMMER */
 167 #endif
 168 };
 169
 170 static struct {
 171         char    *vendor;
 172         u_int   vendor_id;
 173 } cpu_vendors[] = {
 174         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
 175         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
 176         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
 177 #ifdef __i386__
 178         { NSC_VENDOR_ID,        CPU_VENDOR_NSC },       /* Geode by NSC */
 179         { CYRIX_VENDOR_ID,      CPU_VENDOR_CYRIX },     /* CyrixInstead */
 180         { TRANSMETA_VENDOR_ID,  CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
 181         { SIS_VENDOR_ID,        CPU_VENDOR_SIS },       /* SiS SiS SiS  */
 182         { UMC_VENDOR_ID,        CPU_VENDOR_UMC },       /* UMC UMC UMC  */
 183         { NEXGEN_VENDOR_ID,     CPU_VENDOR_NEXGEN },    /* NexGenDriven */
 184         { RISE_VENDOR_ID,       CPU_VENDOR_RISE },      /* RiseRiseRise */
 185 #if 0
 186         /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
 187         { "TransmetaCPU",       CPU_VENDOR_TRANSMETA },
 188 #endif
 189 #endif
 190 };
 191
 192 void
 193 printcpuinfo(void)
 194 {
 195         u_int regs[4], i;
 196         char *brand;
 197
 198         cpu_class = cpus[cpu].cpu_class;
 199         printf("CPU: ");
 200         strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
 201
 202         /* Check for extended CPUID information and a processor name. */
 203         if (cpu_exthigh >= 0x80000004) {
 204                 brand = cpu_brand;
 205                 for (i = 0x80000002; i < 0x80000005; i++) {
 206                         do_cpuid(i, regs);
 207                         memcpy(brand, regs, sizeof(regs));
 208                         brand += sizeof(regs);
 209                 }
 210         }
 211
 212         switch (cpu_vendor_id) {
 213         case CPU_VENDOR_INTEL:
 214 #ifdef __i386__
 215                 if ((cpu_id & 0xf00) > 0x300) {
 216                         u_int brand_index;
 217
 218                         cpu_model[0] = '\0';
 219
 220                         switch (cpu_id & 0x3000) {
 221                         case 0x1000:
 222                                 strcpy(cpu_model, "Overdrive ");
 223                                 break;
 224                         case 0x2000:
 225                                 strcpy(cpu_model, "Dual ");
 226                                 break;
 227                         }
 228
 229                         switch (cpu_id & 0xf00) {
 230                         case 0x400:
 231                                 strcat(cpu_model, "i486 ");
 232                                 /* Check the particular flavor of 486 */
 233                                 switch (cpu_id & 0xf0) {
 234                                 case 0x00:
 235                                 case 0x10:
 236                                         strcat(cpu_model, "DX");
 237                                         break;
 238                                 case 0x20:
 239                                         strcat(cpu_model, "SX");
 240                                         break;
 241                                 case 0x30:
 242                                         strcat(cpu_model, "DX2");
 243                                         break;
 244                                 case 0x40:
 245                                         strcat(cpu_model, "SL");
 246                                         break;
 247                                 case 0x50:
 248                                         strcat(cpu_model, "SX2");
 249                                         break;
 250                                 case 0x70:
 251                                         strcat(cpu_model,
 252                                             "DX2 Write-Back Enhanced");
 253                                         break;
 254                                 case 0x80:
 255                                         strcat(cpu_model, "DX4");
 256                                         break;
 257                                 }
 258                                 break;
 259                         case 0x500:
 260                                 /* Check the particular flavor of 586 */
 261                                 strcat(cpu_model, "Pentium");
 262                                 switch (cpu_id & 0xf0) {
 263                                 case 0x00:
 264                                         strcat(cpu_model, " A-step");
 265                                         break;
 266                                 case 0x10:
 267                                         strcat(cpu_model, "/P5");
 268                                         break;
 269                                 case 0x20:
 270                                         strcat(cpu_model, "/P54C");
 271                                         break;
 272                                 case 0x30:
 273                                         strcat(cpu_model, "/P24T");
 274                                         break;
 275                                 case 0x40:
 276                                         strcat(cpu_model, "/P55C");
 277                                         break;
 278                                 case 0x70:
 279                                         strcat(cpu_model, "/P54C");
 280                                         break;
 281                                 case 0x80:
 282                                         strcat(cpu_model, "/P55C (quarter-micron)");
 283                                         break;
 284                                 default:
 285                                         /* nothing */
 286                                         break;
 287                                 }
 288 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 289                                 /*
 290                                  * XXX - If/when Intel fixes the bug, this
 291                                  * should also check the version of the
 292                                  * CPU, not just that it's a Pentium.
 293                                  */
 294                                 has_f00f_bug = 1;
 295 #endif
 296                                 break;
 297                         case 0x600:
 298                                 /* Check the particular flavor of 686 */
 299                                 switch (cpu_id & 0xf0) {
 300                                 case 0x00:
 301                                         strcat(cpu_model, "Pentium Pro A-step");
 302                                         break;
 303                                 case 0x10:
 304                                         strcat(cpu_model, "Pentium Pro");
 305                                         break;
 306                                 case 0x30:
 307                                 case 0x50:
 308                                 case 0x60:
 309                                         strcat(cpu_model,
 310                                 "Pentium II/Pentium II Xeon/Celeron");
 311                                         cpu = CPU_PII;
 312                                         break;
 313                                 case 0x70:
 314                                 case 0x80:
 315                                 case 0xa0:
 316                                 case 0xb0:
 317                                         strcat(cpu_model,
 318                                         "Pentium III/Pentium III Xeon/Celeron");
 319                                         cpu = CPU_PIII;
 320                                         break;
 321                                 default:
 322                                         strcat(cpu_model, "Unknown 80686");
 323                                         break;
 324                                 }
 325                                 break;
 326                         case 0xf00:
 327                                 strcat(cpu_model, "Pentium 4");
 328                                 cpu = CPU_P4;
 329                                 break;
 330                         default:
 331                                 strcat(cpu_model, "unknown");
 332                                 break;
 333                         }
 334
 335                         /*
 336                          * If we didn't get a brand name from the extended
 337                          * CPUID, try to look it up in the brand table.
 338                          */
 339                         if (cpu_high > 0 && *cpu_brand == '\0') {
 340                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
 341                                 if (brand_index <= MAX_BRAND_INDEX &&
 342                                     cpu_brandtable[brand_index] != NULL)
 343                                         strcpy(cpu_brand,
 344                                             cpu_brandtable[brand_index]);
 345                         }
 346                 }
 347 #else
 348                 /* Please make up your mind folks! */
 349                 strcat(cpu_model, "EM64T");
 350 #endif
 351                 break;
 352         case CPU_VENDOR_AMD:
 353                 /*
 354                  * Values taken from AMD Processor Recognition
 355                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
 356                  * (also describes ``Features'' encodings.
 357                  */
 358                 strcpy(cpu_model, "AMD ");
 359 #ifdef __i386__
 360                 switch (cpu_id & 0xFF0) {
 361                 case 0x410:
 362                         strcat(cpu_model, "Standard Am486DX");
 363                         break;
 364                 case 0x430:
 365                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
 366                         break;
 367                 case 0x470:
 368                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
 369                         break;
 370                 case 0x480:
 371                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
 372                         break;
 373                 case 0x490:
 374                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
 375                         break;
 376                 case 0x4E0:
 377                         strcat(cpu_model, "Am5x86 Write-Through");
 378                         break;
 379                 case 0x4F0:
 380                         strcat(cpu_model, "Am5x86 Write-Back");
 381                         break;
 382                 case 0x500:
 383                         strcat(cpu_model, "K5 model 0");
 384                         break;
 385                 case 0x510:
 386                         strcat(cpu_model, "K5 model 1");
 387                         break;
 388                 case 0x520:
 389                         strcat(cpu_model, "K5 PR166 (model 2)");
 390                         break;
 391                 case 0x530:
 392                         strcat(cpu_model, "K5 PR200 (model 3)");
 393                         break;
 394                 case 0x560:
 395                         strcat(cpu_model, "K6");
 396                         break;
 397                 case 0x570:
 398                         strcat(cpu_model, "K6 266 (model 1)");
 399                         break;
 400                 case 0x580:
 401                         strcat(cpu_model, "K6-2");
 402                         break;
 403                 case 0x590:
 404                         strcat(cpu_model, "K6-III");
 405                         break;
 406                 case 0x5a0:
 407                         strcat(cpu_model, "Geode LX");
 408                         break;
 409                 default:
 410                         strcat(cpu_model, "Unknown");
 411                         break;
 412                 }
 413 #else
 414                 if ((cpu_id & 0xf00) == 0xf00)
 415                         strcat(cpu_model, "AMD64 Processor");
 416                 else
 417                         strcat(cpu_model, "Unknown");
 418 #endif
 419                 break;
 420 #ifdef __i386__
 421         case CPU_VENDOR_CYRIX:
 422                 strcpy(cpu_model, "Cyrix ");
 423                 switch (cpu_id & 0xff0) {
 424                 case 0x440:
 425                         strcat(cpu_model, "MediaGX");
 426                         break;
 427                 case 0x520:
 428                         strcat(cpu_model, "6x86");
 429                         break;
 430                 case 0x540:
 431                         cpu_class = CPUCLASS_586;
 432                         strcat(cpu_model, "GXm");
 433                         break;
 434                 case 0x600:
 435                         strcat(cpu_model, "6x86MX");
 436                         break;
 437                 default:
 438                         /*
 439                          * Even though CPU supports the cpuid
 440                          * instruction, it can be disabled.
 441                          * Therefore, this routine supports all Cyrix
 442                          * CPUs.
 443                          */
 444                         switch (cyrix_did & 0xf0) {
 445                         case 0x00:
 446                                 switch (cyrix_did & 0x0f) {
 447                                 case 0x00:
 448                                         strcat(cpu_model, "486SLC");
 449                                         break;
 450                                 case 0x01:
 451                                         strcat(cpu_model, "486DLC");
 452                                         break;
 453                                 case 0x02:
 454                                         strcat(cpu_model, "486SLC2");
 455                                         break;
 456                                 case 0x03:
 457                                         strcat(cpu_model, "486DLC2");
 458                                         break;
 459                                 case 0x04:
 460                                         strcat(cpu_model, "486SRx");
 461                                         break;
 462                                 case 0x05:
 463                                         strcat(cpu_model, "486DRx");
 464                                         break;
 465                                 case 0x06:
 466                                         strcat(cpu_model, "486SRx2");
 467                                         break;
 468                                 case 0x07:
 469                                         strcat(cpu_model, "486DRx2");
 470                                         break;
 471                                 case 0x08:
 472                                         strcat(cpu_model, "486SRu");
 473                                         break;
 474                                 case 0x09:
 475                                         strcat(cpu_model, "486DRu");
 476                                         break;
 477                                 case 0x0a:
 478                                         strcat(cpu_model, "486SRu2");
 479                                         break;
 480                                 case 0x0b:
 481                                         strcat(cpu_model, "486DRu2");
 482                                         break;
 483                                 default:
 484                                         strcat(cpu_model, "Unknown");
 485                                         break;
 486                                 }
 487                                 break;
 488                         case 0x10:
 489                                 switch (cyrix_did & 0x0f) {
 490                                 case 0x00:
 491                                         strcat(cpu_model, "486S");
 492                                         break;
 493                                 case 0x01:
 494                                         strcat(cpu_model, "486S2");
 495                                         break;
 496                                 case 0x02:
 497                                         strcat(cpu_model, "486Se");
 498                                         break;
 499                                 case 0x03:
 500                                         strcat(cpu_model, "486S2e");
 501                                         break;
 502                                 case 0x0a:
 503                                         strcat(cpu_model, "486DX");
 504                                         break;
 505                                 case 0x0b:
 506                                         strcat(cpu_model, "486DX2");
 507                                         break;
 508                                 case 0x0f:
 509                                         strcat(cpu_model, "486DX4");
 510                                         break;
 511                                 default:
 512                                         strcat(cpu_model, "Unknown");
 513                                         break;
 514                                 }
 515                                 break;
 516                         case 0x20:
 517                                 if ((cyrix_did & 0x0f) < 8)
 518                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
 519                                 else
 520                                         strcat(cpu_model, "5x86");
 521                                 break;
 522                         case 0x30:
 523                                 strcat(cpu_model, "6x86");
 524                                 break;
 525                         case 0x40:
 526                                 if ((cyrix_did & 0xf000) == 0x3000) {
 527                                         cpu_class = CPUCLASS_586;
 528                                         strcat(cpu_model, "GXm");
 529                                 } else
 530                                         strcat(cpu_model, "MediaGX");
 531                                 break;
 532                         case 0x50:
 533                                 strcat(cpu_model, "6x86MX");
 534                                 break;
 535                         case 0xf0:
 536                                 switch (cyrix_did & 0x0f) {
 537                                 case 0x0d:
 538                                         strcat(cpu_model, "Overdrive CPU");
 539                                         break;
 540                                 case 0x0e:
 541                                         strcpy(cpu_model, "Texas Instruments 486SXL");
 542                                         break;
 543                                 case 0x0f:
 544                                         strcat(cpu_model, "486SLC/DLC");
 545                                         break;
 546                                 default:
 547                                         strcat(cpu_model, "Unknown");
 548                                         break;
 549                                 }
 550                                 break;
 551                         default:
 552                                 strcat(cpu_model, "Unknown");
 553                                 break;
 554                         }
 555                         break;
 556                 }
 557                 break;
 558         case CPU_VENDOR_RISE:
 559                 strcpy(cpu_model, "Rise ");
 560                 switch (cpu_id & 0xff0) {
 561                 case 0x500:     /* 6401 and 6441 (Kirin) */
 562                 case 0x520:     /* 6510 (Lynx) */
 563                         strcat(cpu_model, "mP6");
 564                         break;
 565                 default:
 566                         strcat(cpu_model, "Unknown");
 567                 }
 568                 break;
 569 #endif
 570         case CPU_VENDOR_CENTAUR:
 571 #ifdef __i386__
 572                 switch (cpu_id & 0xff0) {
 573                 case 0x540:
 574                         strcpy(cpu_model, "IDT WinChip C6");
 575                         break;
 576                 case 0x580:
 577                         strcpy(cpu_model, "IDT WinChip 2");
 578                         break;
 579                 case 0x590:
 580                         strcpy(cpu_model, "IDT WinChip 3");
 581                         break;
 582                 case 0x660:
 583                         strcpy(cpu_model, "VIA C3 Samuel");
 584                         break;
 585                 case 0x670:
 586                         if (cpu_id & 0x8)
 587                                 strcpy(cpu_model, "VIA C3 Ezra");
 588                         else
 589                                 strcpy(cpu_model, "VIA C3 Samuel 2");
 590                         break;
 591                 case 0x680:
 592                         strcpy(cpu_model, "VIA C3 Ezra-T");
 593                         break;
 594                 case 0x690:
 595                         strcpy(cpu_model, "VIA C3 Nehemiah");
 596                         break;
 597                 case 0x6a0:
 598                 case 0x6d0:
 599                         strcpy(cpu_model, "VIA C7 Esther");
 600                         break;
 601                 case 0x6f0:
 602                         strcpy(cpu_model, "VIA Nano");
 603                         break;
 604                 default:
 605                         strcpy(cpu_model, "VIA/IDT Unknown");
 606                 }
 607 #else
 608                 strcpy(cpu_model, "VIA ");
 609                 if ((cpu_id & 0xff0) == 0x6f0)
 610                         strcat(cpu_model, "Nano Processor");
 611                 else
 612                         strcat(cpu_model, "Unknown");
 613 #endif
 614                 break;
 615 #ifdef __i386__
 616         case CPU_VENDOR_IBM:
 617                 strcpy(cpu_model, "Blue Lightning CPU");
 618                 break;
 619         case CPU_VENDOR_NSC:
 620                 switch (cpu_id & 0xff0) {
 621                 case 0x540:
 622                         strcpy(cpu_model, "Geode SC1100");
 623                         cpu = CPU_GEODE1100;
 624                         break;
 625                 default:
 626                         strcpy(cpu_model, "Geode/NSC unknown");
 627                         break;
 628                 }
 629                 break;
 630 #endif
 631         default:
 632                 strcat(cpu_model, "Unknown");
 633                 break;
 634         }
 635
 636         /*
 637          * Replace cpu_model with cpu_brand minus leading spaces if
 638          * we have one.
 639          */
 640         brand = cpu_brand;
 641         while (*brand == ' ')
 642                 ++brand;
 643         if (*brand != '\0')
 644                 strcpy(cpu_model, brand);
 645
 646         printf("%s (", cpu_model);
 647         if (tsc_freq != 0) {
 648                 hw_clockrate = (tsc_freq + 5000) / 1000000;
 649                 printf("%jd.%02d-MHz ",
 650                     (intmax_t)(tsc_freq + 4999) / 1000000,
 651                     (u_int)((tsc_freq + 4999) / 10000) % 100);
 652         }
 653         switch(cpu_class) {
 654 #ifdef __i386__
 655         case CPUCLASS_286:
 656                 printf("286");
 657                 break;
 658         case CPUCLASS_386:
 659                 printf("386");
 660                 break;
 661 #if defined(I486_CPU)
 662         case CPUCLASS_486:
 663                 printf("486");
 664                 break;
 665 #endif
 666 #if defined(I586_CPU)
 667         case CPUCLASS_586:
 668                 printf("586");
 669                 break;
 670 #endif
 671 #if defined(I686_CPU)
 672         case CPUCLASS_686:
 673                 printf("686");
 674                 break;
 675 #endif
 676 #else
 677         case CPUCLASS_K8:
 678                 printf("K8");
 679                 break;
 680 #endif
 681         default:
 682                 printf("Unknown");      /* will panic below... */
 683         }
 684         printf("-class CPU)\n");
 685         if (*cpu_vendor)
 686                 printf("  Origin=\"%s\"", cpu_vendor);
 687         if (cpu_id)
 688                 printf("  Id=0x%x", cpu_id);
 689
 690         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 691             cpu_vendor_id == CPU_VENDOR_AMD ||
 692             cpu_vendor_id == CPU_VENDOR_CENTAUR ||
 693 #ifdef __i386__
 694             cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
 695             cpu_vendor_id == CPU_VENDOR_RISE ||
 696             cpu_vendor_id == CPU_VENDOR_NSC ||
 697             (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
 698 #endif
 699             0) {
 700                 printf("  Family=0x%x", CPUID_TO_FAMILY(cpu_id));
 701                 printf("  Model=0x%x", CPUID_TO_MODEL(cpu_id));
 702                 printf("  Stepping=%u", cpu_id & CPUID_STEPPING);
 703 #ifdef __i386__
 704                 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
 705                         printf("\n  DIR=0x%04x", cyrix_did);
 706 #endif
 707
 708                 /*
 709                  * AMD CPUID Specification
 710                  * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
 711                  *
 712                  * Intel Processor Identification and CPUID Instruction
 713                  * http://www.intel.com/assets/pdf/appnote/241618.pdf
 714                  */
 715                 if (cpu_high > 0) {
 716
 717                         /*
 718                          * Here we should probably set up flags indicating
 719                          * whether or not various features are available.
 720                          * The interesting ones are probably VME, PSE, PAE,
 721                          * and PGE.  The code already assumes without bothering
 722                          * to check that all CPUs >= Pentium have a TSC and
 723                          * MSRs.
 724                          */
 725                         printf("\n  Features=0x%b", cpu_feature,
 726                         "\020"
 727                         "\001FPU"       /* Integral FPU */
 728                         "\002VME"       /* Extended VM86 mode support */
 729                         "\003DE"        /* Debugging Extensions (CR4.DE) */
 730                         "\004PSE"       /* 4MByte page tables */
 731                         "\005TSC"       /* Timestamp counter */
 732                         "\006MSR"       /* Machine specific registers */
 733                         "\007PAE"       /* Physical address extension */
 734                         "\010MCE"       /* Machine Check support */
 735                         "\011CX8"       /* CMPEXCH8 instruction */
 736                         "\012APIC"      /* SMP local APIC */
 737                         "\013oldMTRR"   /* Previous implementation of MTRR */
 738                         "\014SEP"       /* Fast System Call */
 739                         "\015MTRR"      /* Memory Type Range Registers */
 740                         "\016PGE"       /* PG_G (global bit) support */
 741                         "\017MCA"       /* Machine Check Architecture */
 742                         "\020CMOV"      /* CMOV instruction */
 743                         "\021PAT"       /* Page attributes table */
 744                         "\022PSE36"     /* 36 bit address space support */
 745                         "\023PN"        /* Processor Serial number */
 746                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
 747                         "\025<b20>"
 748                         "\026DTS"       /* Debug Trace Store */
 749                         "\027ACPI"      /* ACPI support */
 750                         "\030MMX"       /* MMX instructions */
 751                         "\031FXSR"      /* FXSAVE/FXRSTOR */
 752                         "\032SSE"       /* Streaming SIMD Extensions */
 753                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
 754                         "\034SS"        /* Self snoop */
 755                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
 756                         "\036TM"        /* Thermal Monitor clock slowdown */
 757                         "\037IA64"      /* CPU can execute IA64 instructions */
 758                         "\040PBE"       /* Pending Break Enable */
 759                         );
 760
 761                         if (cpu_feature2 != 0) {
 762                                 printf("\n  Features2=0x%b", cpu_feature2,
 763                                 "\020"
 764                                 "\001SSE3"      /* SSE3 */
 765                                 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
 766                                 "\003DTES64"    /* 64-bit Debug Trace */
 767                                 "\004MON"       /* MONITOR/MWAIT Instructions */
 768                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
 769                                 "\006VMX"       /* Virtual Machine Extensions */
 770                                 "\007SMX"       /* Safer Mode Extensions */
 771                                 "\010EST"       /* Enhanced SpeedStep */
 772                                 "\011TM2"       /* Thermal Monitor 2 */
 773                                 "\012SSSE3"     /* SSSE3 */
 774                                 "\013CNXT-ID"   /* L1 context ID available */
 775                                 "\014<b11>"
 776                                 "\015FMA"       /* Fused Multiply Add */
 777                                 "\016CX16"      /* CMPXCHG16B Instruction */
 778                                 "\017xTPR"      /* Send Task Priority Messages*/
 779                                 "\020PDCM"      /* Perf/Debug Capability MSR */
 780                                 "\021<b16>"
 781                                 "\022PCID"      /* Process-context Identifiers*/
 782                                 "\023DCA"       /* Direct Cache Access */
 783                                 "\024SSE4.1"    /* SSE 4.1 */
 784                                 "\025SSE4.2"    /* SSE 4.2 */
 785                                 "\026x2APIC"    /* xAPIC Extensions */
 786                                 "\027MOVBE"     /* MOVBE Instruction */
 787                                 "\030POPCNT"    /* POPCNT Instruction */
 788                                 "\031TSCDLT"    /* TSC-Deadline Timer */
 789                                 "\032AESNI"     /* AES Crypto */
 790                                 "\033XSAVE"     /* XSAVE/XRSTOR States */
 791                                 "\034OSXSAVE"   /* OS-Enabled State Management*/
 792                                 "\035AVX"       /* Advanced Vector Extensions */
 793                                 "\036F16C"      /* Half-precision conversions */
 794                                 "\037RDRAND"    /* RDRAND Instruction */
 795                                 "\040HV"        /* Hypervisor */
 796                                 );
 797                         }
 798
 799                         if (amd_feature != 0) {
 800                                 printf("\n  AMD Features=0x%b", amd_feature,
 801                                 "\020"          /* in hex */
 802                                 "\001<s0>"      /* Same */
 803                                 "\002<s1>"      /* Same */
 804                                 "\003<s2>"      /* Same */
 805                                 "\004<s3>"      /* Same */
 806                                 "\005<s4>"      /* Same */
 807                                 "\006<s5>"      /* Same */
 808                                 "\007<s6>"      /* Same */
 809                                 "\010<s7>"      /* Same */
 810                                 "\011<s8>"      /* Same */
 811                                 "\012<s9>"      /* Same */
 812                                 "\013<b10>"     /* Undefined */
 813                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
 814                                 "\015<s12>"     /* Same */
 815                                 "\016<s13>"     /* Same */
 816                                 "\017<s14>"     /* Same */
 817                                 "\020<s15>"     /* Same */
 818                                 "\021<s16>"     /* Same */
 819                                 "\022<s17>"     /* Same */
 820                                 "\023<b18>"     /* Reserved, unknown */
 821                                 "\024MP"        /* Multiprocessor Capable */
 822                                 "\025NX"        /* Has EFER.NXE, NX */
 823                                 "\026<b21>"     /* Undefined */
 824                                 "\027MMX+"      /* AMD MMX Extensions */
 825                                 "\030<s23>"     /* Same */
 826                                 "\031<s24>"     /* Same */
 827                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
 828                                 "\033Page1GB"   /* 1-GB large page support */
 829                                 "\034RDTSCP"    /* RDTSCP */
 830                                 "\035<b28>"     /* Undefined */
 831                                 "\036LM"        /* 64 bit long mode */
 832                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
 833                                 "\0403DNow!"    /* AMD 3DNow! */
 834                                 );
 835                         }
 836
 837                         if (amd_feature2 != 0) {
 838                                 printf("\n  AMD Features2=0x%b", amd_feature2,
 839                                 "\020"
 840                                 "\001LAHF"      /* LAHF/SAHF in long mode */
 841                                 "\002CMP"       /* CMP legacy */
 842                                 "\003SVM"       /* Secure Virtual Mode */
 843                                 "\004ExtAPIC"   /* Extended APIC register */
 844                                 "\005CR8"       /* CR8 in legacy mode */
 845                                 "\006ABM"       /* LZCNT instruction */
 846                                 "\007SSE4A"     /* SSE4A */
 847                                 "\010MAS"       /* Misaligned SSE mode */
 848                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
 849                                 "\012OSVW"      /* OS visible workaround */
 850                                 "\013IBS"       /* Instruction based sampling */
 851                                 "\014XOP"       /* XOP extended instructions */
 852                                 "\015SKINIT"    /* SKINIT/STGI */
 853                                 "\016WDT"       /* Watchdog timer */
 854                                 "\017<b14>"
 855                                 "\020LWP"       /* Lightweight Profiling */
 856                                 "\021FMA4"      /* 4-operand FMA instructions */
 857                                 "\022TCE"       /* Translation Cache Extension */
 858                                 "\023<b18>"
 859                                 "\024NodeId"    /* NodeId MSR support */
 860                                 "\025<b20>"
 861                                 "\026TBM"       /* Trailing Bit Manipulation */
 862                                 "\027Topology"  /* Topology Extensions */
 863                                 "\030PCXC"      /* Core perf count */
 864                                 "\031PNXC"      /* NB perf count */
 865                                 "\032<b25>"
 866                                 "\033DBE"       /* Data Breakpoint extension */
 867                                 "\034PTSC"      /* Performance TSC */
 868                                 "\035PL2I"      /* L2I perf count */
 869                                 "\036<b29>"
 870                                 "\037<b30>"
 871                                 "\040<b31>"
 872                                 );
 873                         }
 874
 875                         if (cpu_stdext_feature != 0) {
 876                                 printf("\n  Structured Extended Features=0x%b",
 877                                     cpu_stdext_feature,
 878                                        "\020"
 879                                        /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
 880                                        "\001FSGSBASE"
 881                                        "\002TSCADJ"
 882                                        /* Bit Manipulation Instructions */
 883                                        "\004BMI1"
 884                                        /* Hardware Lock Elision */
 885                                        "\005HLE"
 886                                        /* Advanced Vector Instructions 2 */
 887                                        "\006AVX2"
 888                                        /* Supervisor Mode Execution Prot. */
 889                                        "\010SMEP"
 890                                        /* Bit Manipulation Instructions */
 891                                        "\011BMI2"
 892                                        "\012ERMS"
 893                                        /* Invalidate Processor Context ID */
 894                                        "\013INVPCID"
 895                                        /* Restricted Transactional Memory */
 896                                        "\014RTM"
 897                                        /* Intel Memory Protection Extensions */
 898                                        "\017MPX"
 899                                        /* AVX512 Foundation */
 900                                        "\021AVX512F"
 901                                        /* Enhanced NRBG */
 902                                        "\023RDSEED"
 903                                        /* ADCX + ADOX */
 904                                        "\024ADX"
 905                                        /* Supervisor Mode Access Prevention */
 906                                        "\025SMAP"
 907                                        "\030CLFLUSHOPT"
 908                                        "\032PROCTRACE"
 909                                        "\033AVX512PF"
 910                                        "\034AVX512ER"
 911                                        "\035AVX512CD"
 912                                        "\036SHA"
 913                                        );
 914                         }
 915
 916                         if (via_feature_rng != 0 || via_feature_xcrypt != 0)
 917                                 print_via_padlock_info();
 918
 919                         if (cpu_feature2 & CPUID2_VMX)
 920                                 print_vmx_info();
 921
 922                         if ((cpu_feature & CPUID_HTT) &&
 923                             cpu_vendor_id == CPU_VENDOR_AMD)
 924                                 cpu_feature &= ~CPUID_HTT;
 925
 926                         /*
 927                          * If this CPU supports P-state invariant TSC then
 928                          * mention the capability.
 929                          */
 930                         if (tsc_is_invariant) {
 931                                 printf("\n  TSC: P-state invariant");
 932                                 if (tsc_perf_stat)
 933                                         printf(", performance statistics");
 934                         }
 935
 936                 }
 937 #ifdef __i386__
 938         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
 939                 printf("  DIR=0x%04x", cyrix_did);
 940                 printf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
 941                 printf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
 942 #ifndef CYRIX_CACHE_REALLY_WORKS
 943                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
 944                         printf("\n  CPU cache: write-through mode");
 945 #endif
 946 #endif
 947         }
 948
 949         /* Avoid ugly blank lines: only print newline when we have to. */
 950         if (*cpu_vendor || cpu_id)
 951                 printf("\n");
 952
 953         if (!bootverbose)
 954                 return;
 955
 956         if (cpu_vendor_id == CPU_VENDOR_AMD)
 957                 print_AMD_info();
 958         else if (cpu_vendor_id == CPU_VENDOR_INTEL)
 959                 print_INTEL_info();
 960 #ifdef __i386__
 961         else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
 962                 print_transmeta_info();
 963 #endif
 964 }
 965
 966 void
 967 panicifcpuunsupported(void)
 968 {
 969
 970 #ifdef __i386__
 971 #if !defined(lint)
 972 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
 973 #error This kernel is not configured for one of the supported CPUs
 974 #endif
 975 #else /* lint */
 976 #endif /* lint */
 977 #else /* __amd64__ */
 978 #ifndef HAMMER
 979 #error "You need to specify a cpu type"
 980 #endif
 981 #endif
 982         /*
 983          * Now that we have told the user what they have,
 984          * let them know if that machine type isn't configured.
 985          */
 986         switch (cpu_class) {
 987 #ifdef __i386__
 988         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
 989         case CPUCLASS_386:
 990 #if !defined(I486_CPU)
 991         case CPUCLASS_486:
 992 #endif
 993 #if !defined(I586_CPU)
 994         case CPUCLASS_586:
 995 #endif
 996 #if !defined(I686_CPU)
 997         case CPUCLASS_686:
 998 #endif
 999 #else /* __amd64__ */
1000         case CPUCLASS_X86:
1001 #ifndef HAMMER
1002         case CPUCLASS_K8:
1003 #endif
1004 #endif
1005                 panic("CPU class not configured");
1006         default:
1007                 break;
1008         }
1009 }
1010
1011 #ifdef __i386__
1012 static  volatile u_int trap_by_rdmsr;
1013
1014 /*
1015  * Special exception 6 handler.
1016  * The rdmsr instruction generates invalid opcodes fault on 486-class
1017  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
1018  * function identblue() when this handler is called.  Stacked eip should
1019  * be advanced.
1020  */
1021 inthand_t       bluetrap6;
1022 #ifdef __GNUCLIKE_ASM
1023 __asm
1024 ("                                                                      \n\
1025         .text                                                           \n\
1026         .p2align 2,0x90                                                 \n\
1027         .type   " __XSTRING(CNAME(bluetrap6)) ",@function               \n\
1028 " __XSTRING(CNAME(bluetrap6)) ":                                        \n\
1029         ss                                                              \n\
1030         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1031         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1032         iret                                                            \n\
1033 ");
1034 #endif
1035
1036 /*
1037  * Special exception 13 handler.
1038  * Accessing non-existent MSR generates general protection fault.
1039  */
1040 inthand_t       bluetrap13;
1041 #ifdef __GNUCLIKE_ASM
1042 __asm
1043 ("                                                                      \n\
1044         .text                                                           \n\
1045         .p2align 2,0x90                                                 \n\
1046         .type   " __XSTRING(CNAME(bluetrap13)) ",@function              \n\
1047 " __XSTRING(CNAME(bluetrap13)) ":                                       \n\
1048         ss                                                              \n\
1049         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1050         popl    %eax            /* discard error code */                \n\
1051         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1052         iret                                                            \n\
1053 ");
1054 #endif
1055
1056 /*
1057  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1058  * support cpuid instruction.  This function should be called after
1059  * loading interrupt descriptor table register.
1060  *
1061  * I don't like this method that handles fault, but I couldn't get
1062  * information for any other methods.  Does blue giant know?
1063  */
1064 static int
1065 identblue(void)
1066 {
1067
1068         trap_by_rdmsr = 0;
1069
1070         /*
1071          * Cyrix 486-class CPU does not support rdmsr instruction.
1072          * The rdmsr instruction generates invalid opcode fault, and exception
1073          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
1074          * bluetrap6() set the magic number to trap_by_rdmsr.
1075          */
1076         setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1077             GSEL(GCODE_SEL, SEL_KPL));
1078
1079         /*
1080          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1081          * In this case, rdmsr generates general protection fault, and
1082          * exception will be trapped by bluetrap13().
1083          */
1084         setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1085             GSEL(GCODE_SEL, SEL_KPL));
1086
1087         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
1088
1089         if (trap_by_rdmsr == 0xa8c1d)
1090                 return IDENTBLUE_CYRIX486;
1091         else if (trap_by_rdmsr == 0xa89c4)
1092                 return IDENTBLUE_CYRIXM2;
1093         return IDENTBLUE_IBMCPU;
1094 }
1095
1096
1097 /*
1098  * identifycyrix() set lower 16 bits of cyrix_did as follows:
1099  *
1100  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
1101  * +-------+-------+---------------+
1102  * |  SID  |  RID  |   Device ID   |
1103  * |    (DIR 1)    |    (DIR 0)    |
1104  * +-------+-------+---------------+
1105  */
1106 static void
1107 identifycyrix(void)
1108 {
1109         register_t saveintr;
1110         int     ccr2_test = 0, dir_test = 0;
1111         u_char  ccr2, ccr3;
1112
1113         saveintr = intr_disable();
1114
1115         ccr2 = read_cyrix_reg(CCR2);
1116         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1117         read_cyrix_reg(CCR2);
1118         if (read_cyrix_reg(CCR2) != ccr2)
1119                 ccr2_test = 1;
1120         write_cyrix_reg(CCR2, ccr2);
1121
1122         ccr3 = read_cyrix_reg(CCR3);
1123         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1124         read_cyrix_reg(CCR3);
1125         if (read_cyrix_reg(CCR3) != ccr3)
1126                 dir_test = 1;                                   /* CPU supports DIRs. */
1127         write_cyrix_reg(CCR3, ccr3);
1128
1129         if (dir_test) {
1130                 /* Device ID registers are available. */
1131                 cyrix_did = read_cyrix_reg(DIR1) << 8;
1132                 cyrix_did += read_cyrix_reg(DIR0);
1133         } else if (ccr2_test)
1134                 cyrix_did = 0x0010;             /* 486S A-step */
1135         else
1136                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
1137
1138         intr_restore(saveintr);
1139 }
1140 #endif
1141
1142 /* Update TSC freq with the value indicated by the caller. */
1143 static void
1144 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1145 {
1146
1147         /* If there was an error during the transition, don't do anything. */
1148         if (status != 0)
1149                 return;
1150
1151         /* Total setting for this level gives the new frequency in MHz. */
1152         hw_clockrate = level->total_set.freq;
1153 }
1154
1155 static void
1156 hook_tsc_freq(void *arg __unused)
1157 {
1158
1159         if (tsc_is_invariant)
1160                 return;
1161
1162         tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1163             tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1164 }
1165
1166 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1167
1168 /*
1169  * Final stage of CPU identification.
1170  */
1171 #ifdef __i386__
1172 void
1173 finishidentcpu(void)
1174 #else
1175 void
1176 identify_cpu(void)
1177 #endif
1178 {
1179         u_int regs[4], cpu_stdext_disable;
1180 #ifdef __i386__
1181         u_char ccr3;
1182 #endif
1183
1184 #ifdef __amd64__
1185         do_cpuid(0, regs);
1186         cpu_high = regs[0];
1187         ((u_int *)&cpu_vendor)[0] = regs[1];
1188         ((u_int *)&cpu_vendor)[1] = regs[3];
1189         ((u_int *)&cpu_vendor)[2] = regs[2];
1190         cpu_vendor[12] = '\0';
1191
1192         do_cpuid(1, regs);
1193         cpu_id = regs[0];
1194         cpu_procinfo = regs[1];
1195         cpu_feature = regs[3];
1196         cpu_feature2 = regs[2];
1197 #endif
1198
1199         cpu_vendor_id = find_cpu_vendor_id();
1200
1201         /*
1202          * Clear "Limit CPUID Maxval" bit and get the largest standard CPUID
1203          * function number again if it is set from BIOS.  It is necessary
1204          * for probing correct CPU topology later.
1205          * XXX This is only done on the BSP package.
1206          */
1207         if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high > 0 && cpu_high < 4 &&
1208             ((CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1209             (CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1210                 uint64_t msr;
1211                 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1212                 if ((msr & 0x400000ULL) != 0) {
1213                         wrmsr(MSR_IA32_MISC_ENABLE, msr & ~0x400000ULL);
1214                         do_cpuid(0, regs);
1215                         cpu_high = regs[0];
1216                 }
1217         }
1218
1219         if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1220                 do_cpuid(5, regs);
1221                 cpu_mon_mwait_flags = regs[2];
1222                 cpu_mon_min_size = regs[0] &  CPUID5_MON_MIN_SIZE;
1223                 cpu_mon_max_size = regs[1] &  CPUID5_MON_MAX_SIZE;
1224         }
1225
1226         if (cpu_high >= 7) {
1227                 cpuid_count(7, 0, regs);
1228                 cpu_stdext_feature = regs[1];
1229
1230                 /*
1231                  * Some hypervisors fail to filter out unsupported
1232                  * extended features.  For now, disable the
1233                  * extensions, activation of which requires setting a
1234                  * bit in CR4, and which VM monitors do not support.
1235                  */
1236                 if (cpu_feature2 & CPUID2_HV) {
1237                         cpu_stdext_disable = CPUID_STDEXT_FSGSBASE |
1238                             CPUID_STDEXT_SMEP;
1239                 } else
1240                         cpu_stdext_disable = 0;
1241                 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1242                 cpu_stdext_feature &= ~cpu_stdext_disable;
1243         }
1244
1245 #ifdef __i386__
1246         if (cpu_high > 0 &&
1247             (cpu_vendor_id == CPU_VENDOR_INTEL ||
1248              cpu_vendor_id == CPU_VENDOR_AMD ||
1249              cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1250              cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1251              cpu_vendor_id == CPU_VENDOR_NSC)) {
1252                 do_cpuid(0x80000000, regs);
1253                 if (regs[0] >= 0x80000000)
1254                         cpu_exthigh = regs[0];
1255         }
1256 #else
1257         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1258             cpu_vendor_id == CPU_VENDOR_AMD ||
1259             cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1260                 do_cpuid(0x80000000, regs);
1261                 cpu_exthigh = regs[0];
1262         }
1263 #endif
1264         if (cpu_exthigh >= 0x80000001) {
1265                 do_cpuid(0x80000001, regs);
1266                 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1267                 amd_feature2 = regs[2];
1268         }
1269         if (cpu_exthigh >= 0x80000007) {
1270                 do_cpuid(0x80000007, regs);
1271                 amd_pminfo = regs[3];
1272         }
1273         if (cpu_exthigh >= 0x80000008) {
1274                 do_cpuid(0x80000008, regs);
1275                 cpu_procinfo2 = regs[2];
1276         }
1277
1278 #ifdef __i386__
1279         if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1280                 if (cpu == CPU_486) {
1281                         /*
1282                          * These conditions are equivalent to:
1283                          *     - CPU does not support cpuid instruction.
1284                          *     - Cyrix/IBM CPU is detected.
1285                          */
1286                         if (identblue() == IDENTBLUE_IBMCPU) {
1287                                 strcpy(cpu_vendor, "IBM");
1288                                 cpu_vendor_id = CPU_VENDOR_IBM;
1289                                 cpu = CPU_BLUE;
1290                                 return;
1291                         }
1292                 }
1293                 switch (cpu_id & 0xf00) {
1294                 case 0x600:
1295                         /*
1296                          * Cyrix's datasheet does not describe DIRs.
1297                          * Therefor, I assume it does not have them
1298                          * and use the result of the cpuid instruction.
1299                          * XXX they seem to have it for now at least. -Peter
1300                          */
1301                         identifycyrix();
1302                         cpu = CPU_M2;
1303                         break;
1304                 default:
1305                         identifycyrix();
1306                         /*
1307                          * This routine contains a trick.
1308                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1309                          */
1310                         switch (cyrix_did & 0x00f0) {
1311                         case 0x00:
1312                         case 0xf0:
1313                                 cpu = CPU_486DLC;
1314                                 break;
1315                         case 0x10:
1316                                 cpu = CPU_CY486DX;
1317                                 break;
1318                         case 0x20:
1319                                 if ((cyrix_did & 0x000f) < 8)
1320                                         cpu = CPU_M1;
1321                                 else
1322                                         cpu = CPU_M1SC;
1323                                 break;
1324                         case 0x30:
1325                                 cpu = CPU_M1;
1326                                 break;
1327                         case 0x40:
1328                                 /* MediaGX CPU */
1329                                 cpu = CPU_M1SC;
1330                                 break;
1331                         default:
1332                                 /* M2 and later CPUs are treated as M2. */
1333                                 cpu = CPU_M2;
1334
1335                                 /*
1336                                  * enable cpuid instruction.
1337                                  */
1338                                 ccr3 = read_cyrix_reg(CCR3);
1339                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1340                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1341                                 write_cyrix_reg(CCR3, ccr3);
1342
1343                                 do_cpuid(0, regs);
1344                                 cpu_high = regs[0];     /* eax */
1345                                 do_cpuid(1, regs);
1346                                 cpu_id = regs[0];       /* eax */
1347                                 cpu_feature = regs[3];  /* edx */
1348                                 break;
1349                         }
1350                 }
1351         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1352                 /*
1353                  * There are BlueLightning CPUs that do not change
1354                  * undefined flags by dividing 5 by 2.  In this case,
1355                  * the CPU identification routine in locore.s leaves
1356                  * cpu_vendor null string and puts CPU_486 into the
1357                  * cpu.
1358                  */
1359                 if (identblue() == IDENTBLUE_IBMCPU) {
1360                         strcpy(cpu_vendor, "IBM");
1361                         cpu_vendor_id = CPU_VENDOR_IBM;
1362                         cpu = CPU_BLUE;
1363                         return;
1364                 }
1365         }
1366 #else
1367         /* XXX */
1368         cpu = CPU_CLAWHAMMER;
1369 #endif
1370 }
1371
1372 static u_int
1373 find_cpu_vendor_id(void)
1374 {
1375         int     i;
1376
1377         for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++)
1378                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1379                         return (cpu_vendors[i].vendor_id);
1380         return (0);
1381 }
1382
1383 static void
1384 print_AMD_assoc(int i)
1385 {
1386         if (i == 255)
1387                 printf(", fully associative\n");
1388         else
1389                 printf(", %d-way associative\n", i);
1390 }
1391
1392 static void
1393 print_AMD_l2_assoc(int i)
1394 {
1395         switch (i & 0x0f) {
1396         case 0: printf(", disabled/not present\n"); break;
1397         case 1: printf(", direct mapped\n"); break;
1398         case 2: printf(", 2-way associative\n"); break;
1399         case 4: printf(", 4-way associative\n"); break;
1400         case 6: printf(", 8-way associative\n"); break;
1401         case 8: printf(", 16-way associative\n"); break;
1402         case 15: printf(", fully associative\n"); break;
1403         default: printf(", reserved configuration\n"); break;
1404         }
1405 }
1406
1407 static void
1408 print_AMD_info(void)
1409 {
1410 #ifdef __i386__
1411         uint64_t amd_whcr;
1412 #endif
1413         u_int regs[4];
1414
1415         if (cpu_exthigh >= 0x80000005) {
1416                 do_cpuid(0x80000005, regs);
1417                 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1418                 print_AMD_assoc(regs[0] >> 24);
1419
1420                 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1421                 print_AMD_assoc((regs[0] >> 8) & 0xff);
1422
1423                 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1424                 print_AMD_assoc(regs[1] >> 24);
1425
1426                 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1427                 print_AMD_assoc((regs[1] >> 8) & 0xff);
1428
1429                 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1430                 printf(", %d bytes/line", regs[2] & 0xff);
1431                 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1432                 print_AMD_assoc((regs[2] >> 16) & 0xff);
1433
1434                 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1435                 printf(", %d bytes/line", regs[3] & 0xff);
1436                 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1437                 print_AMD_assoc((regs[3] >> 16) & 0xff);
1438         }
1439
1440         if (cpu_exthigh >= 0x80000006) {
1441                 do_cpuid(0x80000006, regs);
1442                 if ((regs[0] >> 16) != 0) {
1443                         printf("L2 2MB data TLB: %d entries",
1444                             (regs[0] >> 16) & 0xfff);
1445                         print_AMD_l2_assoc(regs[0] >> 28);
1446                         printf("L2 2MB instruction TLB: %d entries",
1447                             regs[0] & 0xfff);
1448                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1449                 } else {
1450                         printf("L2 2MB unified TLB: %d entries",
1451                             regs[0] & 0xfff);
1452                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1453                 }
1454                 if ((regs[1] >> 16) != 0) {
1455                         printf("L2 4KB data TLB: %d entries",
1456                             (regs[1] >> 16) & 0xfff);
1457                         print_AMD_l2_assoc(regs[1] >> 28);
1458
1459                         printf("L2 4KB instruction TLB: %d entries",
1460                             (regs[1] >> 16) & 0xfff);
1461                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1462                 } else {
1463                         printf("L2 4KB unified TLB: %d entries",
1464                             (regs[1] >> 16) & 0xfff);
1465                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1466                 }
1467                 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1468                 printf(", %d bytes/line", regs[2] & 0xff);
1469                 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1470                 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1471         }
1472
1473 #ifdef __i386__
1474         if (((cpu_id & 0xf00) == 0x500)
1475             && (((cpu_id & 0x0f0) > 0x80)
1476                 || (((cpu_id & 0x0f0) == 0x80)
1477                     && (cpu_id & 0x00f) > 0x07))) {
1478                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1479                 amd_whcr = rdmsr(0xc0000082);
1480                 if (!(amd_whcr & (0x3ff << 22))) {
1481                         printf("Write Allocate Disable\n");
1482                 } else {
1483                         printf("Write Allocate Enable Limit: %dM bytes\n",
1484                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1485                         printf("Write Allocate 15-16M bytes: %s\n",
1486                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1487                 }
1488         } else if (((cpu_id & 0xf00) == 0x500)
1489                    && ((cpu_id & 0x0f0) > 0x50)) {
1490                 /* K6, K6-2(old core) */
1491                 amd_whcr = rdmsr(0xc0000082);
1492                 if (!(amd_whcr & (0x7f << 1))) {
1493                         printf("Write Allocate Disable\n");
1494                 } else {
1495                         printf("Write Allocate Enable Limit: %dM bytes\n",
1496                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1497                         printf("Write Allocate 15-16M bytes: %s\n",
1498                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
1499                         printf("Hardware Write Allocate Control: %s\n",
1500                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
1501                 }
1502         }
1503 #endif
1504         /*
1505          * Opteron Rev E shows a bug as in very rare occasions a read memory
1506          * barrier is not performed as expected if it is followed by a
1507          * non-atomic read-modify-write instruction.
1508          * As long as that bug pops up very rarely (intensive machine usage
1509          * on other operating systems generally generates one unexplainable
1510          * crash any 2 months) and as long as a model specific fix would be
1511          * impratical at this stage, print out a warning string if the broken
1512          * model and family are identified.
1513          */
1514         if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1515             CPUID_TO_MODEL(cpu_id) <= 0x3f)
1516                 printf("WARNING: This architecture revision has known SMP "
1517                     "hardware bugs which may cause random instability\n");
1518 }
1519
1520 static void
1521 print_INTEL_info(void)
1522 {
1523         u_int regs[4];
1524         u_int rounds, regnum;
1525         u_int nwaycode, nway;
1526
1527         if (cpu_high >= 2) {
1528                 rounds = 0;
1529                 do {
1530                         do_cpuid(0x2, regs);
1531                         if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1532                                 break;  /* we have a buggy CPU */
1533
1534                         for (regnum = 0; regnum <= 3; ++regnum) {
1535                                 if (regs[regnum] & (1<<31))
1536                                         continue;
1537                                 if (regnum != 0)
1538                                         print_INTEL_TLB(regs[regnum] & 0xff);
1539                                 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1540                                 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1541                                 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1542                         }
1543                 } while (--rounds > 0);
1544         }
1545
1546         if (cpu_exthigh >= 0x80000006) {
1547                 do_cpuid(0x80000006, regs);
1548                 nwaycode = (regs[2] >> 12) & 0x0f;
1549                 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1550                         nway = 1 << (nwaycode / 2);
1551                 else
1552                         nway = 0;
1553                 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1554                     (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1555         }
1556 }
1557
1558 static void
1559 print_INTEL_TLB(u_int data)
1560 {
1561         switch (data) {
1562         case 0x0:
1563         case 0x40:
1564         default:
1565                 break;
1566         case 0x1:
1567                 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1568                 break;
1569         case 0x2:
1570                 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1571                 break;
1572         case 0x3:
1573                 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1574                 break;
1575         case 0x4:
1576                 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1577                 break;
1578         case 0x6:
1579                 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1580                 break;
1581         case 0x8:
1582                 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
1583                 break;
1584         case 0xa:
1585                 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
1586                 break;
1587         case 0xc:
1588                 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
1589                 break;
1590         case 0x22:
1591                 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1592                 break;
1593         case 0x23:
1594                 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1595                 break;
1596         case 0x25:
1597                 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1598                 break;
1599         case 0x29:
1600                 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1601                 break;
1602         case 0x2c:
1603                 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
1604                 break;
1605         case 0x30:
1606                 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
1607                 break;
1608         case 0x39:
1609                 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1610                 break;
1611         case 0x3b:
1612                 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
1613                 break;
1614         case 0x3c:
1615                 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1616                 break;
1617         case 0x41:
1618                 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
1619                 break;
1620         case 0x42:
1621                 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
1622                 break;
1623         case 0x43:
1624                 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
1625                 break;
1626         case 0x44:
1627                 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
1628                 break;
1629         case 0x45:
1630                 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
1631                 break;
1632         case 0x46:
1633                 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
1634                 break;
1635         case 0x47:
1636                 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
1637                 break;
1638         case 0x50:
1639                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
1640                 break;
1641         case 0x51:
1642                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
1643                 break;
1644         case 0x52:
1645                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
1646                 break;
1647         case 0x5b:
1648                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
1649                 break;
1650         case 0x5c:
1651                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
1652                 break;
1653         case 0x5d:
1654                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
1655                 break;
1656         case 0x60:
1657                 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1658                 break;
1659         case 0x66:
1660                 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1661                 break;
1662         case 0x67:
1663                 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1664                 break;
1665         case 0x68:
1666                 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
1667                 break;
1668         case 0x70:
1669                 printf("Trace cache: 12K-uops, 8-way set associative\n");
1670                 break;
1671         case 0x71:
1672                 printf("Trace cache: 16K-uops, 8-way set associative\n");
1673                 break;
1674         case 0x72:
1675                 printf("Trace cache: 32K-uops, 8-way set associative\n");
1676                 break;
1677         case 0x78:
1678                 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
1679                 break;
1680         case 0x79:
1681                 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1682                 break;
1683         case 0x7a:
1684                 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1685                 break;
1686         case 0x7b:
1687                 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1688                 break;
1689         case 0x7c:
1690                 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1691                 break;
1692         case 0x7d:
1693                 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
1694                 break;
1695         case 0x7f:
1696                 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
1697                 break;
1698         case 0x82:
1699                 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
1700                 break;
1701         case 0x83:
1702                 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
1703                 break;
1704         case 0x84:
1705                 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
1706                 break;
1707         case 0x85:
1708                 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
1709                 break;
1710         case 0x86:
1711                 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
1712                 break;
1713         case 0x87:
1714                 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
1715                 break;
1716         case 0xb0:
1717                 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
1718                 break;
1719         case 0xb3:
1720                 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
1721                 break;
1722         }
1723 }
1724
1725 #ifdef __i386__
1726 static void
1727 print_transmeta_info(void)
1728 {
1729         u_int regs[4], nreg = 0;
1730
1731         do_cpuid(0x80860000, regs);
1732         nreg = regs[0];
1733         if (nreg >= 0x80860001) {
1734                 do_cpuid(0x80860001, regs);
1735                 printf("  Processor revision %u.%u.%u.%u\n",
1736                        (regs[1] >> 24) & 0xff,
1737                        (regs[1] >> 16) & 0xff,
1738                        (regs[1] >> 8) & 0xff,
1739                        regs[1] & 0xff);
1740         }
1741         if (nreg >= 0x80860002) {
1742                 do_cpuid(0x80860002, regs);
1743                 printf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
1744                        (regs[1] >> 24) & 0xff,
1745                        (regs[1] >> 16) & 0xff,
1746                        (regs[1] >> 8) & 0xff,
1747                        regs[1] & 0xff,
1748                        regs[2]);
1749         }
1750         if (nreg >= 0x80860006) {
1751                 char info[65];
1752                 do_cpuid(0x80860003, (u_int*) &info[0]);
1753                 do_cpuid(0x80860004, (u_int*) &info[16]);
1754                 do_cpuid(0x80860005, (u_int*) &info[32]);
1755                 do_cpuid(0x80860006, (u_int*) &info[48]);
1756                 info[64] = 0;
1757                 printf("  %s\n", info);
1758         }
1759 }
1760 #endif
1761
1762 static void
1763 print_via_padlock_info(void)
1764 {
1765         u_int regs[4];
1766
1767         do_cpuid(0xc0000001, regs);
1768         printf("\n  VIA Padlock Features=0x%b", regs[3],
1769         "\020"
1770         "\003RNG"               /* RNG */
1771         "\007AES"               /* ACE */
1772         "\011AES-CTR"           /* ACE2 */
1773         "\013SHA1,SHA256"       /* PHE */
1774         "\015RSA"               /* PMM */
1775         );
1776 }
1777
1778 static uint32_t
1779 vmx_settable(uint64_t basic, int msr, int true_msr)
1780 {
1781         uint64_t val;
1782
1783         if (basic & (1ULL << 55))
1784                 val = rdmsr(true_msr);
1785         else
1786                 val = rdmsr(msr);
1787
1788         /* Just report the controls that can be set to 1. */
1789         return (val >> 32);
1790 }
1791
1792 static void
1793 print_vmx_info(void)
1794 {
1795         uint64_t basic, msr;
1796         uint32_t entry, exit, mask, pin, proc, proc2;
1797         int comma;
1798
1799         printf("\n  VT-x: ");
1800         msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
1801         if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
1802                 printf("(disabled in BIOS) ");
1803         basic = rdmsr(MSR_VMX_BASIC);
1804         pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
1805             MSR_VMX_TRUE_PINBASED_CTLS);
1806         proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
1807             MSR_VMX_TRUE_PROCBASED_CTLS);
1808         if (proc & PROCBASED_SECONDARY_CONTROLS)
1809                 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
1810                     MSR_VMX_PROCBASED_CTLS2);
1811         else
1812                 proc2 = 0;
1813         exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
1814         entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
1815
1816         if (!bootverbose) {
1817                 comma = 0;
1818                 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
1819                     entry & VM_ENTRY_LOAD_PAT) {
1820                         printf("%sPAT", comma ? "," : "");
1821                         comma = 1;
1822                 }
1823                 if (proc & PROCBASED_HLT_EXITING) {
1824                         printf("%sHLT", comma ? "," : "");
1825                         comma = 1;
1826                 }
1827                 if (proc & PROCBASED_MTF) {
1828                         printf("%sMTF", comma ? "," : "");
1829                         comma = 1;
1830                 }
1831                 if (proc & PROCBASED_PAUSE_EXITING) {
1832                         printf("%sPAUSE", comma ? "," : "");
1833                         comma = 1;
1834                 }
1835                 if (proc2 & PROCBASED2_ENABLE_EPT) {
1836                         printf("%sEPT", comma ? "," : "");
1837                         comma = 1;
1838                 }
1839                 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
1840                         printf("%sUG", comma ? "," : "");
1841                         comma = 1;
1842                 }
1843                 if (proc2 & PROCBASED2_ENABLE_VPID) {
1844                         printf("%sVPID", comma ? "," : "");
1845                         comma = 1;
1846                 }
1847                 if (proc & PROCBASED_USE_TPR_SHADOW &&
1848                     proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
1849                     proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
1850                     proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
1851                     proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
1852                         printf("%sVID", comma ? "," : "");
1853                         comma = 1;
1854                         if (pin & PINBASED_POSTED_INTERRUPT)
1855                                 printf(",PostIntr");
1856                 }
1857                 return;
1858         }
1859
1860         mask = basic >> 32;
1861         printf("Basic Features=0x%b", mask,
1862         "\020"
1863         "\02132PA"              /* 32-bit physical addresses */
1864         "\022SMM"               /* SMM dual-monitor */
1865         "\027INS/OUTS"          /* VM-exit info for INS and OUTS */
1866         "\030TRUE"              /* TRUE_CTLS MSRs */
1867         );
1868         printf("\n        Pin-Based Controls=0x%b", pin,
1869         "\020"
1870         "\001ExtINT"            /* External-interrupt exiting */
1871         "\004NMI"               /* NMI exiting */
1872         "\006VNMI"              /* Virtual NMIs */
1873         "\007PreTmr"            /* Activate VMX-preemption timer */
1874         "\010PostIntr"          /* Process posted interrupts */
1875         );
1876         printf("\n        Primary Processor Controls=0x%b", proc,
1877         "\020"
1878         "\003INTWIN"            /* Interrupt-window exiting */
1879         "\004TSCOff"            /* Use TSC offsetting */
1880         "\010HLT"               /* HLT exiting */
1881         "\012INVLPG"            /* INVLPG exiting */
1882         "\013MWAIT"             /* MWAIT exiting */
1883         "\014RDPMC"             /* RDPMC exiting */
1884         "\015RDTSC"             /* RDTSC exiting */
1885         "\020CR3-LD"            /* CR3-load exiting */
1886         "\021CR3-ST"            /* CR3-store exiting */
1887         "\024CR8-LD"            /* CR8-load exiting */
1888         "\025CR8-ST"            /* CR8-store exiting */
1889         "\026TPR"               /* Use TPR shadow */
1890         "\027NMIWIN"            /* NMI-window exiting */
1891         "\030MOV-DR"            /* MOV-DR exiting */
1892         "\031IO"                /* Unconditional I/O exiting */
1893         "\032IOmap"             /* Use I/O bitmaps */
1894         "\034MTF"               /* Monitor trap flag */
1895         "\035MSRmap"            /* Use MSR bitmaps */
1896         "\036MONITOR"           /* MONITOR exiting */
1897         "\037PAUSE"             /* PAUSE exiting */
1898         );
1899         if (proc & PROCBASED_SECONDARY_CONTROLS)
1900                 printf("\n        Secondary Processor Controls=0x%b", proc2,
1901                 "\020"
1902                 "\001APIC"              /* Virtualize APIC accesses */
1903                 "\002EPT"               /* Enable EPT */
1904                 "\003DT"                /* Descriptor-table exiting */
1905                 "\004RDTSCP"            /* Enable RDTSCP */
1906                 "\005x2APIC"            /* Virtualize x2APIC mode */
1907                 "\006VPID"              /* Enable VPID */
1908                 "\007WBINVD"            /* WBINVD exiting */
1909                 "\010UG"                /* Unrestricted guest */
1910                 "\011APIC-reg"          /* APIC-register virtualization */
1911                 "\012VID"               /* Virtual-interrupt delivery */
1912                 "\013PAUSE-loop"        /* PAUSE-loop exiting */
1913                 "\014RDRAND"            /* RDRAND exiting */
1914                 "\015INVPCID"           /* Enable INVPCID */
1915                 "\016VMFUNC"            /* Enable VM functions */
1916                 "\017VMCS"              /* VMCS shadowing */
1917                 "\020EPT#VE"            /* EPT-violation #VE */
1918                 "\021XSAVES"            /* Enable XSAVES/XRSTORS */
1919                 );
1920         printf("\n        Exit Controls=0x%b", mask,
1921         "\020"
1922         "\003DR"                /* Save debug controls */
1923                                 /* Ignore Host address-space size */
1924         "\015PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
1925         "\020AckInt"            /* Acknowledge interrupt on exit */
1926         "\023PAT-SV"            /* Save MSR_PAT */
1927         "\024PAT-LD"            /* Load MSR_PAT */
1928         "\025EFER-SV"           /* Save MSR_EFER */
1929         "\026EFER-LD"           /* Load MSR_EFER */
1930         "\027PTMR-SV"           /* Save VMX-preemption timer value */
1931         );
1932         printf("\n        Entry Controls=0x%b", mask,
1933         "\020"
1934         "\003DR"                /* Save debug controls */
1935                                 /* Ignore IA-32e mode guest */
1936                                 /* Ignore Entry to SMM */
1937                                 /* Ignore Deactivate dual-monitor treatment */
1938         "\016PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
1939         "\017PAT"               /* Load MSR_PAT */
1940         "\020EFER"              /* Load MSR_EFER */
1941         );
1942         if (proc & PROCBASED_SECONDARY_CONTROLS &&
1943             (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
1944                 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
1945                 mask = msr;
1946                 printf("\n        EPT Features=0x%b", mask,
1947                 "\020"
1948                 "\001XO"                /* Execute-only translations */
1949                 "\007PW4"               /* Page-walk length of 4 */
1950                 "\011UC"                /* EPT paging-structure mem can be UC */
1951                 "\017WB"                /* EPT paging-structure mem can be WB */
1952                 "\0212M"                /* EPT PDE can map a 2-Mbyte page */
1953                 "\0221G"                /* EPT PDPTE can map a 1-Gbyte page */
1954                 "\025INVEPT"            /* INVEPT is supported */
1955                 "\026AD"                /* Accessed and dirty flags for EPT */
1956                 "\032single"            /* INVEPT single-context type */
1957                 "\033all"               /* INVEPT all-context type */
1958                 );
1959                 mask = msr >> 32;
1960                 printf("\n        VPID Features=0x%b", mask,
1961                 "\020"
1962                 "\001INVVPID"           /* INVVPID is supported */
1963                 "\011individual"        /* INVVPID individual-address type */
1964                 "\012single"            /* INVVPID single-context type */
1965                 "\013all"               /* INVVPID all-context type */
1966                  /* INVVPID single-context-retaining-globals type */
1967                 "\014single-globals"
1968                 );
1969         }
1970 }