2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/kernel.h>
40 #include <sys/malloc.h>
41 #include <sys/module.h>
42 #include <sys/mutex.h>
43 #include <sys/sysctl.h>
45 #include <dev/pci/pcireg.h>
46 #include <dev/pci/pcivar.h>
51 #include <x86/apicreg.h>
52 #include <machine/frame.h>
53 #include <machine/intr_machdep.h>
54 #include <machine/apicvar.h>
55 #include <machine/resource.h>
56 #include <machine/segments.h>
58 #define IOAPIC_ISA_INTS 16
59 #define IOAPIC_MEM_REGION 32
60 #define IOAPIC_REDTBL_LO(i) (IOAPIC_REDTBL + (i) * 2)
61 #define IOAPIC_REDTBL_HI(i) (IOAPIC_REDTBL_LO(i) + 1)
63 #define IRQ_EXTINT (NUM_IO_INTS + 1)
64 #define IRQ_NMI (NUM_IO_INTS + 2)
65 #define IRQ_SMI (NUM_IO_INTS + 3)
66 #define IRQ_DISABLED (NUM_IO_INTS + 4)
68 static MALLOC_DEFINE(M_IOAPIC, "io_apic", "I/O APIC structures");
71 * I/O APIC interrupt source driver. Each pin is assigned an IRQ cookie
72 * as laid out in the ACPI System Interrupt number model where each I/O
73 * APIC has a contiguous chunk of the System Interrupt address space.
74 * We assume that IRQs 1 - 15 behave like ISA IRQs and that all other
75 * IRQs behave as PCI IRQs by default. We also assume that the pin for
76 * IRQ 0 is actually an ExtINT pin. The apic enumerators override the
77 * configuration of individual pins as indicated by their tables.
79 * Documentation for the I/O APIC: "82093AA I/O Advanced Programmable
80 * Interrupt Controller (IOAPIC)", May 1996, Intel Corp.
81 * ftp://download.intel.com/design/chipsets/datashts/29056601.pdf
84 struct ioapic_intsrc {
85 struct intsrc io_intsrc;
91 u_int io_edgetrigger:1;
99 u_int io_id:8; /* logical ID */
101 u_int io_intbase:8; /* System Interrupt base */
103 volatile ioapic_t *io_addr; /* XXX: should use bus_space */
105 STAILQ_ENTRY(ioapic) io_next;
106 struct ioapic_intsrc io_pins[0];
109 static u_int ioapic_read(volatile ioapic_t *apic, int reg);
110 static void ioapic_write(volatile ioapic_t *apic, int reg, u_int val);
111 static const char *ioapic_bus_string(int bus_type);
112 static void ioapic_print_irq(struct ioapic_intsrc *intpin);
113 static void ioapic_enable_source(struct intsrc *isrc);
114 static void ioapic_disable_source(struct intsrc *isrc, int eoi);
115 static void ioapic_eoi_source(struct intsrc *isrc);
116 static void ioapic_enable_intr(struct intsrc *isrc);
117 static void ioapic_disable_intr(struct intsrc *isrc);
118 static int ioapic_vector(struct intsrc *isrc);
119 static int ioapic_source_pending(struct intsrc *isrc);
120 static int ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
121 enum intr_polarity pol);
122 static void ioapic_resume(struct pic *pic, bool suspend_cancelled);
123 static int ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id);
124 static void ioapic_program_intpin(struct ioapic_intsrc *intpin);
126 static STAILQ_HEAD(,ioapic) ioapic_list = STAILQ_HEAD_INITIALIZER(ioapic_list);
127 struct pic ioapic_template = { ioapic_enable_source, ioapic_disable_source,
128 ioapic_eoi_source, ioapic_enable_intr,
129 ioapic_disable_intr, ioapic_vector,
130 ioapic_source_pending, NULL, ioapic_resume,
131 ioapic_config_intr, ioapic_assign_cpu };
133 static int next_ioapic_base;
134 static u_int next_id;
136 static SYSCTL_NODE(_hw, OID_AUTO, apic, CTLFLAG_RD, 0, "APIC options");
137 static int enable_extint;
138 SYSCTL_INT(_hw_apic, OID_AUTO, enable_extint, CTLFLAG_RDTUN, &enable_extint, 0,
139 "Enable the ExtINT pin in the first I/O APIC");
140 TUNABLE_INT("hw.apic.enable_extint", &enable_extint);
143 _ioapic_eoi_source(struct intsrc *isrc)
149 ioapic_read(volatile ioapic_t *apic, int reg)
152 mtx_assert(&icu_lock, MA_OWNED);
153 apic->ioregsel = reg;
154 return (apic->iowin);
158 ioapic_write(volatile ioapic_t *apic, int reg, u_int val)
161 mtx_assert(&icu_lock, MA_OWNED);
162 apic->ioregsel = reg;
167 ioapic_bus_string(int bus_type)
183 ioapic_print_irq(struct ioapic_intsrc *intpin)
186 switch (intpin->io_irq) {
200 printf("%s IRQ %u", ioapic_bus_string(intpin->io_bus),
206 ioapic_enable_source(struct intsrc *isrc)
208 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
209 struct ioapic *io = (struct ioapic *)isrc->is_pic;
212 mtx_lock_spin(&icu_lock);
213 if (intpin->io_masked) {
214 flags = intpin->io_lowreg & ~IOART_INTMASK;
215 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
217 intpin->io_masked = 0;
219 mtx_unlock_spin(&icu_lock);
223 ioapic_disable_source(struct intsrc *isrc, int eoi)
225 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
226 struct ioapic *io = (struct ioapic *)isrc->is_pic;
229 mtx_lock_spin(&icu_lock);
230 if (!intpin->io_masked && !intpin->io_edgetrigger) {
231 flags = intpin->io_lowreg | IOART_INTMSET;
232 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
234 intpin->io_masked = 1;
238 _ioapic_eoi_source(isrc);
240 mtx_unlock_spin(&icu_lock);
244 ioapic_eoi_source(struct intsrc *isrc)
247 _ioapic_eoi_source(isrc);
251 * Completely program an intpin based on the data in its interrupt source
255 ioapic_program_intpin(struct ioapic_intsrc *intpin)
257 struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic;
258 uint32_t low, high, value;
261 * If a pin is completely invalid or if it is valid but hasn't
262 * been enabled yet, just ensure that the pin is masked.
264 mtx_assert(&icu_lock, MA_OWNED);
265 if (intpin->io_irq == IRQ_DISABLED || (intpin->io_irq < NUM_IO_INTS &&
266 intpin->io_vector == 0)) {
267 low = ioapic_read(io->io_addr,
268 IOAPIC_REDTBL_LO(intpin->io_intpin));
269 if ((low & IOART_INTMASK) == IOART_INTMCLR)
270 ioapic_write(io->io_addr,
271 IOAPIC_REDTBL_LO(intpin->io_intpin),
272 low | IOART_INTMSET);
276 /* Set the destination. */
278 high = intpin->io_cpu << APIC_ID_SHIFT;
280 /* Program the rest of the low word. */
281 if (intpin->io_edgetrigger)
282 low |= IOART_TRGREDG;
284 low |= IOART_TRGRLVL;
285 if (intpin->io_activehi)
289 if (intpin->io_masked)
290 low |= IOART_INTMSET;
291 switch (intpin->io_irq) {
293 KASSERT(intpin->io_edgetrigger,
294 ("ExtINT not edge triggered"));
295 low |= IOART_DELEXINT;
298 KASSERT(intpin->io_edgetrigger,
299 ("NMI not edge triggered"));
303 KASSERT(intpin->io_edgetrigger,
304 ("SMI not edge triggered"));
308 KASSERT(intpin->io_vector != 0, ("No vector for IRQ %u",
310 low |= IOART_DELFIXED | intpin->io_vector;
313 /* Write the values to the APIC. */
314 value = ioapic_read(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin));
315 value &= ~IOART_DEST;
317 ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), value);
318 intpin->io_lowreg = low;
319 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), low);
323 ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id)
325 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
326 struct ioapic *io = (struct ioapic *)isrc->is_pic;
327 u_int old_vector, new_vector;
331 * keep 1st core as the destination for NMI
333 if (intpin->io_irq == IRQ_NMI)
337 * Set us up to free the old irq.
339 old_vector = intpin->io_vector;
340 old_id = intpin->io_cpu;
341 if (old_vector && apic_id == old_id)
345 * Allocate an APIC vector for this interrupt pin. Once
346 * we have a vector we program the interrupt pin.
348 new_vector = apic_alloc_vector(apic_id, intpin->io_irq);
353 * Mask the old intpin if it is enabled while it is migrated.
355 * At least some level-triggered interrupts seem to need the
356 * extra DELAY() to avoid being stuck in a non-EOI'd state.
358 mtx_lock_spin(&icu_lock);
359 if (!intpin->io_masked && !intpin->io_edgetrigger) {
360 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
361 intpin->io_lowreg | IOART_INTMSET);
362 mtx_unlock_spin(&icu_lock);
364 mtx_lock_spin(&icu_lock);
367 intpin->io_cpu = apic_id;
368 intpin->io_vector = new_vector;
369 if (isrc->is_handlers > 0)
370 apic_enable_vector(intpin->io_cpu, intpin->io_vector);
372 printf("ioapic%u: routing intpin %u (", io->io_id,
374 ioapic_print_irq(intpin);
375 printf(") to lapic %u vector %u\n", intpin->io_cpu,
378 ioapic_program_intpin(intpin);
379 mtx_unlock_spin(&icu_lock);
382 * Free the old vector after the new one is established. This is done
383 * to prevent races where we could miss an interrupt.
386 if (isrc->is_handlers > 0)
387 apic_disable_vector(old_id, old_vector);
388 apic_free_vector(old_id, old_vector, intpin->io_irq);
394 ioapic_enable_intr(struct intsrc *isrc)
396 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
398 if (intpin->io_vector == 0)
399 if (ioapic_assign_cpu(isrc, intr_next_cpu()) != 0)
400 panic("Couldn't find an APIC vector for IRQ %d",
402 apic_enable_vector(intpin->io_cpu, intpin->io_vector);
407 ioapic_disable_intr(struct intsrc *isrc)
409 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
412 if (intpin->io_vector != 0) {
413 /* Mask this interrupt pin and free its APIC vector. */
414 vector = intpin->io_vector;
415 apic_disable_vector(intpin->io_cpu, vector);
416 mtx_lock_spin(&icu_lock);
417 intpin->io_masked = 1;
418 intpin->io_vector = 0;
419 ioapic_program_intpin(intpin);
420 mtx_unlock_spin(&icu_lock);
421 apic_free_vector(intpin->io_cpu, vector, intpin->io_irq);
426 ioapic_vector(struct intsrc *isrc)
428 struct ioapic_intsrc *pin;
430 pin = (struct ioapic_intsrc *)isrc;
431 return (pin->io_irq);
435 ioapic_source_pending(struct intsrc *isrc)
437 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
439 if (intpin->io_vector == 0)
441 return (lapic_intr_pending(intpin->io_vector));
445 ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
446 enum intr_polarity pol)
448 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
449 struct ioapic *io = (struct ioapic *)isrc->is_pic;
452 KASSERT(!(trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM),
453 ("%s: Conforming trigger or polarity\n", __func__));
456 * EISA interrupts always use active high polarity, so don't allow
457 * them to be set to active low.
459 * XXX: Should we write to the ELCR if the trigger mode changes for
460 * an EISA IRQ or an ISA IRQ with the ELCR present?
462 mtx_lock_spin(&icu_lock);
463 if (intpin->io_bus == APIC_BUS_EISA)
464 pol = INTR_POLARITY_HIGH;
466 if (intpin->io_edgetrigger != (trig == INTR_TRIGGER_EDGE)) {
468 printf("ioapic%u: Changing trigger for pin %u to %s\n",
469 io->io_id, intpin->io_intpin,
470 trig == INTR_TRIGGER_EDGE ? "edge" : "level");
471 intpin->io_edgetrigger = (trig == INTR_TRIGGER_EDGE);
474 if (intpin->io_activehi != (pol == INTR_POLARITY_HIGH)) {
476 printf("ioapic%u: Changing polarity for pin %u to %s\n",
477 io->io_id, intpin->io_intpin,
478 pol == INTR_POLARITY_HIGH ? "high" : "low");
479 intpin->io_activehi = (pol == INTR_POLARITY_HIGH);
483 ioapic_program_intpin(intpin);
484 mtx_unlock_spin(&icu_lock);
489 ioapic_resume(struct pic *pic, bool suspend_cancelled)
491 struct ioapic *io = (struct ioapic *)pic;
494 mtx_lock_spin(&icu_lock);
495 for (i = 0; i < io->io_numintr; i++)
496 ioapic_program_intpin(&io->io_pins[i]);
497 mtx_unlock_spin(&icu_lock);
501 * Create a plain I/O APIC object.
504 ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase)
507 struct ioapic_intsrc *intpin;
508 volatile ioapic_t *apic;
512 /* Map the register window so we can access the device. */
513 apic = pmap_mapdev(addr, IOAPIC_MEM_REGION);
514 mtx_lock_spin(&icu_lock);
515 value = ioapic_read(apic, IOAPIC_VER);
516 mtx_unlock_spin(&icu_lock);
518 /* If it's version register doesn't seem to work, punt. */
519 if (value == 0xffffffff) {
520 pmap_unmapdev((vm_offset_t)apic, IOAPIC_MEM_REGION);
524 /* Determine the number of vectors and set the APIC ID. */
525 numintr = ((value & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1;
526 io = malloc(sizeof(struct ioapic) +
527 numintr * sizeof(struct ioapic_intsrc), M_IOAPIC, M_WAITOK);
528 io->io_pic = ioapic_template;
529 mtx_lock_spin(&icu_lock);
530 io->io_id = next_id++;
531 io->io_apic_id = ioapic_read(apic, IOAPIC_ID) >> APIC_ID_SHIFT;
532 if (apic_id != -1 && io->io_apic_id != apic_id) {
533 ioapic_write(apic, IOAPIC_ID, apic_id << APIC_ID_SHIFT);
534 mtx_unlock_spin(&icu_lock);
535 io->io_apic_id = apic_id;
536 printf("ioapic%u: Changing APIC ID to %d\n", io->io_id,
539 mtx_unlock_spin(&icu_lock);
541 intbase = next_ioapic_base;
542 printf("ioapic%u: Assuming intbase of %d\n", io->io_id,
544 } else if (intbase != next_ioapic_base && bootverbose)
545 printf("ioapic%u: WARNING: intbase %d != expected base %d\n",
546 io->io_id, intbase, next_ioapic_base);
547 io->io_intbase = intbase;
548 next_ioapic_base = intbase + numintr;
549 io->io_numintr = numintr;
554 * Initialize pins. Start off with interrupts disabled. Default
555 * to active-hi and edge-triggered for ISA interrupts and active-lo
556 * and level-triggered for all others.
558 bzero(io->io_pins, sizeof(struct ioapic_intsrc) * numintr);
559 mtx_lock_spin(&icu_lock);
560 for (i = 0, intpin = io->io_pins; i < numintr; i++, intpin++) {
561 intpin->io_intsrc.is_pic = (struct pic *)io;
562 intpin->io_intpin = i;
563 intpin->io_irq = intbase + i;
566 * Assume that pin 0 on the first I/O APIC is an ExtINT pin.
567 * Assume that pins 1-15 are ISA interrupts and that all
568 * other pins are PCI interrupts.
570 if (intpin->io_irq == 0)
571 ioapic_set_extint(io, i);
572 else if (intpin->io_irq < IOAPIC_ISA_INTS) {
573 intpin->io_bus = APIC_BUS_ISA;
574 intpin->io_activehi = 1;
575 intpin->io_edgetrigger = 1;
576 intpin->io_masked = 1;
578 intpin->io_bus = APIC_BUS_PCI;
579 intpin->io_activehi = 0;
580 intpin->io_edgetrigger = 0;
581 intpin->io_masked = 1;
585 * Route interrupts to the BSP by default. Interrupts may
586 * be routed to other CPUs later after they are enabled.
588 intpin->io_cpu = PCPU_GET(apic_id);
589 value = ioapic_read(apic, IOAPIC_REDTBL_LO(i));
590 ioapic_write(apic, IOAPIC_REDTBL_LO(i), value | IOART_INTMSET);
592 mtx_unlock_spin(&icu_lock);
598 ioapic_get_vector(void *cookie, u_int pin)
602 io = (struct ioapic *)cookie;
603 if (pin >= io->io_numintr)
605 return (io->io_pins[pin].io_irq);
609 ioapic_disable_pin(void *cookie, u_int pin)
613 io = (struct ioapic *)cookie;
614 if (pin >= io->io_numintr)
616 if (io->io_pins[pin].io_irq == IRQ_DISABLED)
618 io->io_pins[pin].io_irq = IRQ_DISABLED;
620 printf("ioapic%u: intpin %d disabled\n", io->io_id, pin);
625 ioapic_remap_vector(void *cookie, u_int pin, int vector)
629 io = (struct ioapic *)cookie;
630 if (pin >= io->io_numintr || vector < 0)
632 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
634 io->io_pins[pin].io_irq = vector;
636 printf("ioapic%u: Routing IRQ %d -> intpin %d\n", io->io_id,
642 ioapic_set_bus(void *cookie, u_int pin, int bus_type)
646 if (bus_type < 0 || bus_type > APIC_BUS_MAX)
648 io = (struct ioapic *)cookie;
649 if (pin >= io->io_numintr)
651 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
653 if (io->io_pins[pin].io_bus == bus_type)
655 io->io_pins[pin].io_bus = bus_type;
657 printf("ioapic%u: intpin %d bus %s\n", io->io_id, pin,
658 ioapic_bus_string(bus_type));
663 ioapic_set_nmi(void *cookie, u_int pin)
667 io = (struct ioapic *)cookie;
668 if (pin >= io->io_numintr)
670 if (io->io_pins[pin].io_irq == IRQ_NMI)
672 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
674 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
675 io->io_pins[pin].io_irq = IRQ_NMI;
676 io->io_pins[pin].io_masked = 0;
677 io->io_pins[pin].io_edgetrigger = 1;
678 io->io_pins[pin].io_activehi = 1;
680 printf("ioapic%u: Routing NMI -> intpin %d\n",
686 ioapic_set_smi(void *cookie, u_int pin)
690 io = (struct ioapic *)cookie;
691 if (pin >= io->io_numintr)
693 if (io->io_pins[pin].io_irq == IRQ_SMI)
695 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
697 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
698 io->io_pins[pin].io_irq = IRQ_SMI;
699 io->io_pins[pin].io_masked = 0;
700 io->io_pins[pin].io_edgetrigger = 1;
701 io->io_pins[pin].io_activehi = 1;
703 printf("ioapic%u: Routing SMI -> intpin %d\n",
709 ioapic_set_extint(void *cookie, u_int pin)
713 io = (struct ioapic *)cookie;
714 if (pin >= io->io_numintr)
716 if (io->io_pins[pin].io_irq == IRQ_EXTINT)
718 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
720 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
721 io->io_pins[pin].io_irq = IRQ_EXTINT;
723 io->io_pins[pin].io_masked = 0;
725 io->io_pins[pin].io_masked = 1;
726 io->io_pins[pin].io_edgetrigger = 1;
727 io->io_pins[pin].io_activehi = 1;
729 printf("ioapic%u: Routing external 8259A's -> intpin %d\n",
735 ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol)
740 io = (struct ioapic *)cookie;
741 if (pin >= io->io_numintr || pol == INTR_POLARITY_CONFORM)
743 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
745 activehi = (pol == INTR_POLARITY_HIGH);
746 if (io->io_pins[pin].io_activehi == activehi)
748 io->io_pins[pin].io_activehi = activehi;
750 printf("ioapic%u: intpin %d polarity: %s\n", io->io_id, pin,
751 pol == INTR_POLARITY_HIGH ? "high" : "low");
756 ioapic_set_triggermode(void *cookie, u_int pin, enum intr_trigger trigger)
761 io = (struct ioapic *)cookie;
762 if (pin >= io->io_numintr || trigger == INTR_TRIGGER_CONFORM)
764 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
766 edgetrigger = (trigger == INTR_TRIGGER_EDGE);
767 if (io->io_pins[pin].io_edgetrigger == edgetrigger)
769 io->io_pins[pin].io_edgetrigger = edgetrigger;
771 printf("ioapic%u: intpin %d trigger: %s\n", io->io_id, pin,
772 trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
777 * Register a complete I/O APIC object with the interrupt subsystem.
780 ioapic_register(void *cookie)
782 struct ioapic_intsrc *pin;
784 volatile ioapic_t *apic;
788 io = (struct ioapic *)cookie;
790 mtx_lock_spin(&icu_lock);
791 flags = ioapic_read(apic, IOAPIC_VER) & IOART_VER_VERSION;
792 STAILQ_INSERT_TAIL(&ioapic_list, io, io_next);
793 mtx_unlock_spin(&icu_lock);
794 printf("ioapic%u <Version %u.%u> irqs %u-%u on motherboard\n",
795 io->io_id, flags >> 4, flags & 0xf, io->io_intbase,
796 io->io_intbase + io->io_numintr - 1);
798 /* Register valid pins as interrupt sources. */
799 intr_register_pic(&io->io_pic);
800 for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++)
801 if (pin->io_irq < NUM_IO_INTS)
802 intr_register_source(&pin->io_intsrc);
805 /* A simple new-bus driver to consume PCI I/O APIC devices. */
807 ioapic_pci_probe(device_t dev)
810 if (pci_get_class(dev) == PCIC_BASEPERIPH &&
811 pci_get_subclass(dev) == PCIS_BASEPERIPH_PIC) {
812 switch (pci_get_progif(dev)) {
813 case PCIP_BASEPERIPH_PIC_IO_APIC:
814 device_set_desc(dev, "IO APIC");
816 case PCIP_BASEPERIPH_PIC_IOX_APIC:
817 device_set_desc(dev, "IO(x) APIC");
829 ioapic_pci_attach(device_t dev)
835 static device_method_t ioapic_pci_methods[] = {
836 /* Device interface */
837 DEVMETHOD(device_probe, ioapic_pci_probe),
838 DEVMETHOD(device_attach, ioapic_pci_attach),
843 DEFINE_CLASS_0(ioapic, ioapic_pci_driver, ioapic_pci_methods, 0);
845 static devclass_t ioapic_devclass;
846 DRIVER_MODULE(ioapic, pci, ioapic_pci_driver, ioapic_devclass, 0, 0);
849 * A new-bus driver to consume the memory resources associated with
850 * the APICs in the system. On some systems ACPI or PnPBIOS system
851 * resource devices may already claim these resources. To keep from
852 * breaking those devices, we attach ourself to the nexus device after
853 * legacy0 and acpi0 and ignore any allocation failures.
856 apic_identify(driver_t *driver, device_t parent)
860 * Add at order 12. acpi0 is probed at order 10 and legacy0
861 * is probed at order 11.
863 if (lapic_paddr != 0)
864 BUS_ADD_CHILD(parent, 12, "apic", 0);
868 apic_probe(device_t dev)
871 device_set_desc(dev, "APIC resources");
877 apic_add_resource(device_t dev, int rid, vm_paddr_t base, size_t length)
883 * Resources use long's to track resources, so we can't
884 * include memory regions above 4GB.
889 error = bus_set_resource(dev, SYS_RES_MEMORY, rid, base, length);
891 panic("apic_add_resource: resource %d failed set with %d", rid,
893 bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 0);
897 apic_attach(device_t dev)
902 /* Reserve the local APIC. */
903 apic_add_resource(dev, 0, lapic_paddr, sizeof(lapic_t));
905 STAILQ_FOREACH(io, &ioapic_list, io_next) {
906 apic_add_resource(dev, i, io->io_paddr, IOAPIC_MEM_REGION);
912 static device_method_t apic_methods[] = {
913 /* Device interface */
914 DEVMETHOD(device_identify, apic_identify),
915 DEVMETHOD(device_probe, apic_probe),
916 DEVMETHOD(device_attach, apic_attach),
921 DEFINE_CLASS_0(apic, apic_driver, apic_methods, 0);
923 static devclass_t apic_devclass;
924 DRIVER_MODULE(apic, nexus, apic_driver, apic_devclass, 0, 0);