2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * Copyright (c) 1996, by Steve Passe
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * Local APIC support on Pentium and later processors.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include "opt_hwpmc_hooks.h"
38 #include "opt_kdtrace.h"
42 #include <sys/param.h>
43 #include <sys/systm.h>
45 #include <sys/kernel.h>
47 #include <sys/mutex.h>
50 #include <sys/sched.h>
56 #include <machine/apicreg.h>
57 #include <machine/cpu.h>
58 #include <machine/cputypes.h>
59 #include <machine/frame.h>
60 #include <machine/intr_machdep.h>
61 #include <machine/apicvar.h>
62 #include <machine/mca.h>
63 #include <machine/md_var.h>
64 #include <machine/smp.h>
65 #include <machine/specialreg.h>
68 #include <sys/interrupt.h>
73 #define SDT_APIC SDT_SYSIGT
74 #define SDT_APICT SDT_SYSIGT
77 #define SDT_APIC SDT_SYS386IGT
78 #define SDT_APICT SDT_SYS386TGT
79 #define GSEL_APIC GSEL(GCODE_SEL, SEL_KPL)
83 #include <sys/dtrace_bsd.h>
84 cyclic_clock_func_t cyclic_clock_func[MAXCPU];
87 /* Sanity checks on IDT vectors. */
88 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT);
89 CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS);
90 CTASSERT(APIC_LOCAL_INTS == 240);
91 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT);
93 /* Magic IRQ values for the timer and syscalls. */
94 #define IRQ_TIMER (NUM_IO_INTS + 1)
95 #define IRQ_SYSCALL (NUM_IO_INTS + 2)
96 #define IRQ_DTRACE_RET (NUM_IO_INTS + 3)
99 * Support for local APICs. Local APICs manage interrupts on each
100 * individual processor as opposed to I/O APICs which receive interrupts
101 * from I/O devices and then forward them on to the local APICs.
103 * Local APICs can also send interrupts to each other thus providing the
104 * mechanism for IPIs.
108 u_int lvt_edgetrigger:1;
109 u_int lvt_activehi:1;
117 struct lvt la_lvts[LVT_MAX + 1];
120 u_int la_cluster_id:2;
122 u_long *la_timer_count;
123 u_long la_hard_ticks;
124 u_long la_stat_ticks;
125 u_long la_prof_ticks;
126 /* Include IDT_SYSCALL to make indexing easier. */
127 int la_ioint_irqs[APIC_NUM_IOINTS + 1];
128 } static lapics[MAX_APIC_ID + 1];
130 /* Global defaults for local APIC LVT entries. */
131 static struct lvt lvts[LVT_MAX + 1] = {
132 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */
133 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */
134 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */
135 { 1, 1, 0, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */
136 { 1, 1, 1, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */
137 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */
138 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_CMC_INT }, /* CMCI */
141 static inthand_t *ioint_handlers[] = {
143 IDTVEC(apic_isr1), /* 32 - 63 */
144 IDTVEC(apic_isr2), /* 64 - 95 */
145 IDTVEC(apic_isr3), /* 96 - 127 */
146 IDTVEC(apic_isr4), /* 128 - 159 */
147 IDTVEC(apic_isr5), /* 160 - 191 */
148 IDTVEC(apic_isr6), /* 192 - 223 */
149 IDTVEC(apic_isr7), /* 224 - 255 */
153 static u_int32_t lapic_timer_divisors[] = {
154 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
155 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128
158 extern inthand_t IDTVEC(rsvd);
160 volatile lapic_t *lapic;
161 vm_paddr_t lapic_paddr;
162 static u_long lapic_timer_divisor, lapic_timer_period, lapic_timer_hz;
163 static enum lapic_clock clockcoverage;
165 static void lapic_enable(void);
166 static void lapic_resume(struct pic *pic);
167 static void lapic_timer_enable_intr(void);
168 static void lapic_timer_oneshot(u_int count);
169 static void lapic_timer_periodic(u_int count);
170 static void lapic_timer_set_divisor(u_int divisor);
171 static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value);
173 struct pic lapic_pic = { .pic_resume = lapic_resume };
176 lvt_mode(struct lapic *la, u_int pin, uint32_t value)
180 KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin));
181 if (la->la_lvts[pin].lvt_active)
182 lvt = &la->la_lvts[pin];
186 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM |
188 if (lvt->lvt_edgetrigger == 0)
189 value |= APIC_LVT_TM;
190 if (lvt->lvt_activehi == 0)
191 value |= APIC_LVT_IIPP_INTALO;
194 value |= lvt->lvt_mode;
195 switch (lvt->lvt_mode) {
196 case APIC_LVT_DM_NMI:
197 case APIC_LVT_DM_SMI:
198 case APIC_LVT_DM_INIT:
199 case APIC_LVT_DM_EXTINT:
200 if (!lvt->lvt_edgetrigger) {
201 printf("lapic%u: Forcing LINT%u to edge trigger\n",
203 value |= APIC_LVT_TM;
205 /* Use a vector of 0. */
207 case APIC_LVT_DM_FIXED:
208 value |= lvt->lvt_vector;
211 panic("bad APIC LVT delivery mode: %#x\n", value);
217 * Map the local APIC and setup necessary interrupt vectors.
220 lapic_init(vm_paddr_t addr)
223 /* Map the local APIC and setup the spurious interrupt handler. */
224 KASSERT(trunc_page(addr) == addr,
225 ("local APIC not aligned on a page boundary"));
226 lapic = pmap_mapdev(addr, sizeof(lapic_t));
228 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_APIC, SEL_KPL,
231 /* Perform basic initialization of the BSP's local APIC. */
234 /* Set BSP's per-CPU local APIC ID. */
235 PCPU_SET(apic_id, lapic_id());
237 /* Local APIC timer interrupt. */
238 setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_APIC, SEL_KPL, GSEL_APIC);
240 /* Local APIC error interrupt. */
241 setidt(APIC_ERROR_INT, IDTVEC(errorint), SDT_APIC, SEL_KPL, GSEL_APIC);
243 /* XXX: Thermal interrupt */
245 /* Local APIC CMCI. */
246 setidt(APIC_CMC_INT, IDTVEC(cmcint), SDT_APICT, SEL_KPL,
247 GSEL(GCODE_SEL, SEL_KPL));
251 * Create a local APIC instance.
254 lapic_create(u_int apic_id, int boot_cpu)
258 if (apic_id > MAX_APIC_ID) {
259 printf("APIC: Ignoring local APIC with ID %d\n", apic_id);
261 panic("Can't ignore BSP");
264 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u",
268 * Assume no local LVT overrides and a cluster of 0 and
269 * intra-cluster ID of 0.
271 lapics[apic_id].la_present = 1;
272 lapics[apic_id].la_id = apic_id;
273 for (i = 0; i <= LVT_MAX; i++) {
274 lapics[apic_id].la_lvts[i] = lvts[i];
275 lapics[apic_id].la_lvts[i].lvt_active = 0;
277 for (i = 0; i <= APIC_NUM_IOINTS; i++)
278 lapics[apic_id].la_ioint_irqs[i] = -1;
279 lapics[apic_id].la_ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL;
280 lapics[apic_id].la_ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] =
283 lapics[apic_id].la_ioint_irqs[IDT_DTRACE_RET - APIC_IO_INTS] = IRQ_DTRACE_RET;
288 cpu_add(apic_id, boot_cpu);
293 * Dump contents of local APIC registers
296 lapic_dump(const char* str)
300 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
301 printf("cpu%d %s:\n", PCPU_GET(cpuid), str);
302 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n",
303 lapic->id, lapic->version, lapic->ldr, lapic->dfr);
304 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
305 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
306 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x",
307 lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error);
308 if (maxlvt >= LVT_PMC)
309 printf(" pmc: 0x%08x", lapic->lvt_pcint);
311 if (maxlvt >= LVT_CMCI)
312 printf(" cmci: 0x%08x\n", lapic->lvt_cmci);
316 lapic_setup(int boot)
321 char buf[MAXCOMLEN + 1];
323 la = &lapics[lapic_id()];
324 KASSERT(la->la_present, ("missing APIC structure"));
325 saveintr = intr_disable();
326 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
328 /* Initialize the TPR to allow all interrupts. */
331 /* Setup spurious vector and enable the local APIC. */
334 /* Program LINT[01] LVT entries. */
335 lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0);
336 lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1);
338 /* Program the PMC LVT entry if present. */
339 if (maxlvt >= LVT_PMC)
340 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint);
342 /* Program timer LVT and setup handler. */
343 lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer);
345 snprintf(buf, sizeof(buf), "cpu%d: timer", PCPU_GET(cpuid));
346 intrcnt_add(buf, &la->la_timer_count);
349 /* We don't setup the timer during boot on the BSP until later. */
350 if (!(boot && PCPU_GET(cpuid) == 0) && lapic_timer_hz != 0) {
351 KASSERT(lapic_timer_period != 0, ("lapic%u: zero divisor",
353 lapic_timer_set_divisor(lapic_timer_divisor);
354 lapic_timer_periodic(lapic_timer_period);
355 lapic_timer_enable_intr();
358 /* Program error LVT and clear any existing errors. */
359 lapic->lvt_error = lvt_mode(la, LVT_ERROR, lapic->lvt_error);
362 /* XXX: Thermal LVT */
364 /* Program the CMCI LVT entry if present. */
365 if (maxlvt >= LVT_CMCI)
366 lapic->lvt_cmci = lvt_mode(la, LVT_CMCI, lapic->lvt_cmci);
368 intr_restore(saveintr);
372 lapic_reenable_pmc(void)
377 value = lapic->lvt_pcint;
378 value &= ~APIC_LVT_M;
379 lapic->lvt_pcint = value;
385 lapic_update_pmc(void *dummy)
389 la = &lapics[lapic_id()];
390 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint);
395 lapic_enable_pmc(void)
400 /* Fail if the local APIC is not present. */
404 /* Fail if the PMC LVT is not present. */
405 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
406 if (maxlvt < LVT_PMC)
409 lvts[LVT_PMC].lvt_masked = 0;
413 * If hwpmc was loaded at boot time then the APs may not be
414 * started yet. In that case, don't forward the request to
415 * them as they will program the lvt when they start.
418 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL);
421 lapic_update_pmc(NULL);
429 lapic_disable_pmc(void)
434 /* Fail if the local APIC is not present. */
438 /* Fail if the PMC LVT is not present. */
439 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
440 if (maxlvt < LVT_PMC)
443 lvts[LVT_PMC].lvt_masked = 1;
446 /* The APs should always be started when hwpmc is unloaded. */
447 KASSERT(mp_ncpus == 1 || smp_started, ("hwpmc unloaded too early"));
449 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL);
454 * Called by cpu_initclocks() on the BSP to setup the local APIC timer so
455 * that it can drive hardclock, statclock, and profclock.
458 lapic_setup_clock(enum lapic_clock srcsdes)
463 /* lapic_setup_clock() should not be called with LAPIC_CLOCK_NONE. */
464 MPASS(srcsdes != LAPIC_CLOCK_NONE);
466 /* Can't drive the timer without a local APIC. */
468 (resource_int_value("apic", 0, "clock", &i) == 0 && i == 0)) {
469 clockcoverage = LAPIC_CLOCK_NONE;
470 return (clockcoverage);
473 /* Start off with a divisor of 2 (power on reset default). */
474 lapic_timer_divisor = 2;
476 /* Try to calibrate the local APIC timer. */
478 lapic_timer_set_divisor(lapic_timer_divisor);
479 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
481 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
482 if (value != APIC_TIMER_MAX_COUNT)
484 lapic_timer_divisor <<= 1;
485 } while (lapic_timer_divisor <= 128);
486 if (lapic_timer_divisor > 128)
487 panic("lapic: Divisor too big");
490 printf("lapic: Divisor %lu, Frequency %lu Hz\n",
491 lapic_timer_divisor, value);
494 * We want to run stathz in the neighborhood of 128hz. We would
495 * like profhz to run as often as possible, so we let it run on
496 * each clock tick. We try to honor the requested 'hz' value as
499 * If 'hz' is above 1500, then we just let the lapic timer
500 * (and profhz) run at hz. If 'hz' is below 1500 but above
501 * 750, then we let the lapic timer run at 2 * 'hz'. If 'hz'
502 * is below 750 then we let the lapic timer run at 4 * 'hz'.
504 * Please note that stathz and profhz are set only if all the
505 * clocks are handled through the local APIC.
507 if (srcsdes == LAPIC_CLOCK_ALL) {
511 lapic_timer_hz = hz * 2;
513 lapic_timer_hz = hz * 4;
516 lapic_timer_period = value / lapic_timer_hz;
517 if (srcsdes == LAPIC_CLOCK_ALL) {
518 if (lapic_timer_hz < 128)
519 stathz = lapic_timer_hz;
521 stathz = lapic_timer_hz / (lapic_timer_hz / 128);
522 profhz = lapic_timer_hz;
526 * Start up the timer on the BSP. The APs will kick off their
527 * timer during lapic_setup().
529 lapic_timer_periodic(lapic_timer_period);
530 lapic_timer_enable_intr();
531 clockcoverage = srcsdes;
540 /* Software disable the local APIC. */
542 value &= ~APIC_SVR_SWEN;
551 /* Program the spurious vector to enable the local APIC. */
553 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS);
554 value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT);
558 /* Reset the local APIC on the BSP during resume. */
560 lapic_resume(struct pic *pic)
570 KASSERT(lapic != NULL, ("local APIC is not mapped"));
571 return (lapic->id >> APIC_ID_SHIFT);
575 lapic_intr_pending(u_int vector)
577 volatile u_int32_t *irr;
580 * The IRR registers are an array of 128-bit registers each of
581 * which only describes 32 interrupts in the low 32 bits.. Thus,
582 * we divide the vector by 32 to get the 128-bit index. We then
583 * multiply that index by 4 to get the equivalent index from
584 * treating the IRR as an array of 32-bit registers. Finally, we
585 * modulus the vector by 32 to determine the individual bit to
589 return (irr[(vector / 32) * 4] & 1 << (vector % 32));
593 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id)
597 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist",
599 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big",
601 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID,
602 ("%s: intra cluster id %u too big", __func__, cluster_id));
603 la = &lapics[apic_id];
604 la->la_cluster = cluster;
605 la->la_cluster_id = cluster_id;
609 lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked)
614 if (apic_id == APIC_ID_ALL) {
615 lvts[pin].lvt_masked = masked;
619 KASSERT(lapics[apic_id].la_present,
620 ("%s: missing APIC %u", __func__, apic_id));
621 lapics[apic_id].la_lvts[pin].lvt_masked = masked;
622 lapics[apic_id].la_lvts[pin].lvt_active = 1;
624 printf("lapic%u:", apic_id);
627 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked");
632 lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode)
638 if (apic_id == APIC_ID_ALL) {
643 KASSERT(lapics[apic_id].la_present,
644 ("%s: missing APIC %u", __func__, apic_id));
645 lvt = &lapics[apic_id].la_lvts[pin];
648 printf("lapic%u:", apic_id);
650 lvt->lvt_mode = mode;
652 case APIC_LVT_DM_NMI:
653 case APIC_LVT_DM_SMI:
654 case APIC_LVT_DM_INIT:
655 case APIC_LVT_DM_EXTINT:
656 lvt->lvt_edgetrigger = 1;
657 lvt->lvt_activehi = 1;
658 if (mode == APIC_LVT_DM_EXTINT)
664 panic("Unsupported delivery mode: 0x%x\n", mode);
669 case APIC_LVT_DM_NMI:
672 case APIC_LVT_DM_SMI:
675 case APIC_LVT_DM_INIT:
678 case APIC_LVT_DM_EXTINT:
682 printf(" -> LINT%u\n", pin);
688 lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol)
691 if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM)
693 if (apic_id == APIC_ID_ALL) {
694 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH);
698 KASSERT(lapics[apic_id].la_present,
699 ("%s: missing APIC %u", __func__, apic_id));
700 lapics[apic_id].la_lvts[pin].lvt_active = 1;
701 lapics[apic_id].la_lvts[pin].lvt_activehi =
702 (pol == INTR_POLARITY_HIGH);
704 printf("lapic%u:", apic_id);
707 printf(" LINT%u polarity: %s\n", pin,
708 pol == INTR_POLARITY_HIGH ? "high" : "low");
713 lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger)
716 if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM)
718 if (apic_id == APIC_ID_ALL) {
719 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE);
723 KASSERT(lapics[apic_id].la_present,
724 ("%s: missing APIC %u", __func__, apic_id));
725 lapics[apic_id].la_lvts[pin].lvt_edgetrigger =
726 (trigger == INTR_TRIGGER_EDGE);
727 lapics[apic_id].la_lvts[pin].lvt_active = 1;
729 printf("lapic%u:", apic_id);
732 printf(" LINT%u trigger: %s\n", pin,
733 trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
738 * Adjust the TPR of the current CPU so that it blocks all interrupts below
739 * the passed in vector.
742 lapic_set_tpr(u_int vector)
749 tpr = lapic->tpr & ~APIC_TPR_PRIO;
763 lapic_handle_intr(int vector, struct trapframe *frame)
768 panic("Couldn't get vector from ISR!");
769 isrc = intr_lookup_source(apic_idt_to_irq(PCPU_GET(apic_id),
771 intr_execute_handlers(isrc, frame);
775 lapic_handle_timer(struct trapframe *frame)
779 /* Send EOI first thing. */
782 #if defined(SMP) && !defined(SCHED_ULE)
784 * Don't do any accounting for the disabled HTT cores, since it
785 * will provide misleading numbers for the userland.
787 * No locking is necessary here, since even if we loose the race
788 * when hlt_cpus_mask changes it is not a big deal, really.
790 * Don't do that for ULE, since ULE doesn't consider hlt_cpus_mask
791 * and unlike other schedulers it actually schedules threads to
794 if ((hlt_cpus_mask & (1 << PCPU_GET(cpuid))) != 0)
798 /* Look up our local APIC structure for the tick counters. */
799 la = &lapics[PCPU_GET(apic_id)];
800 (*la->la_timer_count)++;
805 * If the DTrace hooks are configured and a callback function
806 * has been registered, then call it to process the high speed
809 int cpu = PCPU_GET(cpuid);
810 if (cyclic_clock_func[cpu] != NULL)
811 (*cyclic_clock_func[cpu])(frame);
814 /* Fire hardclock at hz. */
815 la->la_hard_ticks += hz;
816 if (la->la_hard_ticks >= lapic_timer_hz) {
817 la->la_hard_ticks -= lapic_timer_hz;
818 if (PCPU_GET(cpuid) == 0)
819 hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame));
821 hardclock_cpu(TRAPF_USERMODE(frame));
823 if (clockcoverage == LAPIC_CLOCK_ALL) {
825 /* Fire statclock at stathz. */
826 la->la_stat_ticks += stathz;
827 if (la->la_stat_ticks >= lapic_timer_hz) {
828 la->la_stat_ticks -= lapic_timer_hz;
829 statclock(TRAPF_USERMODE(frame));
832 /* Fire profclock at profhz, but only when needed. */
833 la->la_prof_ticks += profhz;
834 if (la->la_prof_ticks >= lapic_timer_hz) {
835 la->la_prof_ticks -= lapic_timer_hz;
837 profclock(TRAPF_USERMODE(frame),
845 lapic_timer_set_divisor(u_int divisor)
848 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor));
849 KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) /
850 sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor));
851 lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1];
855 lapic_timer_oneshot(u_int count)
859 value = lapic->lvt_timer;
860 value &= ~APIC_LVTT_TM;
861 value |= APIC_LVTT_TM_ONE_SHOT;
862 lapic->lvt_timer = value;
863 lapic->icr_timer = count;
867 lapic_timer_periodic(u_int count)
871 value = lapic->lvt_timer;
872 value &= ~APIC_LVTT_TM;
873 value |= APIC_LVTT_TM_PERIODIC;
874 lapic->lvt_timer = value;
875 lapic->icr_timer = count;
879 lapic_timer_enable_intr(void)
883 value = lapic->lvt_timer;
884 value &= ~APIC_LVT_M;
885 lapic->lvt_timer = value;
889 lapic_handle_cmc(void)
897 * Called from the mca_init() to activate the CMC interrupt if this CPU is
898 * responsible for monitoring any MC banks for CMC events. Since mca_init()
899 * is called prior to lapic_setup() during boot, this just needs to unmask
900 * this CPU's LVT_CMCI entry.
903 lapic_enable_cmc(void)
907 apic_id = PCPU_GET(apic_id);
908 KASSERT(lapics[apic_id].la_present,
909 ("%s: missing APIC %u", __func__, apic_id));
910 lapics[apic_id].la_lvts[LVT_CMCI].lvt_masked = 0;
911 lapics[apic_id].la_lvts[LVT_CMCI].lvt_active = 1;
913 printf("lapic%u: CMCI unmasked\n", apic_id);
917 lapic_handle_error(void)
922 * Read the contents of the error status register. Write to
923 * the register first before reading from it to force the APIC
924 * to update its value to indicate any errors that have
925 * occurred since the previous write to the register.
930 printf("CPU%d: local APIC error 0x%x\n", PCPU_GET(cpuid), esr);
935 apic_cpuid(u_int apic_id)
938 return apic_cpuids[apic_id];
944 /* Request a free IDT vector to be used by the specified IRQ. */
946 apic_alloc_vector(u_int apic_id, u_int irq)
950 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
953 * Search for a free vector. Currently we just use a very simple
954 * algorithm to find the first free vector.
956 mtx_lock_spin(&icu_lock);
957 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
958 if (lapics[apic_id].la_ioint_irqs[vector] != -1)
960 lapics[apic_id].la_ioint_irqs[vector] = irq;
961 mtx_unlock_spin(&icu_lock);
962 return (vector + APIC_IO_INTS);
964 mtx_unlock_spin(&icu_lock);
969 * Request 'count' free contiguous IDT vectors to be used by 'count'
970 * IRQs. 'count' must be a power of two and the vectors will be
971 * aligned on a boundary of 'align'. If the request cannot be
972 * satisfied, 0 is returned.
975 apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count, u_int align)
977 u_int first, run, vector;
979 KASSERT(powerof2(count), ("bad count"));
980 KASSERT(powerof2(align), ("bad align"));
981 KASSERT(align >= count, ("align < count"));
983 for (run = 0; run < count; run++)
984 KASSERT(irqs[run] < NUM_IO_INTS, ("Invalid IRQ %u at index %u",
989 * Search for 'count' free vectors. As with apic_alloc_vector(),
990 * this just uses a simple first fit algorithm.
994 mtx_lock_spin(&icu_lock);
995 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
997 /* Vector is in use, end run. */
998 if (lapics[apic_id].la_ioint_irqs[vector] != -1) {
1004 /* Start a new run if run == 0 and vector is aligned. */
1006 if ((vector & (align - 1)) != 0)
1012 /* Keep looping if the run isn't long enough yet. */
1016 /* Found a run, assign IRQs and return the first vector. */
1017 for (vector = 0; vector < count; vector++)
1018 lapics[apic_id].la_ioint_irqs[first + vector] =
1020 mtx_unlock_spin(&icu_lock);
1021 return (first + APIC_IO_INTS);
1023 mtx_unlock_spin(&icu_lock);
1024 printf("APIC: Couldn't find APIC vectors for %u IRQs\n", count);
1029 * Enable a vector for a particular apic_id. Since all lapics share idt
1030 * entries and ioint_handlers this enables the vector on all lapics. lapics
1031 * which do not have the vector configured would report spurious interrupts
1035 apic_enable_vector(u_int apic_id, u_int vector)
1038 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
1039 KASSERT(ioint_handlers[vector / 32] != NULL,
1040 ("No ISR handler for vector %u", vector));
1041 #ifdef KDTRACE_HOOKS
1042 KASSERT(vector != IDT_DTRACE_RET,
1043 ("Attempt to overwrite DTrace entry"));
1045 setidt(vector, ioint_handlers[vector / 32], SDT_APIC, SEL_KPL,
1050 apic_disable_vector(u_int apic_id, u_int vector)
1053 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
1054 #ifdef KDTRACE_HOOKS
1055 KASSERT(vector != IDT_DTRACE_RET,
1056 ("Attempt to overwrite DTrace entry"));
1058 KASSERT(ioint_handlers[vector / 32] != NULL,
1059 ("No ISR handler for vector %u", vector));
1062 * We can not currently clear the idt entry because other cpus
1063 * may have a valid vector at this offset.
1065 setidt(vector, &IDTVEC(rsvd), SDT_APICT, SEL_KPL, GSEL_APIC);
1069 /* Release an APIC vector when it's no longer in use. */
1071 apic_free_vector(u_int apic_id, u_int vector, u_int irq)
1075 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
1076 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
1077 ("Vector %u does not map to an IRQ line", vector));
1078 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
1079 KASSERT(lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS] ==
1080 irq, ("IRQ mismatch"));
1081 #ifdef KDTRACE_HOOKS
1082 KASSERT(vector != IDT_DTRACE_RET,
1083 ("Attempt to overwrite DTrace entry"));
1087 * Bind us to the cpu that owned the vector before freeing it so
1088 * we don't lose an interrupt delivery race.
1093 if (sched_is_bound(td))
1094 panic("apic_free_vector: Thread already bound.\n");
1095 sched_bind(td, apic_cpuid(apic_id));
1098 mtx_lock_spin(&icu_lock);
1099 lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS] = -1;
1100 mtx_unlock_spin(&icu_lock);
1108 /* Map an IDT vector (APIC) to an IRQ (interrupt source). */
1110 apic_idt_to_irq(u_int apic_id, u_int vector)
1114 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
1115 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
1116 ("Vector %u does not map to an IRQ line", vector));
1117 #ifdef KDTRACE_HOOKS
1118 KASSERT(vector != IDT_DTRACE_RET,
1119 ("Attempt to overwrite DTrace entry"));
1121 irq = lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS];
1129 * Dump data about APIC IDT vector mappings.
1131 DB_SHOW_COMMAND(apic, db_show_apic)
1133 struct intsrc *isrc;
1138 if (strcmp(modif, "vv") == 0)
1140 else if (strcmp(modif, "v") == 0)
1144 for (apic_id = 0; apic_id <= MAX_APIC_ID; apic_id++) {
1145 if (lapics[apic_id].la_present == 0)
1147 db_printf("Interrupts bound to lapic %u\n", apic_id);
1148 for (i = 0; i < APIC_NUM_IOINTS + 1 && !db_pager_quit; i++) {
1149 irq = lapics[apic_id].la_ioint_irqs[i];
1150 if (irq == -1 || irq == IRQ_SYSCALL)
1152 #ifdef KDTRACE_HOOKS
1153 if (irq == IRQ_DTRACE_RET)
1156 db_printf("vec 0x%2x -> ", i + APIC_IO_INTS);
1157 if (irq == IRQ_TIMER)
1158 db_printf("lapic timer\n");
1159 else if (irq < NUM_IO_INTS) {
1160 isrc = intr_lookup_source(irq);
1161 if (isrc == NULL || verbose == 0)
1162 db_printf("IRQ %u\n", irq);
1164 db_dump_intr_event(isrc->is_event,
1167 db_printf("IRQ %u ???\n", irq);
1173 dump_mask(const char *prefix, uint32_t v, int base)
1178 for (i = 0; i < 32; i++)
1181 db_printf("%s:", prefix);
1184 db_printf(" %02x", base + i);
1190 /* Show info from the lapic regs for this CPU. */
1191 DB_SHOW_COMMAND(lapic, db_show_lapic)
1195 db_printf("lapic ID = %d\n", lapic_id());
1197 db_printf("version = %d.%d\n", (v & APIC_VER_VERSION) >> 4,
1199 db_printf("max LVT = %d\n", (v & APIC_VER_MAXLVT) >> MAXLVTSHIFT);
1201 db_printf("SVR = %02x (%s)\n", v & APIC_SVR_VECTOR,
1202 v & APIC_SVR_ENABLE ? "enabled" : "disabled");
1203 db_printf("TPR = %02x\n", lapic->tpr);
1205 #define dump_field(prefix, index) \
1206 dump_mask(__XSTRING(prefix ## index), lapic->prefix ## index, \
1209 db_printf("In-service Interrupts:\n");
1219 db_printf("TMR Interrupts:\n");
1229 db_printf("IRR Interrupts:\n");
1244 * APIC probing support code. This includes code to manage enumerators.
1247 static SLIST_HEAD(, apic_enumerator) enumerators =
1248 SLIST_HEAD_INITIALIZER(enumerators);
1249 static struct apic_enumerator *best_enum;
1252 apic_register_enumerator(struct apic_enumerator *enumerator)
1255 struct apic_enumerator *apic_enum;
1257 SLIST_FOREACH(apic_enum, &enumerators, apic_next) {
1258 if (apic_enum == enumerator)
1259 panic("%s: Duplicate register of %s", __func__,
1260 enumerator->apic_name);
1263 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next);
1267 * We have to look for CPU's very, very early because certain subsystems
1268 * want to know how many CPU's we have extremely early on in the boot
1272 apic_init(void *dummy __unused)
1274 struct apic_enumerator *enumerator;
1280 /* We only support built in local APICs. */
1281 if (!(cpu_feature & CPUID_APIC))
1284 /* Don't probe if APIC mode is disabled. */
1285 if (resource_disabled("apic", 0))
1288 /* First, probe all the enumerators to find the best match. */
1291 SLIST_FOREACH(enumerator, &enumerators, apic_next) {
1292 retval = enumerator->apic_probe();
1295 if (best_enum == NULL || best < retval) {
1296 best_enum = enumerator;
1300 if (best_enum == NULL) {
1302 printf("APIC: Could not find any APICs.\n");
1307 printf("APIC: Using the %s enumerator.\n",
1308 best_enum->apic_name);
1312 * To work around an errata, we disable the local APIC on some
1313 * CPUs during early startup. We need to turn the local APIC back
1314 * on on such CPUs now.
1316 if (cpu == CPU_686 && cpu_vendor_id == CPU_VENDOR_INTEL &&
1317 (cpu_id & 0xff0) == 0x610) {
1318 apic_base = rdmsr(MSR_APICBASE);
1319 apic_base |= APICBASE_ENABLED;
1320 wrmsr(MSR_APICBASE, apic_base);
1324 /* Second, probe the CPU's in the system. */
1325 retval = best_enum->apic_probe_cpus();
1327 printf("%s: Failed to probe CPUs: returned %d\n",
1328 best_enum->apic_name, retval);
1332 SYSINIT(apic_init, SI_SUB_TUNABLES - 1, SI_ORDER_SECOND, apic_init, NULL);
1335 * Setup the local APIC. We have to do this prior to starting up the APs
1339 apic_setup_local(void *dummy __unused)
1343 if (best_enum == NULL)
1346 /* Third, initialize the local APIC. */
1347 retval = best_enum->apic_setup_local();
1349 printf("%s: Failed to setup the local APIC: returned %d\n",
1350 best_enum->apic_name, retval);
1353 SYSINIT(apic_setup_local, SI_SUB_CPU, SI_ORDER_SECOND, apic_setup_local,
1356 SYSINIT(apic_init, SI_SUB_CPU, SI_ORDER_SECOND, apic_init, NULL);
1360 * Setup the I/O APICs.
1363 apic_setup_io(void *dummy __unused)
1367 if (best_enum == NULL)
1369 retval = best_enum->apic_setup_io();
1371 printf("%s: Failed to setup I/O APICs: returned %d\n",
1372 best_enum->apic_name, retval);
1378 * Finish setting up the local APIC on the BSP once we know how to
1379 * properly program the LINT pins.
1382 intr_register_pic(&lapic_pic);
1386 /* Enable the MSI "pic". */
1389 SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL);
1393 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are
1394 * private to the MD code. The public interface for the rest of the
1395 * kernel is defined in mp_machdep.c.
1398 lapic_ipi_wait(int delay)
1403 * Wait delay loops for IPI to be sent. This is highly bogus
1404 * since this is sensitive to CPU clock speed. If delay is
1405 * -1, we wait forever.
1412 for (x = 0; x < delay; x += incr) {
1413 if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE)
1421 lapic_ipi_raw(register_t icrlo, u_int dest)
1423 register_t value, saveintr;
1425 /* XXX: Need more sanity checking of icrlo? */
1426 KASSERT(lapic != NULL, ("%s called too early", __func__));
1427 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
1428 ("%s: invalid dest field", __func__));
1429 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0,
1430 ("%s: reserved bits set in ICR LO register", __func__));
1432 /* Set destination in ICR HI register if it is being used. */
1433 saveintr = intr_disable();
1434 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) {
1435 value = lapic->icr_hi;
1436 value &= ~APIC_ID_MASK;
1437 value |= dest << APIC_ID_SHIFT;
1438 lapic->icr_hi = value;
1441 /* Program the contents of the IPI and dispatch it. */
1442 value = lapic->icr_lo;
1443 value &= APIC_ICRLO_RESV_MASK;
1445 lapic->icr_lo = value;
1446 intr_restore(saveintr);
1449 #define BEFORE_SPIN 1000000
1450 #ifdef DETECT_DEADLOCK
1451 #define AFTER_SPIN 1000
1455 lapic_ipi_vectored(u_int vector, int dest)
1457 register_t icrlo, destfield;
1459 KASSERT((vector & ~APIC_VECTOR_MASK) == 0,
1460 ("%s: invalid vector %d", __func__, vector));
1462 icrlo = APIC_DESTMODE_PHY | APIC_TRIGMOD_EDGE;
1465 * IPI_STOP_HARD is just a "fake" vector used to send a NMI.
1466 * Use special rules regard NMI if passed, otherwise specify
1469 if (vector == IPI_STOP_HARD)
1470 icrlo |= APIC_DELMODE_NMI | APIC_LEVEL_ASSERT;
1472 icrlo |= vector | APIC_DELMODE_FIXED | APIC_LEVEL_DEASSERT;
1475 case APIC_IPI_DEST_SELF:
1476 icrlo |= APIC_DEST_SELF;
1478 case APIC_IPI_DEST_ALL:
1479 icrlo |= APIC_DEST_ALLISELF;
1481 case APIC_IPI_DEST_OTHERS:
1482 icrlo |= APIC_DEST_ALLESELF;
1485 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
1486 ("%s: invalid destination 0x%x", __func__, dest));
1490 /* Wait for an earlier IPI to finish. */
1491 if (!lapic_ipi_wait(BEFORE_SPIN)) {
1492 if (panicstr != NULL)
1495 panic("APIC: Previous IPI is stuck");
1498 lapic_ipi_raw(icrlo, destfield);
1500 #ifdef DETECT_DEADLOCK
1501 /* Wait for IPI to be delivered. */
1502 if (!lapic_ipi_wait(AFTER_SPIN)) {
1503 #ifdef needsattention
1507 * The above function waits for the message to actually be
1508 * delivered. It breaks out after an arbitrary timeout
1509 * since the message should eventually be delivered (at
1510 * least in theory) and that if it wasn't we would catch
1511 * the failure with the check above when the next IPI is
1514 * We could skip this wait entirely, EXCEPT it probably
1515 * protects us from other routines that assume that the
1516 * message was delivered and acted upon when this function
1519 printf("APIC: IPI might be stuck\n");
1520 #else /* !needsattention */
1521 /* Wait until mesage is sent without a timeout. */
1522 while (lapic->icr_lo & APIC_DELSTAT_PEND)
1524 #endif /* needsattention */
1526 #endif /* DETECT_DEADLOCK */