2 * Copyright (c) 2009 Advanced Computing Technologies LLC
3 * Written by: John H. Baldwin <jhb@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Support for x86 machine check architecture.
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
41 #include <sys/param.h>
43 #include <sys/interrupt.h>
44 #include <sys/kernel.h>
46 #include <sys/malloc.h>
47 #include <sys/mutex.h>
49 #include <sys/sched.h>
51 #include <sys/sysctl.h>
52 #include <sys/systm.h>
53 #include <sys/taskqueue.h>
54 #include <machine/intr_machdep.h>
55 #include <machine/apicvar.h>
56 #include <machine/cputypes.h>
58 #include <machine/md_var.h>
59 #include <machine/specialreg.h>
61 /* Modes for mca_scan() */
70 * State maintained for each monitored MCx bank to control the
71 * corrected machine check interrupt threshold.
80 struct mca_record rec;
82 STAILQ_ENTRY(mca_internal) link;
85 static MALLOC_DEFINE(M_MCA, "MCA", "Machine Check Architecture");
87 static int mca_count; /* Number of records stored. */
88 static int mca_banks; /* Number of per-CPU register banks. */
90 static SYSCTL_NODE(_hw, OID_AUTO, mca, CTLFLAG_RD, NULL,
91 "Machine Check Architecture");
93 static int mca_enabled = 1;
94 TUNABLE_INT("hw.mca.enabled", &mca_enabled);
95 SYSCTL_INT(_hw_mca, OID_AUTO, enabled, CTLFLAG_RDTUN, &mca_enabled, 0,
96 "Administrative toggle for machine check support");
98 static int amd10h_L1TP = 1;
99 TUNABLE_INT("hw.mca.amd10h_L1TP", &amd10h_L1TP);
100 SYSCTL_INT(_hw_mca, OID_AUTO, amd10h_L1TP, CTLFLAG_RDTUN, &amd10h_L1TP, 0,
101 "Administrative toggle for logging of level one TLB parity (L1TP) errors");
103 int workaround_erratum383;
104 SYSCTL_INT(_hw_mca, OID_AUTO, erratum383, CTLFLAG_RD, &workaround_erratum383, 0,
105 "Is the workaround for Erratum 383 on AMD Family 10h processors enabled?");
107 static STAILQ_HEAD(, mca_internal) mca_freelist;
108 static int mca_freecount;
109 static STAILQ_HEAD(, mca_internal) mca_records;
110 static struct callout mca_timer;
111 static int mca_ticks = 3600; /* Check hourly by default. */
112 static struct taskqueue *mca_tq;
113 static struct task mca_refill_task, mca_scan_task;
114 static struct mtx mca_lock;
117 static struct cmc_state **cmc_state; /* Indexed by cpuid, bank */
118 static int cmc_throttle = 60; /* Time in seconds to throttle CMCI. */
122 sysctl_positive_int(SYSCTL_HANDLER_ARGS)
126 value = *(int *)arg1;
127 error = sysctl_handle_int(oidp, &value, 0, req);
128 if (error || req->newptr == NULL)
132 *(int *)arg1 = value;
137 sysctl_mca_records(SYSCTL_HANDLER_ARGS)
139 int *name = (int *)arg1;
140 u_int namelen = arg2;
141 struct mca_record record;
142 struct mca_internal *rec;
148 if (name[0] < 0 || name[0] >= mca_count)
151 mtx_lock_spin(&mca_lock);
152 if (name[0] >= mca_count) {
153 mtx_unlock_spin(&mca_lock);
157 STAILQ_FOREACH(rec, &mca_records, link) {
164 mtx_unlock_spin(&mca_lock);
165 return (SYSCTL_OUT(req, &record, sizeof(record)));
169 mca_error_ttype(uint16_t mca_error)
172 switch ((mca_error & 0x000c) >> 2) {
184 mca_error_level(uint16_t mca_error)
187 switch (mca_error & 0x0003) {
201 mca_error_request(uint16_t mca_error)
204 switch ((mca_error & 0x00f0) >> 4) {
228 mca_error_mmtype(uint16_t mca_error)
231 switch ((mca_error & 0x70) >> 4) {
246 /* Dump details about a single machine check. */
247 static void __nonnull(1)
248 mca_log(const struct mca_record *rec)
252 printf("MCA: Bank %d, Status 0x%016llx\n", rec->mr_bank,
253 (long long)rec->mr_status);
254 printf("MCA: Global Cap 0x%016llx, Status 0x%016llx\n",
255 (long long)rec->mr_mcg_cap, (long long)rec->mr_mcg_status);
256 printf("MCA: Vendor \"%s\", ID 0x%x, APIC ID %d\n", cpu_vendor,
257 rec->mr_cpu_id, rec->mr_apic_id);
258 printf("MCA: CPU %d ", rec->mr_cpu);
259 if (rec->mr_status & MC_STATUS_UC)
263 if (rec->mr_mcg_cap & MCG_CAP_CMCI_P)
264 printf("(%lld) ", ((long long)rec->mr_status &
265 MC_STATUS_COR_COUNT) >> 38);
267 if (rec->mr_status & MC_STATUS_PCC)
269 if (rec->mr_status & MC_STATUS_OVER)
271 mca_error = rec->mr_status & MC_STATUS_MCA_ERROR;
273 /* Simple error codes. */
278 printf("unclassified error");
281 printf("ucode ROM parity error");
284 printf("external error");
290 printf("internal parity error");
293 printf("internal timer error");
296 if ((mca_error & 0xfc00) == 0x0400) {
297 printf("internal error %x", mca_error & 0x03ff);
301 /* Compound error codes. */
303 /* Memory hierarchy error. */
304 if ((mca_error & 0xeffc) == 0x000c) {
305 printf("%s memory error", mca_error_level(mca_error));
310 if ((mca_error & 0xeff0) == 0x0010) {
311 printf("%sTLB %s error", mca_error_ttype(mca_error),
312 mca_error_level(mca_error));
316 /* Memory controller error. */
317 if ((mca_error & 0xef80) == 0x0080) {
318 printf("%s channel ", mca_error_mmtype(mca_error));
319 if ((mca_error & 0x000f) != 0x000f)
320 printf("%d", mca_error & 0x000f);
323 printf(" memory error");
328 if ((mca_error & 0xef00) == 0x0100) {
329 printf("%sCACHE %s %s error",
330 mca_error_ttype(mca_error),
331 mca_error_level(mca_error),
332 mca_error_request(mca_error));
336 /* Bus and/or Interconnect error. */
337 if ((mca_error & 0xe800) == 0x0800) {
338 printf("BUS%s ", mca_error_level(mca_error));
339 switch ((mca_error & 0x0600) >> 9) {
353 printf(" %s ", mca_error_request(mca_error));
354 switch ((mca_error & 0x000c) >> 2) {
368 if (mca_error & 0x0100)
369 printf(" timed out");
373 printf("unknown error %x", mca_error);
377 if (rec->mr_status & MC_STATUS_ADDRV)
378 printf("MCA: Address 0x%llx\n", (long long)rec->mr_addr);
379 if (rec->mr_status & MC_STATUS_MISCV)
380 printf("MCA: Misc 0x%llx\n", (long long)rec->mr_misc);
383 static int __nonnull(2)
384 mca_check_status(int bank, struct mca_record *rec)
389 status = rdmsr(MSR_MC_STATUS(bank));
390 if (!(status & MC_STATUS_VAL))
393 /* Save exception information. */
394 rec->mr_status = status;
397 if (status & MC_STATUS_ADDRV)
398 rec->mr_addr = rdmsr(MSR_MC_ADDR(bank));
400 if (status & MC_STATUS_MISCV)
401 rec->mr_misc = rdmsr(MSR_MC_MISC(bank));
402 rec->mr_tsc = rdtsc();
403 rec->mr_apic_id = PCPU_GET(apic_id);
404 rec->mr_mcg_cap = rdmsr(MSR_MCG_CAP);
405 rec->mr_mcg_status = rdmsr(MSR_MCG_STATUS);
406 rec->mr_cpu_id = cpu_id;
407 rec->mr_cpu_vendor_id = cpu_vendor_id;
408 rec->mr_cpu = PCPU_GET(cpuid);
411 * Clear machine check. Don't do this for uncorrectable
412 * errors so that the BIOS can see them.
414 if (!(rec->mr_status & (MC_STATUS_PCC | MC_STATUS_UC))) {
415 wrmsr(MSR_MC_STATUS(bank), 0);
422 mca_fill_freelist(void)
424 struct mca_internal *rec;
428 * Ensure we have at least one record for each bank and one
431 desired = imax(mp_ncpus, mca_banks);
432 mtx_lock_spin(&mca_lock);
433 while (mca_freecount < desired) {
434 mtx_unlock_spin(&mca_lock);
435 rec = malloc(sizeof(*rec), M_MCA, M_WAITOK);
436 mtx_lock_spin(&mca_lock);
437 STAILQ_INSERT_TAIL(&mca_freelist, rec, link);
440 mtx_unlock_spin(&mca_lock);
444 mca_refill(void *context, int pending)
450 static void __nonnull(2)
451 mca_record_entry(enum scan_mode mode, const struct mca_record *record)
453 struct mca_internal *rec;
455 if (mode == POLLED) {
456 rec = malloc(sizeof(*rec), M_MCA, M_WAITOK);
457 mtx_lock_spin(&mca_lock);
459 mtx_lock_spin(&mca_lock);
460 rec = STAILQ_FIRST(&mca_freelist);
462 printf("MCA: Unable to allocate space for an event.\n");
464 mtx_unlock_spin(&mca_lock);
467 STAILQ_REMOVE_HEAD(&mca_freelist, link);
473 STAILQ_INSERT_TAIL(&mca_records, rec, link);
475 mtx_unlock_spin(&mca_lock);
477 taskqueue_enqueue_fast(mca_tq, &mca_refill_task);
482 * Update the interrupt threshold for a CMCI. The strategy is to use
483 * a low trigger that interrupts as soon as the first event occurs.
484 * However, if a steady stream of events arrive, the threshold is
485 * increased until the interrupts are throttled to once every
486 * cmc_throttle seconds or the periodic scan. If a periodic scan
487 * finds that the threshold is too high, it is lowered.
490 cmci_update(enum scan_mode mode, int bank, int valid, struct mca_record *rec)
492 struct cmc_state *cc;
497 /* Fetch the current limit for this bank. */
498 cc = &cmc_state[PCPU_GET(cpuid)][bank];
499 ctl = rdmsr(MSR_MC_CTL2(bank));
500 count = (rec->mr_status & MC_STATUS_COR_COUNT) >> 38;
501 delta = (u_int)(ticks - cc->last_intr);
504 * If an interrupt was received less than cmc_throttle seconds
505 * since the previous interrupt and the count from the current
506 * event is greater than or equal to the current threshold,
507 * double the threshold up to the max.
509 if (mode == CMCI && valid) {
510 limit = ctl & MC_CTL2_THRESHOLD;
511 if (delta < cmc_throttle && count >= limit &&
512 limit < cc->max_threshold) {
513 limit = min(limit << 1, cc->max_threshold);
514 ctl &= ~MC_CTL2_THRESHOLD;
516 wrmsr(MSR_MC_CTL2(bank), limit);
518 cc->last_intr = ticks;
523 * When the banks are polled, check to see if the threshold
529 /* If a CMCI occured recently, do nothing for now. */
530 if (delta < cmc_throttle)
534 * Compute a new limit based on the average rate of events per
535 * cmc_throttle seconds since the last interrupt.
538 count = (rec->mr_status & MC_STATUS_COR_COUNT) >> 38;
539 limit = count * cmc_throttle / delta;
542 else if (limit > cc->max_threshold)
543 limit = cc->max_threshold;
546 if ((ctl & MC_CTL2_THRESHOLD) != limit) {
547 ctl &= ~MC_CTL2_THRESHOLD;
549 wrmsr(MSR_MC_CTL2(bank), limit);
555 * This scans all the machine check banks of the current CPU to see if
556 * there are any machine checks. Any non-recoverable errors are
557 * reported immediately via mca_log(). The current thread must be
558 * pinned when this is called. The 'mode' parameter indicates if we
559 * are being called from the MC exception handler, the CMCI handler,
560 * or the periodic poller. In the MC exception case this function
561 * returns true if the system is restartable. Otherwise, it returns a
562 * count of the number of valid MC records found.
565 mca_scan(enum scan_mode mode)
567 struct mca_record rec;
568 uint64_t mcg_cap, ucmask;
569 int count, i, recoverable, valid;
573 ucmask = MC_STATUS_UC | MC_STATUS_PCC;
575 /* When handling a MCE#, treat the OVER flag as non-restartable. */
577 ucmask |= MC_STATUS_OVER;
578 mcg_cap = rdmsr(MSR_MCG_CAP);
579 for (i = 0; i < (mcg_cap & MCG_CAP_COUNT); i++) {
582 * For a CMCI, only check banks this CPU is
585 if (mode == CMCI && !(PCPU_GET(cmci_mask) & 1 << i))
589 valid = mca_check_status(i, &rec);
592 if (rec.mr_status & ucmask) {
594 mtx_lock_spin(&mca_lock);
596 mtx_unlock_spin(&mca_lock);
598 mca_record_entry(mode, &rec);
603 * If this is a bank this CPU monitors via CMCI,
604 * update the threshold.
606 if (PCPU_GET(cmci_mask) & 1 << i)
607 cmci_update(mode, i, valid, &rec);
612 return (mode == MCE ? recoverable : count);
616 * Scan the machine check banks on all CPUs by binding to each CPU in
617 * turn. If any of the CPUs contained new machine check records, log
618 * them to the console.
621 mca_scan_cpus(void *context, int pending)
623 struct mca_internal *mca;
634 count += mca_scan(POLLED);
640 mtx_lock_spin(&mca_lock);
641 STAILQ_FOREACH(mca, &mca_records, link) {
647 mtx_unlock_spin(&mca_lock);
652 mca_periodic_scan(void *arg)
655 taskqueue_enqueue_fast(mca_tq, &mca_scan_task);
656 callout_reset(&mca_timer, mca_ticks * hz, mca_periodic_scan, NULL);
660 sysctl_mca_scan(SYSCTL_HANDLER_ARGS)
665 error = sysctl_handle_int(oidp, &i, 0, req);
669 taskqueue_enqueue_fast(mca_tq, &mca_scan_task);
674 mca_createtq(void *dummy)
679 mca_tq = taskqueue_create_fast("mca", M_WAITOK,
680 taskqueue_thread_enqueue, &mca_tq);
681 taskqueue_start_threads(&mca_tq, 1, PI_SWI(SWI_TQ), "mca taskq");
683 SYSINIT(mca_createtq, SI_SUB_CONFIGURE, SI_ORDER_ANY, mca_createtq, NULL);
686 mca_startup(void *dummy)
692 callout_reset(&mca_timer, mca_ticks * hz, mca_periodic_scan, NULL);
694 SYSINIT(mca_startup, SI_SUB_SMP, SI_ORDER_ANY, mca_startup, NULL);
702 cmc_state = malloc((mp_maxid + 1) * sizeof(struct cmc_state **),
704 for (i = 0; i <= mp_maxid; i++)
705 cmc_state[i] = malloc(sizeof(struct cmc_state) * mca_banks,
706 M_MCA, M_WAITOK | M_ZERO);
707 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
708 "cmc_throttle", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE,
709 &cmc_throttle, 0, sysctl_positive_int, "I",
710 "Interval in seconds to throttle corrected MC interrupts");
715 mca_setup(uint64_t mcg_cap)
719 * On AMD Family 10h processors, unless logging of level one TLB
720 * parity (L1TP) errors is disabled, enable the recommended workaround
723 if (cpu_vendor_id == CPU_VENDOR_AMD &&
724 CPUID_TO_FAMILY(cpu_id) == 0x10 && amd10h_L1TP)
725 workaround_erratum383 = 1;
727 mca_banks = mcg_cap & MCG_CAP_COUNT;
728 mtx_init(&mca_lock, "mca", NULL, MTX_SPIN);
729 STAILQ_INIT(&mca_records);
730 TASK_INIT(&mca_scan_task, 0, mca_scan_cpus, NULL);
731 callout_init(&mca_timer, CALLOUT_MPSAFE);
732 STAILQ_INIT(&mca_freelist);
733 TASK_INIT(&mca_refill_task, 0, mca_refill, NULL);
735 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
736 "count", CTLFLAG_RD, &mca_count, 0, "Record count");
737 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
738 "interval", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, &mca_ticks,
739 0, sysctl_positive_int, "I",
740 "Periodic interval in seconds to scan for machine checks");
741 SYSCTL_ADD_NODE(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
742 "records", CTLFLAG_RD, sysctl_mca_records, "Machine check records");
743 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
744 "force_scan", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, NULL, 0,
745 sysctl_mca_scan, "I", "Force an immediate scan for machine checks");
747 if (mcg_cap & MCG_CAP_CMCI_P)
754 * See if we should monitor CMCI for this bank. If CMCI_EN is already
755 * set in MC_CTL2, then another CPU is responsible for this bank, so
756 * ignore it. If CMCI_EN returns zero after being set, then this bank
757 * does not support CMCI_EN. If this CPU sets CMCI_EN, then it should
758 * now monitor this bank.
763 struct cmc_state *cc;
766 KASSERT(i < mca_banks, ("CPU %d has more MC banks", PCPU_GET(cpuid)));
768 ctl = rdmsr(MSR_MC_CTL2(i));
769 if (ctl & MC_CTL2_CMCI_EN)
770 /* Already monitored by another CPU. */
773 /* Set the threshold to one event for now. */
774 ctl &= ~MC_CTL2_THRESHOLD;
775 ctl |= MC_CTL2_CMCI_EN | 1;
776 wrmsr(MSR_MC_CTL2(i), ctl);
777 ctl = rdmsr(MSR_MC_CTL2(i));
778 if (!(ctl & MC_CTL2_CMCI_EN))
779 /* This bank does not support CMCI. */
782 cc = &cmc_state[PCPU_GET(cpuid)][i];
784 /* Determine maximum threshold. */
785 ctl &= ~MC_CTL2_THRESHOLD;
787 wrmsr(MSR_MC_CTL2(i), ctl);
788 ctl = rdmsr(MSR_MC_CTL2(i));
789 cc->max_threshold = ctl & MC_CTL2_THRESHOLD;
791 /* Start off with a threshold of 1. */
792 ctl &= ~MC_CTL2_THRESHOLD;
794 wrmsr(MSR_MC_CTL2(i), ctl);
796 /* Mark this bank as monitored. */
797 PCPU_SET(cmci_mask, PCPU_GET(cmci_mask) | 1 << i);
801 * For resume, reset the threshold for any banks we monitor back to
802 * one and throw away the timestamp of the last interrupt.
807 struct cmc_state *cc;
810 KASSERT(i < mca_banks, ("CPU %d has more MC banks", PCPU_GET(cpuid)));
812 /* Ignore banks not monitored by this CPU. */
813 if (!(PCPU_GET(cmci_mask) & 1 << i))
816 cc = &cmc_state[PCPU_GET(cpuid)][i];
817 cc->last_intr = -ticks;
818 ctl = rdmsr(MSR_MC_CTL2(i));
819 ctl &= ~MC_CTL2_THRESHOLD;
820 ctl |= MC_CTL2_CMCI_EN | 1;
821 wrmsr(MSR_MC_CTL2(i), ctl);
826 * Initializes per-CPU machine check registers and enables corrected
827 * machine check interrupts.
836 /* MCE is required. */
837 if (!mca_enabled || !(cpu_feature & CPUID_MCE))
840 if (cpu_feature & CPUID_MCA) {
842 PCPU_SET(cmci_mask, 0);
844 mcg_cap = rdmsr(MSR_MCG_CAP);
845 if (mcg_cap & MCG_CAP_CTL_P)
846 /* Enable MCA features. */
847 wrmsr(MSR_MCG_CTL, MCG_CTL_ENABLE);
848 if (PCPU_GET(cpuid) == 0 && boot)
852 * Disable logging of level one TLB parity (L1TP) errors by
853 * the data cache as an alternative workaround for AMD Family
854 * 10h Erratum 383. Unlike the recommended workaround, there
855 * is no performance penalty to this workaround. However,
856 * L1TP errors will go unreported.
858 if (cpu_vendor_id == CPU_VENDOR_AMD &&
859 CPUID_TO_FAMILY(cpu_id) == 0x10 && !amd10h_L1TP) {
860 mask = rdmsr(MSR_MC0_CTL_MASK);
861 if ((mask & (1UL << 5)) == 0)
862 wrmsr(MSR_MC0_CTL_MASK, mask | (1UL << 5));
864 for (i = 0; i < (mcg_cap & MCG_CAP_COUNT); i++) {
865 /* By default enable logging of all errors. */
866 ctl = 0xffffffffffffffffUL;
869 if (cpu_vendor_id == CPU_VENDOR_INTEL) {
871 * For P6 models before Nehalem MC0_CTL is
872 * always enabled and reserved.
874 if (i == 0 && CPUID_TO_FAMILY(cpu_id) == 0x6
875 && CPUID_TO_MODEL(cpu_id) < 0x1a)
877 } else if (cpu_vendor_id == CPU_VENDOR_AMD) {
878 /* BKDG for Family 10h: unset GartTblWkEn. */
879 if (i == 4 && CPUID_TO_FAMILY(cpu_id) >= 0xf)
884 wrmsr(MSR_MC_CTL(i), ctl);
887 if (mcg_cap & MCG_CAP_CMCI_P) {
895 /* Clear all errors. */
896 wrmsr(MSR_MC_STATUS(i), 0);
900 if (PCPU_GET(cmci_mask) != 0 && boot)
905 load_cr4(rcr4() | CR4_MCE);
908 /* Must be executed on each CPU during boot. */
916 /* Must be executed on each CPU during resume. */
925 * The machine check registers for the BSP cannot be initialized until
926 * the local APIC is initialized. This happens at SI_SUB_CPU,
930 mca_init_bsp(void *arg __unused)
935 SYSINIT(mca_init_bsp, SI_SUB_CPU, SI_ORDER_ANY, mca_init_bsp, NULL);
937 /* Called when a machine check exception fires. */
944 if (!(cpu_feature & CPUID_MCA)) {
946 * Just print the values of the old Pentium registers
949 printf("MC Type: 0x%jx Address: 0x%jx\n",
950 (uintmax_t)rdmsr(MSR_P5_MC_TYPE),
951 (uintmax_t)rdmsr(MSR_P5_MC_ADDR));
952 panic("Machine check");
955 /* Scan the banks and check for any non-recoverable errors. */
956 recoverable = mca_scan(MCE);
957 mcg_status = rdmsr(MSR_MCG_STATUS);
958 if (!(mcg_status & MCG_STATUS_RIPV))
962 wrmsr(MSR_MCG_STATUS, mcg_status & ~MCG_STATUS_MCIP);
964 panic("Unrecoverable machine check exception");
968 /* Called for a CMCI (correctable machine check interrupt). */
972 struct mca_internal *mca;
976 * Serialize MCA bank scanning to prevent collisions from
979 count = mca_scan(CMCI);
981 /* If we found anything, log them to the console. */
983 mtx_lock_spin(&mca_lock);
984 STAILQ_FOREACH(mca, &mca_records, link) {
990 mtx_unlock_spin(&mca_lock);