2 * Structure definitions for HVM state that is held by Xen and must
3 * be saved along with the domain's memory and device-model state.
5 * Copyright (c) 2007 XenSource Ltd.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to
9 * deal in the Software without restriction, including without limitation the
10 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
11 * sell copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
20 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 #ifndef __XEN_PUBLIC_HVM_SAVE_X86_H__
27 #define __XEN_PUBLIC_HVM_SAVE_X86_H__
30 * Save/restore header: general info about the save file.
33 #define HVM_FILE_MAGIC 0x54381286
34 #define HVM_FILE_VERSION 0x00000001
36 struct hvm_save_header {
37 uint32_t magic; /* Must be HVM_FILE_MAGIC */
38 uint32_t version; /* File format version */
39 uint64_t changeset; /* Version of Xen that saved this file */
40 uint32_t cpuid; /* CPUID[0x01][%eax] on the saving machine */
44 DECLARE_HVM_SAVE_TYPE(HEADER, 1, struct hvm_save_header);
52 uint8_t fpu_regs[512];
124 uint32_t ldtr_arbytes;
126 uint32_t sysenter_cs;
129 uint64_t sysenter_esp;
130 uint64_t sysenter_eip;
135 /* msr content saved/restored. */
140 uint64_t msr_syscall_mask;
143 /* guest's idea of what rdtsc() would return */
146 /* pending event, if any */
148 uint32_t pending_event;
150 uint8_t pending_vector:8;
151 uint8_t pending_type:3;
152 uint8_t pending_error_valid:1;
153 uint32_t pending_reserved:19;
154 uint8_t pending_valid:1;
157 /* error code for pending event */
161 DECLARE_HVM_SAVE_TYPE(CPU, 2, struct hvm_hw_cpu);
169 /* IR line bitmasks. */
174 /* Line IRx maps to IRQ irq_base+x */
178 * Where are we in ICW2-4 initialisation (0 means no init in progress)?
179 * Bits 0-1 (=x): Next write at A=1 sets ICW(x+1).
180 * Bit 2: ICW1.IC4 (1 == ICW4 included in init sequence)
181 * Bit 3: ICW1.SNGL (0 == ICW3 included in init sequence)
183 uint8_t init_state:4;
185 /* IR line with highest priority. */
186 uint8_t priority_add:4;
188 /* Reads from A=0 obtain ISR or IRR? */
189 uint8_t readsel_isr:1;
191 /* Reads perform a polling read? */
194 /* Automatically clear IRQs from the ISR during INTA? */
197 /* Automatically rotate IRQ priorities during AEOI? */
198 uint8_t rotate_on_auto_eoi:1;
200 /* Exclude slave inputs when considering in-service IRQs? */
201 uint8_t special_fully_nested_mode:1;
203 /* Special mask mode excludes masked IRs from AEOI and priority checks. */
204 uint8_t special_mask_mode:1;
206 /* Is this a master PIC or slave PIC? (NB. This is not programmable.) */
209 /* Edge/trigger selection. */
212 /* Virtual INT output. */
216 DECLARE_HVM_SAVE_TYPE(PIC, 3, struct hvm_hw_vpic);
224 #define VIOAPIC_IS_IOSAPIC 1
225 #define VIOAPIC_NUM_PINS 24
227 #define VIOAPIC_NUM_PINS 48 /* 16 ISA IRQs, 32 non-legacy PCI IRQS. */
230 struct hvm_hw_vioapic {
231 uint64_t base_address;
234 union vioapic_redir_entry
239 uint8_t delivery_mode:3;
241 uint8_t delivery_status:1;
243 uint8_t remote_irr:1;
247 #if !VIOAPIC_IS_IOSAPIC
255 } redirtbl[VIOAPIC_NUM_PINS];
258 DECLARE_HVM_SAVE_TYPE(IOAPIC, 4, struct hvm_hw_vioapic);
265 struct hvm_hw_lapic {
266 uint64_t apic_base_msr;
267 uint32_t disabled; /* VLAPIC_xx_DISABLED */
268 uint32_t timer_divisor;
271 DECLARE_HVM_SAVE_TYPE(LAPIC, 5, struct hvm_hw_lapic);
273 struct hvm_hw_lapic_regs {
277 DECLARE_HVM_SAVE_TYPE(LAPIC_REGS, 6, struct hvm_hw_lapic_regs);
284 struct hvm_hw_pci_irqs {
286 * Virtual interrupt wires for a single PCI bus.
287 * Indexed by: device*4 + INTx#.
290 DECLARE_BITMAP(i, 32*4);
295 DECLARE_HVM_SAVE_TYPE(PCI_IRQ, 7, struct hvm_hw_pci_irqs);
297 struct hvm_hw_isa_irqs {
299 * Virtual interrupt wires for ISA devices.
300 * Indexed by ISA IRQ (assumes no ISA-device IRQ sharing).
303 DECLARE_BITMAP(i, 16);
308 DECLARE_HVM_SAVE_TYPE(ISA_IRQ, 8, struct hvm_hw_isa_irqs);
310 struct hvm_hw_pci_link {
312 * PCI-ISA interrupt router.
313 * Each PCI <device:INTx#> is 'wire-ORed' into one of four links using
314 * the traditional 'barber's pole' mapping ((device + INTx#) & 3).
315 * The router provides a programmable mapping from each link to a GSI.
321 DECLARE_HVM_SAVE_TYPE(PCI_LINK, 9, struct hvm_hw_pci_link);
328 struct hvm_hw_pit_channel {
329 uint32_t count; /* can be 65536 */
330 uint16_t latched_count;
331 uint8_t count_latched;
332 uint8_t status_latched;
339 uint8_t bcd; /* not supported */
340 uint8_t gate; /* timer start */
341 } channels[3]; /* 3 x 16 bytes */
342 uint32_t speaker_data_on;
346 DECLARE_HVM_SAVE_TYPE(PIT, 10, struct hvm_hw_pit);
353 #define RTC_CMOS_SIZE 14
356 uint8_t cmos_data[RTC_CMOS_SIZE];
357 /* Index register for 2-part operations */
362 DECLARE_HVM_SAVE_TYPE(RTC, 11, struct hvm_hw_rtc);
369 #define HPET_TIMER_NUM 3 /* 3 timers supported now */
371 /* Memory-mapped, software visible registers */
372 uint64_t capability; /* capabilities */
373 uint64_t res0; /* reserved */
374 uint64_t config; /* configuration */
375 uint64_t res1; /* reserved */
376 uint64_t isr; /* interrupt status reg */
377 uint64_t res2[25]; /* reserved */
378 uint64_t mc64; /* main counter */
379 uint64_t res3; /* reserved */
380 struct { /* timers */
381 uint64_t config; /* configuration/cap */
382 uint64_t cmp; /* comparator */
383 uint64_t fsb; /* FSB route, not supported now */
384 uint64_t res4; /* reserved */
385 } timers[HPET_TIMER_NUM];
386 uint64_t res5[4*(24-HPET_TIMER_NUM)]; /* reserved, up to 0x3ff */
388 /* Hidden register state */
389 uint64_t period[HPET_TIMER_NUM]; /* Last value written to comparator */
392 DECLARE_HVM_SAVE_TYPE(HPET, 12, struct hvm_hw_hpet);
399 struct hvm_hw_pmtimer {
400 uint32_t tmr_val; /* PM_TMR_BLK.TMR_VAL: 32bit free-running counter */
401 uint16_t pm1a_sts; /* PM1a_EVT_BLK.PM1a_STS: status register */
402 uint16_t pm1a_en; /* PM1a_EVT_BLK.PM1a_EN: enable register */
405 DECLARE_HVM_SAVE_TYPE(PMTIMER, 13, struct hvm_hw_pmtimer);
413 #define NUM_FIXED_MSR 11
415 /* mtrr physbase & physmask msr pair*/
416 uint64_t msr_mtrr_var[MTRR_VCNT*2];
417 uint64_t msr_mtrr_fixed[NUM_FIXED_MSR];
418 uint64_t msr_mtrr_cap;
419 uint64_t msr_mtrr_def_type;
422 DECLARE_HVM_SAVE_TYPE(MTRR, 14, struct hvm_hw_mtrr);
425 * Largest type-code in use
427 #define HVM_SAVE_CODE_MAX 14
429 #endif /* __XEN_PUBLIC_HVM_SAVE_X86_H__ */