2 .TH "LLC" "1" "2012-08-16" "3.2" "LLVM"
4 llc \- LLVM static compiler
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36 \fBllc\fP [\fIoptions\fP] [\fIfilename\fP]
39 The \fBllc\fP command compiles LLVM source inputs into assembly language for a
40 specified architecture. The assembly language output can then be passed through
41 a native assembler and linker to generate a native executable.
43 The choice of architecture for the output assembly code is automatically
44 determined from the input file, unless the \fB\-march\fP option is used to override
48 If \fIfilename\fP is \- or omitted, \fBllc\fP reads from standard input. Otherwise, it
49 will from \fIfilename\fP. Inputs can be in either the LLVM assembly language
50 format (.ll) or the LLVM bitcode format (.bc).
52 If the \fB\-o\fP option is omitted, then \fBllc\fP will send its output to standard
53 output if the input is from standard input. If the \fB\-o\fP option specifies \-,
54 then the output will also be sent to standard output.
56 If no \fB\-o\fP option is specified and an input file other than \- is specified,
57 then \fBllc\fP creates the output filename by taking the input filename,
58 removing any existing \fI.bc\fP extension, and adding a \fI.s\fP suffix.
60 Other \fBllc\fP options are as follows:
66 Print a summary of command line options.
73 Generate code at different optimization levels. These correspond to the \fI\-O0\fP,
74 \fI\-O1\fP, \fI\-O2\fP, and \fI\-O3\fP optimization levels used by \fBllvm\-gcc\fP and
79 \fB\-mtriple\fP=\fItarget triple\fP
82 Override the target triple specified in the input file with the specified
87 \fB\-march\fP=\fIarch\fP
90 Specify the architecture for which to generate assembly, overriding the target
91 encoded in the input file. See the output of \fBllc \-help\fP for a list of
92 valid architectures. By default this is inferred from the target triple or
93 autodetected to the current architecture.
97 \fB\-mcpu\fP=\fIcpuname\fP
100 Specify a specific chip in the current architecture to generate code for.
101 By default this is inferred from the target triple and autodetected to
102 the current architecture. For a list of available CPUs, use:
103 \fBllvm\-as < /dev/null | llc \-march=xyz \-mcpu=help\fP
107 \fB\-mattr\fP=\fIa1,+a2,\-a3,...\fP
110 Override or control specific attributes of the target, such as whether SIMD
111 operations are enabled or not. The default set of attributes is set by the
112 current CPU. For a list of available attributes, use:
113 \fBllvm\-as < /dev/null | llc \-march=xyz \-mattr=help\fP
117 \fB\-\-disable\-fp\-elim\fP
120 Disable frame pointer elimination optimization.
124 \fB\-\-disable\-excess\-fp\-precision\fP
127 Disable optimizations that may produce excess precision for floating point.
128 Note that this option can dramatically slow down code on some systems
133 \fB\-\-enable\-no\-infs\-fp\-math\fP
136 Enable optimizations that assume no Inf values.
140 \fB\-\-enable\-no\-nans\-fp\-math\fP
143 Enable optimizations that assume no NAN values.
147 \fB\-\-enable\-unsafe\-fp\-math\fP
150 Enable optimizations that make unsafe assumptions about IEEE math (e.g. that
151 addition is associative) or may not work for all input ranges. These
152 optimizations allow the code generator to make use of some instructions which
153 would otherwise not be usable (such as fsin on X86).
157 \fB\-\-enable\-correct\-eh\-support\fP
160 Instruct the \fBlowerinvoke\fP pass to insert code for correct exception handling
161 support. This is expensive and is by default omitted for efficiency.
168 Print statistics recorded by code\-generation passes.
172 \fB\-\-time\-passes\fP
175 Record the amount of time needed for each pass and print a report to standard
180 \fB\-\-load\fP=\fIdso_path\fP
183 Dynamically load \fIdso_path\fP (a path to a dynamically shared object) that
184 implements an LLVM target. This will permit the target name to be used with the
185 \fB\-march\fP option so that code can be generated for that target.
188 .SS Tuning/Configuration Options
190 \fB\-\-print\-machineinstrs\fP
193 Print generated machine code between compilation phases (useful for debugging).
197 \fB\-\-regalloc\fP=\fIallocator\fP
200 Specify the register allocator to use. The default \fIallocator\fP is \fIlocal\fP.
201 Valid register allocators are:
206 Very simple "always spill" register allocator
213 Local register allocator
220 Linear scan global register allocator
227 Iterative scan global register allocator
233 \fB\-\-spiller\fP=\fIspiller\fP
236 Specify the spiller to use for register allocators that support it. Currently
237 this option is used only by the linear scan register allocator. The default
238 \fIspiller\fP is \fIlocal\fP. Valid spillers are:
255 .SS Intel IA\-32\-specific Options
257 \fB\-\-x86\-asm\-syntax=att|intel\fP
260 Specify whether to emit assembly code in AT&T syntax (the default) or intel
266 If \fBllc\fP succeeds, it will exit with 0. Otherwise, if an error occurs,
267 it will exit with a non\-zero value.
272 Maintained by The LLVM Team (http://llvm.org/).
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