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4 .TH "LLI" "1" "2014-01-01" "3.4" "LLVM"
6 lli \- directly execute programs from LLVM bitcode
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36 \fBlli\fP [\fIoptions\fP] [\fIfilename\fP] [\fIprogram args\fP]
39 \fBlli\fP directly executes programs in LLVM bitcode format. It takes a program
40 in LLVM bitcode format and executes it using a just\-in\-time compiler, if one is
41 available for the current architecture, or an interpreter. \fBlli\fP takes all of
42 the same code generator options as llc|llc, but they are only effective when
43 \fBlli\fP is using the just\-in\-time compiler.
45 If \fIfilename\fP is not specified, then \fBlli\fP reads the LLVM bitcode for the
46 program from standard input.
48 The optional \fIargs\fP specified on the command line are passed to the program as
52 \fB\-fake\-argv0\fP=\fIexecutable\fP
55 Override the \fBargv[0]\fP value passed into the executing program.
59 \fB\-force\-interpreter\fP=\fI{false,true}\fP
62 If set to true, use the interpreter even if a just\-in\-time compiler is available
63 for this architecture. Defaults to false.
70 Print a summary of command line options.
74 \fB\-load\fP=\fIpluginfilename\fP
77 Causes \fBlli\fP to load the plugin (shared object) named \fIpluginfilename\fP and use
85 Print statistics from the code\-generation passes. This is only meaningful for
86 the just\-in\-time compiler, at present.
93 Record the amount of time needed for each code\-generation pass and print it to
101 Print out the version of \fBlli\fP and exit without doing anything else.
106 \fB\-mtriple\fP=\fItarget triple\fP
109 Override the target triple specified in the input bitcode file with the
110 specified string. This may result in a crash if you pick an
111 architecture which is not compatible with the current system.
115 \fB\-march\fP=\fIarch\fP
118 Specify the architecture for which to generate assembly, overriding the target
119 encoded in the bitcode file. See the output of \fBllc \-help\fP for a list of
120 valid architectures. By default this is inferred from the target triple or
121 autodetected to the current architecture.
125 \fB\-mcpu\fP=\fIcpuname\fP
128 Specify a specific chip in the current architecture to generate code for.
129 By default this is inferred from the target triple and autodetected to
130 the current architecture. For a list of available CPUs, use:
131 \fBllvm\-as < /dev/null | llc \-march=xyz \-mcpu=help\fP
135 \fB\-mattr\fP=\fIa1,+a2,\-a3,...\fP
138 Override or control specific attributes of the target, such as whether SIMD
139 operations are enabled or not. The default set of attributes is set by the
140 current CPU. For a list of available attributes, use:
141 \fBllvm\-as < /dev/null | llc \-march=xyz \-mattr=help\fP
144 .SH FLOATING POINT OPTIONS
146 \fB\-disable\-excess\-fp\-precision\fP
149 Disable optimizations that may increase floating point precision.
153 \fB\-enable\-no\-infs\-fp\-math\fP
156 Enable optimizations that assume no Inf values.
160 \fB\-enable\-no\-nans\-fp\-math\fP
163 Enable optimizations that assume no NAN values.
167 \fB\-enable\-unsafe\-fp\-math\fP
170 Causes \fBlli\fP to enable optimizations that may decrease floating point
178 Causes \fBlli\fP to generate software floating point library calls instead of
179 equivalent hardware instructions.
182 .SH CODE GENERATION OPTIONS
184 \fB\-code\-model\fP=\fImodel\fP
187 Choose the code model from:
193 default: Target default code model
194 small: Small code model
195 kernel: Kernel code model
196 medium: Medium code model
197 large: Large code model
205 \fB\-disable\-post\-RA\-scheduler\fP
208 Disable scheduling after register allocation.
212 \fB\-disable\-spill\-fusing\fP
215 Disable fusing of spill code into instructions.
219 \fB\-enable\-correct\-eh\-support\fP
222 Make the \-lowerinvoke pass insert expensive, but correct, EH code.
226 \fB\-jit\-enable\-eh\fP
229 Exception handling should be enabled in the just\-in\-time compiler.
233 \fB\-join\-liveintervals\fP
236 Coalesce copies (default=true).
240 \fB\-nozero\-initialized\-in\-bss\fP Don\(aqt place zero\-initialized symbols into the BSS section.
242 \fB\-pre\-RA\-sched\fP=\fIscheduler\fP
245 Instruction schedulers available (before register allocation):
251 =default: Best scheduler for the target
252 =none: No scheduling: breadth first sequencing
253 =simple: Simple two pass scheduling: minimize critical path and maximize processor utilization
254 =simple\-noitin: Simple two pass scheduling: Same as simple except using generic latency
255 =list\-burr: Bottom\-up register reduction list scheduling
256 =list\-tdrr: Top\-down register reduction list scheduling
257 =list\-td: Top\-down list scheduler \-print\-machineinstrs \- Print generated machine code
265 \fB\-regalloc\fP=\fIallocator\fP
268 Register allocator to use (default=linearscan)
274 =bigblock: Big\-block register allocator
275 =linearscan: linear scan register allocator =local \- local register allocator
276 =simple: simple register allocator
284 \fB\-relocation\-model\fP=\fImodel\fP
287 Choose relocation model from:
293 =default: Target default relocation model
294 =static: Non\-relocatable code =pic \- Fully relocatable, position independent code
295 =dynamic\-no\-pic: Relocatable external references, non\-relocatable code
306 Spiller to use (default=local)
312 =simple: simple spiller
313 =local: local spiller
321 \fB\-x86\-asm\-syntax\fP=\fIsyntax\fP
324 Choose style of code to emit from X86 backend:
330 =att: Emit AT&T\-style assembly
331 =intel: Emit Intel\-style assembly
340 If \fBlli\fP fails to load the program, it will exit with an exit code of 1.
341 Otherwise, it will return the exit code of the program it executes.
346 Maintained by The LLVM Team (http://llvm.org/).
348 2003-2013, LLVM Project
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