2 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org>
3 * Copyright (c) 2015-2016 Alexander Motin <mav@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/linker_set.h>
37 #include <sys/ioctl.h>
40 #include <sys/endian.h>
52 #include <pthread_np.h>
61 #define DEF_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */
62 #define MAX_PORTS 32 /* AHCI supports 32 ports */
64 #define PxSIG_ATA 0x00000101 /* ATA drive */
65 #define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */
68 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */
69 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */
70 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */
71 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */
72 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */
73 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */
74 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */
75 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */
81 #define TEST_UNIT_READY 0x00
82 #define REQUEST_SENSE 0x03
84 #define START_STOP_UNIT 0x1B
85 #define PREVENT_ALLOW 0x1E
86 #define READ_CAPACITY 0x25
88 #define POSITION_TO_ELEMENT 0x2B
90 #define GET_EVENT_STATUS_NOTIFICATION 0x4A
91 #define MODE_SENSE_10 0x5A
92 #define REPORT_LUNS 0xA0
97 * SCSI mode page codes
99 #define MODEPAGE_RW_ERROR_RECOVERY 0x01
100 #define MODEPAGE_CD_CAPABILITIES 0x2A
105 #define ATA_SF_ENAB_SATA_SF 0x10
106 #define ATA_SATA_SF_AN 0x05
107 #define ATA_SF_DIS_SATA_SF 0x90
114 #define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0)
116 #define DPRINTF(format, arg...)
118 #define WPRINTF(format, arg...) printf(format, ##arg)
121 struct blockif_req io_req;
122 struct ahci_port *io_pr;
123 STAILQ_ENTRY(ahci_ioreq) io_flist;
124 TAILQ_ENTRY(ahci_ioreq) io_blist;
133 struct blockif_ctxt *bctx;
134 struct pci_ahci_softc *pr_sc;
144 uint8_t err_cfis[20];
171 struct ahci_ioreq *ioreq;
173 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd;
174 TAILQ_HEAD(ahci_bhead, ahci_ioreq) iobhd;
177 struct ahci_cmd_hdr {
182 uint32_t reserved[4];
185 struct ahci_prdt_entry {
188 #define DBCMASK 0x3fffff
192 struct pci_ahci_softc {
193 struct pci_devinst *asc_pi;
208 struct ahci_port port[MAX_PORTS];
210 #define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx)
212 static void ahci_handle_port(struct ahci_port *p);
214 static inline void lba_to_msf(uint8_t *buf, int lba)
217 buf[0] = (lba / 75) / 60;
218 buf[1] = (lba / 75) % 60;
223 * Generate HBA interrupts on global IS register write.
226 ahci_generate_intr(struct pci_ahci_softc *sc, uint32_t mask)
228 struct pci_devinst *pi = sc->asc_pi;
233 /* Update global IS from PxIS/PxIE. */
234 for (i = 0; i < sc->ports; i++) {
239 DPRINTF("%s(%08x) %08x\n", __func__, mask, sc->is);
241 /* If there is nothing enabled -- clear legacy interrupt and exit. */
242 if (sc->is == 0 || (sc->ghc & AHCI_GHC_IE) == 0) {
244 pci_lintr_deassert(pi);
250 /* If there is anything and no MSI -- assert legacy interrupt. */
251 nmsg = pci_msi_maxmsgnum(pi);
255 pci_lintr_assert(pi);
260 /* Assert respective MSIs for ports that were touched. */
261 for (i = 0; i < nmsg; i++) {
262 if (sc->ports <= nmsg || i < nmsg - 1)
265 mmask = 0xffffffff << i;
266 if (sc->is & mask && mmask & mask)
267 pci_generate_msi(pi, i);
272 * Generate HBA interrupt on specific port event.
275 ahci_port_intr(struct ahci_port *p)
277 struct pci_ahci_softc *sc = p->pr_sc;
278 struct pci_devinst *pi = sc->asc_pi;
281 DPRINTF("%s(%d) %08x/%08x %08x\n", __func__,
282 p->port, p->is, p->ie, sc->is);
284 /* If there is nothing enabled -- we are done. */
285 if ((p->is & p->ie) == 0)
288 /* In case of non-shared MSI always generate interrupt. */
289 nmsg = pci_msi_maxmsgnum(pi);
290 if (sc->ports <= nmsg || p->port < nmsg - 1) {
291 sc->is |= (1 << p->port);
292 if ((sc->ghc & AHCI_GHC_IE) == 0)
294 pci_generate_msi(pi, p->port);
298 /* If IS for this port is already set -- do nothing. */
299 if (sc->is & (1 << p->port))
302 sc->is |= (1 << p->port);
304 /* If interrupts are enabled -- generate one. */
305 if ((sc->ghc & AHCI_GHC_IE) == 0)
308 pci_generate_msi(pi, nmsg - 1);
309 } else if (!sc->lintr) {
311 pci_lintr_assert(pi);
316 ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis)
318 int offset, len, irq;
320 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE))
324 case FIS_TYPE_REGD2H:
327 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_DHR : 0;
329 case FIS_TYPE_SETDEVBITS:
332 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_SDB : 0;
334 case FIS_TYPE_PIOSETUP:
337 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_PS : 0;
340 WPRINTF("unsupported fis type %d\n", ft);
343 if (fis[2] & ATA_S_ERROR) {
345 irq |= AHCI_P_IX_TFE;
347 memcpy(p->rfis + offset, fis, len);
357 ahci_write_fis_piosetup(struct ahci_port *p)
361 memset(fis, 0, sizeof(fis));
362 fis[0] = FIS_TYPE_PIOSETUP;
363 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis);
367 ahci_write_fis_sdb(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
372 error = (tfd >> 8) & 0xff;
374 memset(fis, 0, sizeof(fis));
375 fis[0] = FIS_TYPE_SETDEVBITS;
379 if (fis[2] & ATA_S_ERROR) {
380 p->err_cfis[0] = slot;
381 p->err_cfis[2] = tfd;
382 p->err_cfis[3] = error;
383 memcpy(&p->err_cfis[4], cfis + 4, 16);
385 *(uint32_t *)(fis + 4) = (1 << slot);
386 p->sact &= ~(1 << slot);
390 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis);
394 ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
399 error = (tfd >> 8) & 0xff;
400 memset(fis, 0, sizeof(fis));
401 fis[0] = FIS_TYPE_REGD2H;
415 if (fis[2] & ATA_S_ERROR) {
416 p->err_cfis[0] = 0x80;
417 p->err_cfis[2] = tfd & 0xff;
418 p->err_cfis[3] = error;
419 memcpy(&p->err_cfis[4], cfis + 4, 16);
421 p->ci &= ~(1 << slot);
423 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
427 ahci_write_fis_d2h_ncq(struct ahci_port *p, int slot)
431 p->tfd = ATA_S_READY | ATA_S_DSC;
432 memset(fis, 0, sizeof(fis));
433 fis[0] = FIS_TYPE_REGD2H;
434 fis[1] = 0; /* No interrupt */
435 fis[2] = p->tfd; /* Status */
436 fis[3] = 0; /* No error */
437 p->ci &= ~(1 << slot);
438 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
442 ahci_write_reset_fis_d2h(struct ahci_port *p)
446 memset(fis, 0, sizeof(fis));
447 fis[0] = FIS_TYPE_REGD2H;
455 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
459 ahci_check_stopped(struct ahci_port *p)
462 * If we are no longer processing the command list and nothing
463 * is in-flight, clear the running bit, the current command
464 * slot, the command issue and active bits.
466 if (!(p->cmd & AHCI_P_CMD_ST)) {
467 if (p->pending == 0) {
469 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK);
478 ahci_port_stop(struct ahci_port *p)
480 struct ahci_ioreq *aior;
486 assert(pthread_mutex_isowned_np(&p->pr_sc->mtx));
488 TAILQ_FOREACH(aior, &p->iobhd, io_blist) {
490 * Try to cancel the outstanding blockif request.
492 error = blockif_cancel(p->bctx, &aior->io_req);
498 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
499 cfis[2] == ATA_READ_FPDMA_QUEUED ||
500 cfis[2] == ATA_SEND_FPDMA_QUEUED)
504 p->sact &= ~(1 << slot);
506 p->ci &= ~(1 << slot);
509 * This command is now done.
511 p->pending &= ~(1 << slot);
514 * Delete the blockif request from the busy list
516 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
519 * Move the blockif request back to the free list
521 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
524 ahci_check_stopped(p);
528 ahci_port_reset(struct ahci_port *pr)
532 pr->xfermode = ATA_UDMA6;
533 pr->mult_sectors = 128;
536 pr->ssts = ATA_SS_DET_NO_DEVICE;
537 pr->sig = 0xFFFFFFFF;
541 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_IPM_ACTIVE;
542 if (pr->sctl & ATA_SC_SPD_MASK)
543 pr->ssts |= (pr->sctl & ATA_SC_SPD_MASK);
545 pr->ssts |= ATA_SS_SPD_GEN3;
546 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA;
549 pr->tfd |= ATA_S_READY;
551 pr->sig = PxSIG_ATAPI;
552 ahci_write_reset_fis_d2h(pr);
556 ahci_reset(struct pci_ahci_softc *sc)
560 sc->ghc = AHCI_GHC_AE;
564 pci_lintr_deassert(sc->asc_pi);
568 for (i = 0; i < sc->ports; i++) {
571 sc->port[i].cmd = (AHCI_P_CMD_SUD | AHCI_P_CMD_POD);
572 if (sc->port[i].bctx)
573 sc->port[i].cmd |= AHCI_P_CMD_CPS;
574 sc->port[i].sctl = 0;
575 ahci_port_reset(&sc->port[i]);
580 ata_string(uint8_t *dest, const char *src, int len)
584 for (i = 0; i < len; i++) {
586 dest[i ^ 1] = *src++;
593 atapi_string(uint8_t *dest, const char *src, int len)
597 for (i = 0; i < len; i++) {
606 * Build up the iovec based on the PRDT, 'done' and 'len'.
609 ahci_build_iov(struct ahci_port *p, struct ahci_ioreq *aior,
610 struct ahci_prdt_entry *prdt, uint16_t prdtl)
612 struct blockif_req *breq = &aior->io_req;
613 int i, j, skip, todo, left, extra;
616 /* Copy part of PRDT between 'done' and 'len' bytes into the iov. */
618 left = aior->len - aior->done;
620 for (i = 0, j = 0; i < prdtl && j < BLOCKIF_IOV_MAX && left > 0;
622 dbcsz = (prdt->dbc & DBCMASK) + 1;
623 /* Skip already done part of the PRDT */
631 breq->br_iov[j].iov_base = paddr_guest2host(ahci_ctx(p->pr_sc),
632 prdt->dba + skip, dbcsz);
633 breq->br_iov[j].iov_len = dbcsz;
640 /* If we got limited by IOV length, round I/O down to sector size. */
641 if (j == BLOCKIF_IOV_MAX) {
642 extra = todo % blockif_sectsz(p->bctx);
646 if (breq->br_iov[j - 1].iov_len > extra) {
647 breq->br_iov[j - 1].iov_len -= extra;
650 extra -= breq->br_iov[j - 1].iov_len;
656 breq->br_resid = todo;
658 aior->more = (aior->done < aior->len && i < prdtl);
662 ahci_handle_rw(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
664 struct ahci_ioreq *aior;
665 struct blockif_req *breq;
666 struct ahci_prdt_entry *prdt;
667 struct ahci_cmd_hdr *hdr;
670 int err, first, ncq, readop;
672 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
673 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
678 if (cfis[2] == ATA_WRITE || cfis[2] == ATA_WRITE48 ||
679 cfis[2] == ATA_WRITE_MUL || cfis[2] == ATA_WRITE_MUL48 ||
680 cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 ||
681 cfis[2] == ATA_WRITE_FPDMA_QUEUED)
684 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
685 cfis[2] == ATA_READ_FPDMA_QUEUED) {
686 lba = ((uint64_t)cfis[10] << 40) |
687 ((uint64_t)cfis[9] << 32) |
688 ((uint64_t)cfis[8] << 24) |
689 ((uint64_t)cfis[6] << 16) |
690 ((uint64_t)cfis[5] << 8) |
692 len = cfis[11] << 8 | cfis[3];
696 } else if (cfis[2] == ATA_READ48 || cfis[2] == ATA_WRITE48 ||
697 cfis[2] == ATA_READ_MUL48 || cfis[2] == ATA_WRITE_MUL48 ||
698 cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) {
699 lba = ((uint64_t)cfis[10] << 40) |
700 ((uint64_t)cfis[9] << 32) |
701 ((uint64_t)cfis[8] << 24) |
702 ((uint64_t)cfis[6] << 16) |
703 ((uint64_t)cfis[5] << 8) |
705 len = cfis[13] << 8 | cfis[12];
709 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) |
710 (cfis[5] << 8) | cfis[4];
715 lba *= blockif_sectsz(p->bctx);
716 len *= blockif_sectsz(p->bctx);
718 /* Pull request off free list */
719 aior = STAILQ_FIRST(&p->iofhd);
720 assert(aior != NULL);
721 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
727 breq = &aior->io_req;
728 breq->br_offset = lba + done;
729 ahci_build_iov(p, aior, prdt, hdr->prdtl);
731 /* Mark this command in-flight. */
732 p->pending |= 1 << slot;
734 /* Stuff request onto busy list. */
735 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
738 ahci_write_fis_d2h_ncq(p, slot);
741 err = blockif_read(p->bctx, breq);
743 err = blockif_write(p->bctx, breq);
748 ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis)
750 struct ahci_ioreq *aior;
751 struct blockif_req *breq;
755 * Pull request off free list
757 aior = STAILQ_FIRST(&p->iofhd);
758 assert(aior != NULL);
759 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
765 breq = &aior->io_req;
768 * Mark this command in-flight.
770 p->pending |= 1 << slot;
773 * Stuff request onto busy list
775 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
777 err = blockif_flush(p->bctx, breq);
782 read_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
785 struct ahci_cmd_hdr *hdr;
786 struct ahci_prdt_entry *prdt;
790 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
793 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
794 for (i = 0; i < hdr->prdtl && len; i++) {
799 dbcsz = (prdt->dbc & DBCMASK) + 1;
800 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
801 sublen = len < dbcsz ? len : dbcsz;
802 memcpy(to, ptr, sublen);
810 ahci_handle_dsm_trim(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
812 struct ahci_ioreq *aior;
813 struct blockif_req *breq;
821 if (cfis[2] == ATA_DATA_SET_MANAGEMENT) {
822 len = (uint16_t)cfis[13] << 8 | cfis[12];
825 } else { /* ATA_SEND_FPDMA_QUEUED */
826 len = (uint16_t)cfis[11] << 8 | cfis[3];
830 read_prdt(p, slot, cfis, buf, sizeof(buf));
834 elba = ((uint64_t)entry[5] << 40) |
835 ((uint64_t)entry[4] << 32) |
836 ((uint64_t)entry[3] << 24) |
837 ((uint64_t)entry[2] << 16) |
838 ((uint64_t)entry[1] << 8) |
840 elen = (uint16_t)entry[7] << 8 | entry[6];
846 ahci_write_fis_d2h_ncq(p, slot);
847 ahci_write_fis_sdb(p, slot, cfis,
848 ATA_S_READY | ATA_S_DSC);
850 ahci_write_fis_d2h(p, slot, cfis,
851 ATA_S_READY | ATA_S_DSC);
853 p->pending &= ~(1 << slot);
854 ahci_check_stopped(p);
863 * Pull request off free list
865 aior = STAILQ_FIRST(&p->iofhd);
866 assert(aior != NULL);
867 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
872 aior->more = (len != done);
874 breq = &aior->io_req;
875 breq->br_offset = elba * blockif_sectsz(p->bctx);
876 breq->br_resid = elen * blockif_sectsz(p->bctx);
879 * Mark this command in-flight.
881 p->pending |= 1 << slot;
884 * Stuff request onto busy list
886 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
889 ahci_write_fis_d2h_ncq(p, slot);
891 err = blockif_delete(p->bctx, breq);
896 write_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
899 struct ahci_cmd_hdr *hdr;
900 struct ahci_prdt_entry *prdt;
904 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
907 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
908 for (i = 0; i < hdr->prdtl && len; i++) {
913 dbcsz = (prdt->dbc & DBCMASK) + 1;
914 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
915 sublen = len < dbcsz ? len : dbcsz;
916 memcpy(ptr, from, sublen);
921 hdr->prdbc = size - len;
925 ahci_checksum(uint8_t *buf, int size)
930 for (i = 0; i < size - 1; i++)
932 buf[size - 1] = 0x100 - sum;
936 ahci_handle_read_log(struct ahci_port *p, int slot, uint8_t *cfis)
938 struct ahci_cmd_hdr *hdr;
941 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
942 if (p->atapi || hdr->prdtl == 0 || cfis[4] != 0x10 ||
943 cfis[5] != 0 || cfis[9] != 0 || cfis[12] != 1 || cfis[13] != 0) {
944 ahci_write_fis_d2h(p, slot, cfis,
945 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
949 memset(buf, 0, sizeof(buf));
950 memcpy(buf, p->err_cfis, sizeof(p->err_cfis));
951 ahci_checksum(buf, sizeof(buf));
953 if (cfis[2] == ATA_READ_LOG_EXT)
954 ahci_write_fis_piosetup(p);
955 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
956 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
960 handle_identify(struct ahci_port *p, int slot, uint8_t *cfis)
962 struct ahci_cmd_hdr *hdr;
964 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
965 if (p->atapi || hdr->prdtl == 0) {
966 ahci_write_fis_d2h(p, slot, cfis,
967 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
971 int sectsz, psectsz, psectoff, candelete, ro;
975 ro = blockif_is_ro(p->bctx);
976 candelete = blockif_candelete(p->bctx);
977 sectsz = blockif_sectsz(p->bctx);
978 sectors = blockif_size(p->bctx) / sectsz;
979 blockif_chs(p->bctx, &cyl, &heads, &sech);
980 blockif_psectsz(p->bctx, &psectsz, &psectoff);
981 memset(buf, 0, sizeof(buf));
986 ata_string((uint8_t *)(buf+10), p->ident, 20);
987 ata_string((uint8_t *)(buf+23), "001", 8);
988 ata_string((uint8_t *)(buf+27), "BHYVE SATA DISK", 40);
989 buf[47] = (0x8000 | 128);
991 buf[49] = (1 << 8 | 1 << 9 | 1 << 11);
993 buf[53] = (1 << 1 | 1 << 2);
995 buf[59] = (0x100 | p->mult_sectors);
996 if (sectors <= 0x0fffffff) {
998 buf[61] = (sectors >> 16);
1004 if (p->xfermode & ATA_WDMA0)
1005 buf[63] |= (1 << ((p->xfermode & 7) + 8));
1013 buf[76] = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3 |
1015 buf[77] = (ATA_SUPPORT_RCVSND_FPDMA_QUEUED |
1016 (p->ssts & ATA_SS_SPD_MASK) >> 3);
1019 buf[82] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE|
1020 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
1021 buf[83] = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
1022 ATA_SUPPORT_FLUSHCACHE48 | 1 << 14);
1023 buf[84] = (1 << 14);
1024 buf[85] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE|
1025 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
1026 buf[86] = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
1027 ATA_SUPPORT_FLUSHCACHE48 | 1 << 15);
1028 buf[87] = (1 << 14);
1030 if (p->xfermode & ATA_UDMA0)
1031 buf[88] |= (1 << ((p->xfermode & 7) + 8));
1033 buf[101] = (sectors >> 16);
1034 buf[102] = (sectors >> 32);
1035 buf[103] = (sectors >> 48);
1036 if (candelete && !ro) {
1037 buf[69] |= ATA_SUPPORT_RZAT | ATA_SUPPORT_DRAT;
1039 buf[169] = ATA_SUPPORT_DSM_TRIM;
1043 if (psectsz > sectsz) {
1045 buf[106] |= ffsl(psectsz / sectsz) - 1;
1046 buf[209] |= (psectoff / sectsz);
1050 buf[117] = sectsz / 2;
1051 buf[118] = ((sectsz / 2) >> 16);
1053 buf[119] = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14);
1054 buf[120] = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14);
1057 ahci_checksum((uint8_t *)buf, sizeof(buf));
1058 ahci_write_fis_piosetup(p);
1059 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
1060 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
1065 handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis)
1068 ahci_write_fis_d2h(p, slot, cfis,
1069 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1073 memset(buf, 0, sizeof(buf));
1074 buf[0] = (2 << 14 | 5 << 8 | 1 << 7 | 2 << 5);
1075 ata_string((uint8_t *)(buf+10), p->ident, 20);
1076 ata_string((uint8_t *)(buf+23), "001", 8);
1077 ata_string((uint8_t *)(buf+27), "BHYVE SATA DVD ROM", 40);
1078 buf[49] = (1 << 9 | 1 << 8);
1079 buf[50] = (1 << 14 | 1);
1080 buf[53] = (1 << 2 | 1 << 1);
1083 if (p->xfermode & ATA_WDMA0)
1084 buf[63] |= (1 << ((p->xfermode & 7) + 8));
1090 buf[76] = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3);
1091 buf[77] = ((p->ssts & ATA_SS_SPD_MASK) >> 3);
1094 buf[82] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET |
1095 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP);
1096 buf[83] = (1 << 14);
1097 buf[84] = (1 << 14);
1098 buf[85] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET |
1099 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP);
1100 buf[87] = (1 << 14);
1102 if (p->xfermode & ATA_UDMA0)
1103 buf[88] |= (1 << ((p->xfermode & 7) + 8));
1106 ahci_checksum((uint8_t *)buf, sizeof(buf));
1107 ahci_write_fis_piosetup(p);
1108 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
1109 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
1114 atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis)
1123 if (acmd[1] & 1) { /* VPD */
1124 if (acmd[2] == 0) { /* Supported VPD pages */
1132 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1134 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1135 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1136 ahci_write_fis_d2h(p, slot, cfis, tfd);
1148 atapi_string(buf + 8, "BHYVE", 8);
1149 atapi_string(buf + 16, "BHYVE DVD-ROM", 16);
1150 atapi_string(buf + 32, "001", 4);
1156 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1157 write_prdt(p, slot, cfis, buf, len);
1158 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1162 atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis)
1167 sectors = blockif_size(p->bctx) / 2048;
1168 be32enc(buf, sectors - 1);
1169 be32enc(buf + 4, 2048);
1170 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1171 write_prdt(p, slot, cfis, buf, sizeof(buf));
1172 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1176 atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis)
1184 len = be16dec(acmd + 7);
1185 format = acmd[9] >> 6;
1191 uint8_t start_track, buf[20], *bp;
1193 msf = (acmd[1] >> 1) & 1;
1194 start_track = acmd[6];
1195 if (start_track > 1 && start_track != 0xaa) {
1197 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1199 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1200 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1201 ahci_write_fis_d2h(p, slot, cfis, tfd);
1207 if (start_track <= 1) {
1227 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1231 lba_to_msf(bp, sectors);
1234 be32enc(bp, sectors);
1238 be16enc(buf, size - 2);
1241 write_prdt(p, slot, cfis, buf, len);
1242 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1243 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1250 memset(buf, 0, sizeof(buf));
1254 if (len > sizeof(buf))
1256 write_prdt(p, slot, cfis, buf, len);
1257 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1258 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1265 uint8_t start_track, *bp, buf[50];
1267 msf = (acmd[1] >> 1) & 1;
1268 start_track = acmd[6];
1304 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1308 lba_to_msf(bp, sectors);
1311 be32enc(bp, sectors);
1334 be16enc(buf, size - 2);
1337 write_prdt(p, slot, cfis, buf, len);
1338 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1339 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1346 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1348 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1349 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1350 ahci_write_fis_d2h(p, slot, cfis, tfd);
1357 atapi_report_luns(struct ahci_port *p, int slot, uint8_t *cfis)
1361 memset(buf, 0, sizeof(buf));
1364 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1365 write_prdt(p, slot, cfis, buf, sizeof(buf));
1366 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1370 atapi_read(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
1372 struct ahci_ioreq *aior;
1373 struct ahci_cmd_hdr *hdr;
1374 struct ahci_prdt_entry *prdt;
1375 struct blockif_req *breq;
1376 struct pci_ahci_softc *sc;
1384 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1385 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1387 lba = be32dec(acmd + 2);
1388 if (acmd[0] == READ_10)
1389 len = be16dec(acmd + 7);
1391 len = be32dec(acmd + 6);
1393 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1394 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1400 * Pull request off free list
1402 aior = STAILQ_FIRST(&p->iofhd);
1403 assert(aior != NULL);
1404 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
1409 breq = &aior->io_req;
1410 breq->br_offset = lba + done;
1411 ahci_build_iov(p, aior, prdt, hdr->prdtl);
1413 /* Mark this command in-flight. */
1414 p->pending |= 1 << slot;
1416 /* Stuff request onto busy list. */
1417 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
1419 err = blockif_read(p->bctx, breq);
1424 atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1432 if (len > sizeof(buf))
1434 memset(buf, 0, len);
1435 buf[0] = 0x70 | (1 << 7);
1436 buf[2] = p->sense_key;
1439 write_prdt(p, slot, cfis, buf, len);
1440 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1441 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1445 atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis)
1447 uint8_t *acmd = cfis + 0x40;
1450 switch (acmd[4] & 3) {
1454 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1455 tfd = ATA_S_READY | ATA_S_DSC;
1458 /* TODO eject media */
1459 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1460 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1462 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1465 ahci_write_fis_d2h(p, slot, cfis, tfd);
1469 atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1477 len = be16dec(acmd + 7);
1479 code = acmd[2] & 0x3f;
1484 case MODEPAGE_RW_ERROR_RECOVERY:
1488 if (len > sizeof(buf))
1491 memset(buf, 0, sizeof(buf));
1492 be16enc(buf, 16 - 2);
1497 write_prdt(p, slot, cfis, buf, len);
1498 tfd = ATA_S_READY | ATA_S_DSC;
1501 case MODEPAGE_CD_CAPABILITIES:
1505 if (len > sizeof(buf))
1508 memset(buf, 0, sizeof(buf));
1509 be16enc(buf, 30 - 2);
1515 be16enc(&buf[18], 2);
1516 be16enc(&buf[20], 512);
1517 write_prdt(p, slot, cfis, buf, len);
1518 tfd = ATA_S_READY | ATA_S_DSC;
1527 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1529 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1534 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1536 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1539 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1540 ahci_write_fis_d2h(p, slot, cfis, tfd);
1544 atapi_get_event_status_notification(struct ahci_port *p, int slot,
1552 /* we don't support asynchronous operation */
1553 if (!(acmd[1] & 1)) {
1554 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1556 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1561 len = be16dec(acmd + 7);
1562 if (len > sizeof(buf))
1565 memset(buf, 0, sizeof(buf));
1566 be16enc(buf, 8 - 2);
1570 write_prdt(p, slot, cfis, buf, len);
1571 tfd = ATA_S_READY | ATA_S_DSC;
1573 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1574 ahci_write_fis_d2h(p, slot, cfis, tfd);
1578 handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1588 for (i = 0; i < 16; i++)
1589 DPRINTF("%02x ", acmd[i]);
1595 case TEST_UNIT_READY:
1596 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1597 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1600 atapi_inquiry(p, slot, cfis);
1603 atapi_read_capacity(p, slot, cfis);
1607 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1608 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1611 atapi_read_toc(p, slot, cfis);
1614 atapi_report_luns(p, slot, cfis);
1618 atapi_read(p, slot, cfis, 0);
1621 atapi_request_sense(p, slot, cfis);
1623 case START_STOP_UNIT:
1624 atapi_start_stop_unit(p, slot, cfis);
1627 atapi_mode_sense(p, slot, cfis);
1629 case GET_EVENT_STATUS_NOTIFICATION:
1630 atapi_get_event_status_notification(p, slot, cfis);
1633 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1634 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1636 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) |
1637 ATA_S_READY | ATA_S_ERROR);
1643 ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1646 p->tfd |= ATA_S_BUSY;
1648 case ATA_ATA_IDENTIFY:
1649 handle_identify(p, slot, cfis);
1651 case ATA_SETFEATURES:
1654 case ATA_SF_ENAB_SATA_SF:
1656 case ATA_SATA_SF_AN:
1657 p->tfd = ATA_S_DSC | ATA_S_READY;
1660 p->tfd = ATA_S_ERROR | ATA_S_READY;
1661 p->tfd |= (ATA_ERROR_ABORT << 8);
1665 case ATA_SF_ENAB_WCACHE:
1666 case ATA_SF_DIS_WCACHE:
1667 case ATA_SF_ENAB_RCACHE:
1668 case ATA_SF_DIS_RCACHE:
1669 p->tfd = ATA_S_DSC | ATA_S_READY;
1671 case ATA_SF_SETXFER:
1673 switch (cfis[12] & 0xf8) {
1679 p->xfermode = (cfis[12] & 0x7);
1682 p->tfd = ATA_S_DSC | ATA_S_READY;
1686 p->tfd = ATA_S_ERROR | ATA_S_READY;
1687 p->tfd |= (ATA_ERROR_ABORT << 8);
1690 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1694 if (cfis[12] != 0 &&
1695 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) {
1696 p->tfd = ATA_S_ERROR | ATA_S_READY;
1697 p->tfd |= (ATA_ERROR_ABORT << 8);
1699 p->mult_sectors = cfis[12];
1700 p->tfd = ATA_S_DSC | ATA_S_READY;
1702 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1710 case ATA_READ_MUL48:
1711 case ATA_WRITE_MUL48:
1714 case ATA_READ_DMA48:
1715 case ATA_WRITE_DMA48:
1716 case ATA_READ_FPDMA_QUEUED:
1717 case ATA_WRITE_FPDMA_QUEUED:
1718 ahci_handle_rw(p, slot, cfis, 0);
1720 case ATA_FLUSHCACHE:
1721 case ATA_FLUSHCACHE48:
1722 ahci_handle_flush(p, slot, cfis);
1724 case ATA_DATA_SET_MANAGEMENT:
1725 if (cfis[11] == 0 && cfis[3] == ATA_DSM_TRIM &&
1726 cfis[13] == 0 && cfis[12] == 1) {
1727 ahci_handle_dsm_trim(p, slot, cfis, 0);
1730 ahci_write_fis_d2h(p, slot, cfis,
1731 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1733 case ATA_SEND_FPDMA_QUEUED:
1734 if ((cfis[13] & 0x1f) == ATA_SFPDMA_DSM &&
1735 cfis[17] == 0 && cfis[16] == ATA_DSM_TRIM &&
1736 cfis[11] == 0 && cfis[3] == 1) {
1737 ahci_handle_dsm_trim(p, slot, cfis, 0);
1740 ahci_write_fis_d2h(p, slot, cfis,
1741 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1743 case ATA_READ_LOG_EXT:
1744 case ATA_READ_LOG_DMA_EXT:
1745 ahci_handle_read_log(p, slot, cfis);
1747 case ATA_SECURITY_FREEZE_LOCK:
1750 ahci_write_fis_d2h(p, slot, cfis,
1751 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1753 case ATA_CHECK_POWER_MODE:
1754 cfis[12] = 0xff; /* always on */
1755 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1757 case ATA_STANDBY_CMD:
1758 case ATA_STANDBY_IMMEDIATE:
1760 case ATA_IDLE_IMMEDIATE:
1762 case ATA_READ_VERIFY:
1763 case ATA_READ_VERIFY48:
1764 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1766 case ATA_ATAPI_IDENTIFY:
1767 handle_atapi_identify(p, slot, cfis);
1769 case ATA_PACKET_CMD:
1771 ahci_write_fis_d2h(p, slot, cfis,
1772 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1774 handle_packet_cmd(p, slot, cfis);
1777 WPRINTF("Unsupported cmd:%02x\n", cfis[2]);
1778 ahci_write_fis_d2h(p, slot, cfis,
1779 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1785 ahci_handle_slot(struct ahci_port *p, int slot)
1787 struct ahci_cmd_hdr *hdr;
1789 struct ahci_prdt_entry *prdt;
1791 struct pci_ahci_softc *sc;
1798 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1800 cfl = (hdr->flags & 0x1f) * 4;
1802 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba,
1803 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry));
1805 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1808 for (i = 0; i < cfl; i++) {
1811 DPRINTF("%02x ", cfis[i]);
1815 for (i = 0; i < hdr->prdtl; i++) {
1816 DPRINTF("%d@%08"PRIx64"\n", prdt->dbc & 0x3fffff, prdt->dba);
1821 if (cfis[0] != FIS_TYPE_REGH2D) {
1822 WPRINTF("Not a H2D FIS:%02x\n", cfis[0]);
1826 if (cfis[1] & 0x80) {
1827 ahci_handle_cmd(p, slot, cfis);
1829 if (cfis[15] & (1 << 2))
1831 else if (p->reset) {
1835 p->ci &= ~(1 << slot);
1840 ahci_handle_port(struct ahci_port *p)
1843 if (!(p->cmd & AHCI_P_CMD_ST))
1847 * Search for any new commands to issue ignoring those that
1848 * are already in-flight. Stop if device is busy or in error.
1850 for (; (p->ci & ~p->pending) != 0; p->ccs = ((p->ccs + 1) & 31)) {
1851 if ((p->tfd & (ATA_S_BUSY | ATA_S_DRQ)) != 0)
1853 if (p->waitforclear)
1855 if ((p->ci & ~p->pending & (1 << p->ccs)) != 0) {
1856 p->cmd &= ~AHCI_P_CMD_CCS_MASK;
1857 p->cmd |= p->ccs << AHCI_P_CMD_CCS_SHIFT;
1858 ahci_handle_slot(p, p->ccs);
1864 * blockif callback routine - this runs in the context of the blockif
1865 * i/o thread, so the mutex needs to be acquired.
1868 ata_ioreq_cb(struct blockif_req *br, int err)
1870 struct ahci_cmd_hdr *hdr;
1871 struct ahci_ioreq *aior;
1872 struct ahci_port *p;
1873 struct pci_ahci_softc *sc;
1878 DPRINTF("%s %d\n", __func__, err);
1881 aior = br->br_param;
1886 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1888 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
1889 cfis[2] == ATA_READ_FPDMA_QUEUED ||
1890 cfis[2] == ATA_SEND_FPDMA_QUEUED)
1892 if (cfis[2] == ATA_DATA_SET_MANAGEMENT ||
1893 (cfis[2] == ATA_SEND_FPDMA_QUEUED &&
1894 (cfis[13] & 0x1f) == ATA_SFPDMA_DSM))
1897 pthread_mutex_lock(&sc->mtx);
1900 * Delete the blockif request from the busy list
1902 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1905 * Move the blockif request back to the free list
1907 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1910 hdr->prdbc = aior->done;
1912 if (!err && aior->more) {
1914 ahci_handle_dsm_trim(p, slot, cfis, aior->done);
1916 ahci_handle_rw(p, slot, cfis, aior->done);
1921 tfd = ATA_S_READY | ATA_S_DSC;
1923 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1925 ahci_write_fis_sdb(p, slot, cfis, tfd);
1927 ahci_write_fis_d2h(p, slot, cfis, tfd);
1930 * This command is now complete.
1932 p->pending &= ~(1 << slot);
1934 ahci_check_stopped(p);
1935 ahci_handle_port(p);
1937 pthread_mutex_unlock(&sc->mtx);
1938 DPRINTF("%s exit\n", __func__);
1942 atapi_ioreq_cb(struct blockif_req *br, int err)
1944 struct ahci_cmd_hdr *hdr;
1945 struct ahci_ioreq *aior;
1946 struct ahci_port *p;
1947 struct pci_ahci_softc *sc;
1952 DPRINTF("%s %d\n", __func__, err);
1954 aior = br->br_param;
1959 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE);
1961 pthread_mutex_lock(&sc->mtx);
1964 * Delete the blockif request from the busy list
1966 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1969 * Move the blockif request back to the free list
1971 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1974 hdr->prdbc = aior->done;
1976 if (!err && aior->more) {
1977 atapi_read(p, slot, cfis, aior->done);
1982 tfd = ATA_S_READY | ATA_S_DSC;
1984 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1986 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1988 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1989 ahci_write_fis_d2h(p, slot, cfis, tfd);
1992 * This command is now complete.
1994 p->pending &= ~(1 << slot);
1996 ahci_check_stopped(p);
1997 ahci_handle_port(p);
1999 pthread_mutex_unlock(&sc->mtx);
2000 DPRINTF("%s exit\n", __func__);
2004 pci_ahci_ioreq_init(struct ahci_port *pr)
2006 struct ahci_ioreq *vr;
2009 pr->ioqsz = blockif_queuesz(pr->bctx);
2010 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq));
2011 STAILQ_INIT(&pr->iofhd);
2014 * Add all i/o request entries to the free queue
2016 for (i = 0; i < pr->ioqsz; i++) {
2020 vr->io_req.br_callback = ata_ioreq_cb;
2022 vr->io_req.br_callback = atapi_ioreq_cb;
2023 vr->io_req.br_param = vr;
2024 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_flist);
2027 TAILQ_INIT(&pr->iobhd);
2031 pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
2033 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
2034 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
2035 struct ahci_port *p = &sc->port[port];
2037 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
2038 port, offset, value);
2058 p->ie = value & 0xFDC000FF;
2063 p->cmd &= ~(AHCI_P_CMD_ST | AHCI_P_CMD_SUD | AHCI_P_CMD_POD |
2064 AHCI_P_CMD_CLO | AHCI_P_CMD_FRE | AHCI_P_CMD_APSTE |
2065 AHCI_P_CMD_ATAPI | AHCI_P_CMD_DLAE | AHCI_P_CMD_ALPE |
2066 AHCI_P_CMD_ASP | AHCI_P_CMD_ICC_MASK);
2067 p->cmd |= (AHCI_P_CMD_ST | AHCI_P_CMD_SUD | AHCI_P_CMD_POD |
2068 AHCI_P_CMD_CLO | AHCI_P_CMD_FRE | AHCI_P_CMD_APSTE |
2069 AHCI_P_CMD_ATAPI | AHCI_P_CMD_DLAE | AHCI_P_CMD_ALPE |
2070 AHCI_P_CMD_ASP | AHCI_P_CMD_ICC_MASK) & value;
2072 if (!(value & AHCI_P_CMD_ST)) {
2077 p->cmd |= AHCI_P_CMD_CR;
2078 clb = (uint64_t)p->clbu << 32 | p->clb;
2079 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb,
2080 AHCI_CL_SIZE * AHCI_MAX_SLOTS);
2083 if (value & AHCI_P_CMD_FRE) {
2086 p->cmd |= AHCI_P_CMD_FR;
2087 fb = (uint64_t)p->fbu << 32 | p->fb;
2088 /* we don't support FBSCP, so rfis size is 256Bytes */
2089 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256);
2091 p->cmd &= ~AHCI_P_CMD_FR;
2094 if (value & AHCI_P_CMD_CLO) {
2095 p->tfd &= ~(ATA_S_BUSY | ATA_S_DRQ);
2096 p->cmd &= ~AHCI_P_CMD_CLO;
2099 if (value & AHCI_P_CMD_ICC_MASK) {
2100 p->cmd &= ~AHCI_P_CMD_ICC_MASK;
2103 ahci_handle_port(p);
2109 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset);
2113 if (!(p->cmd & AHCI_P_CMD_ST)) {
2114 if (value & ATA_SC_DET_RESET)
2126 ahci_handle_port(p);
2136 pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
2138 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
2146 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset);
2149 if (value & AHCI_GHC_HR) {
2153 if (value & AHCI_GHC_IE)
2154 sc->ghc |= AHCI_GHC_IE;
2156 sc->ghc &= ~AHCI_GHC_IE;
2157 ahci_generate_intr(sc, 0xffffffff);
2161 ahci_generate_intr(sc, value);
2169 pci_ahci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
2170 int baridx, uint64_t offset, int size, uint64_t value)
2172 struct pci_ahci_softc *sc = pi->pi_arg;
2174 assert(baridx == 5);
2175 assert((offset % 4) == 0 && size == 4);
2177 pthread_mutex_lock(&sc->mtx);
2179 if (offset < AHCI_OFFSET)
2180 pci_ahci_host_write(sc, offset, value);
2181 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
2182 pci_ahci_port_write(sc, offset, value);
2184 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n", offset);
2186 pthread_mutex_unlock(&sc->mtx);
2190 pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset)
2206 uint32_t *p = &sc->cap;
2207 p += (offset - AHCI_CAP) / sizeof(uint32_t);
2215 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n",
2222 pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset)
2225 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
2226 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
2246 uint32_t *p= &sc->port[port].clb;
2247 p += (offset - AHCI_P_CLB) / sizeof(uint32_t);
2256 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n",
2257 port, offset, value);
2263 pci_ahci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
2264 uint64_t regoff, int size)
2266 struct pci_ahci_softc *sc = pi->pi_arg;
2270 assert(baridx == 5);
2271 assert(size == 1 || size == 2 || size == 4);
2272 assert((regoff & (size - 1)) == 0);
2274 pthread_mutex_lock(&sc->mtx);
2276 offset = regoff & ~0x3; /* round down to a multiple of 4 bytes */
2277 if (offset < AHCI_OFFSET)
2278 value = pci_ahci_host_read(sc, offset);
2279 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
2280 value = pci_ahci_port_read(sc, offset);
2283 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n",
2286 value >>= 8 * (regoff & 0x3);
2288 pthread_mutex_unlock(&sc->mtx);
2294 pci_ahci_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts, int atapi)
2296 char bident[sizeof("XX:XX:XX")];
2297 struct blockif_ctxt *bctxt;
2298 struct pci_ahci_softc *sc;
2307 dbg = fopen("/tmp/log", "w+");
2310 sc = calloc(1, sizeof(struct pci_ahci_softc));
2313 pthread_mutex_init(&sc->mtx, NULL);
2318 for (p = 0; p < MAX_PORTS && opts != NULL; p++, opts = next) {
2319 /* Identify and cut off type of present port. */
2320 if (strncmp(opts, "hd:", 3) == 0) {
2323 } else if (strncmp(opts, "cd:", 3) == 0) {
2328 /* Find and cut off the next port options. */
2329 next = strstr(opts, ",hd:");
2330 next2 = strstr(opts, ",cd:");
2331 if (next == NULL || (next2 != NULL && next2 < next))
2342 * Attempt to open the backing image. Use the PCI slot/func
2343 * and the port number for the identifier string.
2345 snprintf(bident, sizeof(bident), "%d:%d:%d", pi->pi_slot,
2347 bctxt = blockif_open(opts, bident);
2348 if (bctxt == NULL) {
2353 sc->port[p].bctx = bctxt;
2354 sc->port[p].pr_sc = sc;
2355 sc->port[p].port = p;
2356 sc->port[p].atapi = atapi;
2359 * Create an identifier for the backing file.
2360 * Use parts of the md5 sum of the filename
2363 MD5Update(&mdctx, opts, strlen(opts));
2364 MD5Final(digest, &mdctx);
2365 sprintf(sc->port[p].ident, "BHYVE-%02X%02X-%02X%02X-%02X%02X",
2366 digest[0], digest[1], digest[2], digest[3], digest[4],
2370 * Allocate blockif request structures and add them
2373 pci_ahci_ioreq_init(&sc->port[p]);
2376 if (sc->port[p].ioqsz < slots)
2377 slots = sc->port[p].ioqsz;
2381 /* Intel ICH8 AHCI */
2383 if (sc->ports < DEF_PORTS)
2384 sc->ports = DEF_PORTS;
2385 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF |
2386 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP |
2387 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)|
2388 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC |
2389 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1);
2392 sc->cap2 = AHCI_CAP2_APST;
2395 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821);
2396 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086);
2397 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE);
2398 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA);
2399 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0);
2400 p = MIN(sc->ports, 16);
2401 p = flsl(p) - ((p & (p - 1)) ? 0 : 1);
2402 pci_emul_add_msicap(pi, 1 << p);
2403 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32,
2404 AHCI_OFFSET + sc->ports * AHCI_STEP);
2406 pci_lintr_request(pi);
2410 for (p = 0; p < sc->ports; p++) {
2411 if (sc->port[p].bctx != NULL)
2412 blockif_close(sc->port[p].bctx);
2421 pci_ahci_hd_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
2424 return (pci_ahci_init(ctx, pi, opts, 0));
2428 pci_ahci_atapi_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
2431 return (pci_ahci_init(ctx, pi, opts, 1));
2435 * Use separate emulation names to distinguish drive and atapi devices
2437 struct pci_devemu pci_de_ahci = {
2439 .pe_init = pci_ahci_hd_init,
2440 .pe_barwrite = pci_ahci_write,
2441 .pe_barread = pci_ahci_read
2443 PCI_EMUL_SET(pci_de_ahci);
2445 struct pci_devemu pci_de_ahci_hd = {
2446 .pe_emu = "ahci-hd",
2447 .pe_init = pci_ahci_hd_init,
2448 .pe_barwrite = pci_ahci_write,
2449 .pe_barread = pci_ahci_read
2451 PCI_EMUL_SET(pci_de_ahci_hd);
2453 struct pci_devemu pci_de_ahci_cd = {
2454 .pe_emu = "ahci-cd",
2455 .pe_init = pci_ahci_atapi_init,
2456 .pe_barwrite = pci_ahci_write,
2457 .pe_barread = pci_ahci_read
2459 PCI_EMUL_SET(pci_de_ahci_cd);