2 * Copyright (c) 2016 Alexander Motin <mav@FreeBSD.org>
3 * Copyright (c) 2015 Peter Grehan <grehan@freebsd.org>
4 * Copyright (c) 2013 Jeremiah Lott, Avere Systems
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer
12 * in this position and unchanged.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/types.h>
34 #include <sys/limits.h>
35 #include <sys/ioctl.h>
37 #include <net/ethernet.h>
38 #include <netinet/in.h>
39 #include <netinet/tcp.h>
49 #include <pthread_np.h>
51 #include "e1000_regs.h"
52 #include "e1000_defines.h"
59 /* Hardware/register definitions XXX: move some to common code. */
60 #define E82545_VENDOR_ID_INTEL 0x8086
61 #define E82545_DEV_ID_82545EM_COPPER 0x100F
62 #define E82545_SUBDEV_ID 0x1008
64 #define E82545_REVISION_4 4
66 #define E82545_MDIC_DATA_MASK 0x0000FFFF
67 #define E82545_MDIC_OP_MASK 0x0c000000
68 #define E82545_MDIC_IE 0x20000000
70 #define E82545_EECD_FWE_DIS 0x00000010 /* Flash writes disabled */
71 #define E82545_EECD_FWE_EN 0x00000020 /* Flash writes enabled */
72 #define E82545_EECD_FWE_MASK 0x00000030 /* Flash writes mask */
74 #define E82545_BAR_REGISTER 0
75 #define E82545_BAR_REGISTER_LEN (128*1024)
76 #define E82545_BAR_FLASH 1
77 #define E82545_BAR_FLASH_LEN (64*1024)
78 #define E82545_BAR_IO 2
79 #define E82545_BAR_IO_LEN 8
81 #define E82545_IOADDR 0x00000000
82 #define E82545_IODATA 0x00000004
83 #define E82545_IO_REGISTER_MAX 0x0001FFFF
84 #define E82545_IO_FLASH_BASE 0x00080000
85 #define E82545_IO_FLASH_MAX 0x000FFFFF
87 #define E82545_ARRAY_ENTRY(reg, offset) (reg + (offset<<2))
88 #define E82545_RAR_MAX 15
89 #define E82545_MTA_MAX 127
90 #define E82545_VFTA_MAX 127
92 /* Slightly modified from the driver versions, hardcoded for 3 opcode bits,
93 * followed by 6 address bits.
94 * TODO: make opcode bits and addr bits configurable?
95 * NVM Commands - Microwire */
96 #define E82545_NVM_OPCODE_BITS 3
97 #define E82545_NVM_ADDR_BITS 6
98 #define E82545_NVM_DATA_BITS 16
99 #define E82545_NVM_OPADDR_BITS (E82545_NVM_OPCODE_BITS + E82545_NVM_ADDR_BITS)
100 #define E82545_NVM_ADDR_MASK ((1 << E82545_NVM_ADDR_BITS)-1)
101 #define E82545_NVM_OPCODE_MASK \
102 (((1 << E82545_NVM_OPCODE_BITS) - 1) << E82545_NVM_ADDR_BITS)
103 #define E82545_NVM_OPCODE_READ (0x6 << E82545_NVM_ADDR_BITS) /* read */
104 #define E82545_NVM_OPCODE_WRITE (0x5 << E82545_NVM_ADDR_BITS) /* write */
105 #define E82545_NVM_OPCODE_ERASE (0x7 << E82545_NVM_ADDR_BITS) /* erase */
106 #define E82545_NVM_OPCODE_EWEN (0x4 << E82545_NVM_ADDR_BITS) /* wr-enable */
108 #define E82545_NVM_EEPROM_SIZE 64 /* 64 * 16-bit values == 128K */
110 #define E1000_ICR_SRPD 0x00010000
112 /* This is an arbitrary number. There is no hard limit on the chip. */
113 #define I82545_MAX_TXSEGS 64
115 /* Legacy receive descriptor */
116 struct e1000_rx_desc {
117 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
118 uint16_t length; /* Length of data DMAed into data buffer */
119 uint16_t csum; /* Packet checksum */
120 uint8_t status; /* Descriptor status */
121 uint8_t errors; /* Descriptor Errors */
125 /* Transmit descriptor types */
126 #define E1000_TXD_MASK (E1000_TXD_CMD_DEXT | 0x00F00000)
127 #define E1000_TXD_TYP_L (0)
128 #define E1000_TXD_TYP_C (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_C)
129 #define E1000_TXD_TYP_D (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)
131 /* Legacy transmit descriptor */
132 struct e1000_tx_desc {
133 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
137 uint16_t length; /* Data buffer length */
138 uint8_t cso; /* Checksum offset */
139 uint8_t cmd; /* Descriptor control */
145 uint8_t status; /* Descriptor status */
146 uint8_t css; /* Checksum start */
152 /* Context descriptor */
153 struct e1000_context_desc {
157 uint8_t ipcss; /* IP checksum start */
158 uint8_t ipcso; /* IP checksum offset */
159 uint16_t ipcse; /* IP checksum end */
165 uint8_t tucss; /* TCP checksum start */
166 uint8_t tucso; /* TCP checksum offset */
167 uint16_t tucse; /* TCP checksum end */
170 uint32_t cmd_and_length;
174 uint8_t status; /* Descriptor status */
175 uint8_t hdr_len; /* Header length */
176 uint16_t mss; /* Maximum segment size */
181 /* Data descriptor */
182 struct e1000_data_desc {
183 uint64_t buffer_addr; /* Address of the descriptor's buffer address */
187 uint16_t length; /* Data buffer length */
195 uint8_t status; /* Descriptor status */
196 uint8_t popts; /* Packet Options */
202 union e1000_tx_udesc {
203 struct e1000_tx_desc td;
204 struct e1000_context_desc cd;
205 struct e1000_data_desc dd;
208 /* Tx checksum info for a packet. */
210 int ck_valid; /* ck_info is valid */
211 uint8_t ck_start; /* start byte of cksum calcuation */
212 uint8_t ck_off; /* offset of cksum insertion */
213 uint16_t ck_len; /* length of cksum calc: 0 is to packet-end */
219 static int e82545_debug = 0;
220 #define DPRINTF(msg,params...) if (e82545_debug) fprintf(stderr, "e82545: " msg, params)
221 #define WPRINTF(msg,params...) fprintf(stderr, "e82545: " msg, params)
223 #define MIN(a,b) (((a)<(b))?(a):(b))
224 #define MAX(a,b) (((a)>(b))?(a):(b))
226 /* s/w representation of the RAL/RAH regs */
230 struct ether_addr eu_eth;
234 struct e82545_softc {
235 struct pci_devinst *esc_pi;
236 struct vmctx *esc_ctx;
237 struct mevent *esc_mevp;
238 struct mevent *esc_mevpitr;
239 pthread_mutex_t esc_mtx;
240 struct ether_addr esc_mac;
244 uint32_t esc_CTRL; /* x0000 device ctl */
245 uint32_t esc_FCAL; /* x0028 flow ctl addr lo */
246 uint32_t esc_FCAH; /* x002C flow ctl addr hi */
247 uint32_t esc_FCT; /* x0030 flow ctl type */
248 uint32_t esc_VET; /* x0038 VLAN eth type */
249 uint32_t esc_FCTTV; /* x0170 flow ctl tx timer */
250 uint32_t esc_LEDCTL; /* x0E00 LED control */
251 uint32_t esc_PBA; /* x1000 pkt buffer allocation */
253 /* Interrupt control */
254 int esc_irq_asserted;
255 uint32_t esc_ICR; /* x00C0 cause read/clear */
256 uint32_t esc_ITR; /* x00C4 intr throttling */
257 uint32_t esc_ICS; /* x00C8 cause set */
258 uint32_t esc_IMS; /* x00D0 mask set/read */
259 uint32_t esc_IMC; /* x00D8 mask clear */
262 union e1000_tx_udesc *esc_txdesc;
263 struct e1000_context_desc esc_txctx;
264 pthread_t esc_tx_tid;
265 pthread_cond_t esc_tx_cond;
268 uint32_t esc_TXCW; /* x0178 transmit config */
269 uint32_t esc_TCTL; /* x0400 transmit ctl */
270 uint32_t esc_TIPG; /* x0410 inter-packet gap */
271 uint16_t esc_AIT; /* x0458 Adaptive Interframe Throttle */
272 uint64_t esc_tdba; /* verified 64-bit desc table addr */
273 uint32_t esc_TDBAL; /* x3800 desc table addr, low bits */
274 uint32_t esc_TDBAH; /* x3804 desc table addr, hi 32-bits */
275 uint32_t esc_TDLEN; /* x3808 # descriptors in bytes */
276 uint16_t esc_TDH; /* x3810 desc table head idx */
277 uint16_t esc_TDHr; /* internal read version of TDH */
278 uint16_t esc_TDT; /* x3818 desc table tail idx */
279 uint32_t esc_TIDV; /* x3820 intr delay */
280 uint32_t esc_TXDCTL; /* x3828 desc control */
281 uint32_t esc_TADV; /* x382C intr absolute delay */
283 /* L2 frame acceptance */
284 struct eth_uni esc_uni[16]; /* 16 x unicast MAC addresses */
285 uint32_t esc_fmcast[128]; /* Multicast filter bit-match */
286 uint32_t esc_fvlan[128]; /* VLAN 4096-bit filter */
289 struct e1000_rx_desc *esc_rxdesc;
290 pthread_cond_t esc_rx_cond;
294 uint32_t esc_RCTL; /* x0100 receive ctl */
295 uint32_t esc_FCRTL; /* x2160 flow cntl thresh, low */
296 uint32_t esc_FCRTH; /* x2168 flow cntl thresh, hi */
297 uint64_t esc_rdba; /* verified 64-bit desc table addr */
298 uint32_t esc_RDBAL; /* x2800 desc table addr, low bits */
299 uint32_t esc_RDBAH; /* x2804 desc table addr, hi 32-bits*/
300 uint32_t esc_RDLEN; /* x2808 #descriptors */
301 uint16_t esc_RDH; /* x2810 desc table head idx */
302 uint16_t esc_RDT; /* x2818 desc table tail idx */
303 uint32_t esc_RDTR; /* x2820 intr delay */
304 uint32_t esc_RXDCTL; /* x2828 desc control */
305 uint32_t esc_RADV; /* x282C intr absolute delay */
306 uint32_t esc_RSRPD; /* x2C00 recv small packet detect */
307 uint32_t esc_RXCSUM; /* x5000 receive cksum ctl */
309 /* IO Port register access */
312 /* Shadow copy of MDIC */
313 uint32_t mdi_control;
314 /* Shadow copy of EECD */
315 uint32_t eeprom_control;
316 /* Latest NVM in/out */
320 uint32_t missed_pkt_count; /* dropped for no room in rx queue */
321 uint32_t pkt_rx_by_size[6];
322 uint32_t pkt_tx_by_size[6];
323 uint32_t good_pkt_rx_count;
324 uint32_t bcast_pkt_rx_count;
325 uint32_t mcast_pkt_rx_count;
326 uint32_t good_pkt_tx_count;
327 uint32_t bcast_pkt_tx_count;
328 uint32_t mcast_pkt_tx_count;
329 uint32_t oversize_rx_count;
330 uint32_t tso_tx_count;
331 uint64_t good_octets_rx;
332 uint64_t good_octets_tx;
333 uint64_t missed_octets; /* counts missed and oversized */
335 uint8_t nvm_bits:6; /* number of bits remaining in/out */
337 #define E82545_NVM_MODE_OPADDR 0x0
338 #define E82545_NVM_MODE_DATAIN 0x1
339 #define E82545_NVM_MODE_DATAOUT 0x2
341 uint16_t eeprom_data[E82545_NVM_EEPROM_SIZE];
344 static void e82545_reset(struct e82545_softc *sc, int dev);
345 static void e82545_rx_enable(struct e82545_softc *sc);
346 static void e82545_rx_disable(struct e82545_softc *sc);
347 static void e82545_tap_callback(int fd, enum ev_type type, void *param);
348 static void e82545_tx_start(struct e82545_softc *sc);
349 static void e82545_tx_enable(struct e82545_softc *sc);
350 static void e82545_tx_disable(struct e82545_softc *sc);
353 e82545_size_stat_index(uint32_t size)
357 } else if (size >= 1024) {
361 return (ffs(size) - 6);
366 e82545_init_eeprom(struct e82545_softc *sc)
368 uint16_t checksum, i;
371 sc->eeprom_data[NVM_MAC_ADDR] = ((uint16_t)sc->esc_mac.octet[0]) |
372 (((uint16_t)sc->esc_mac.octet[1]) << 8);
373 sc->eeprom_data[NVM_MAC_ADDR+1] = ((uint16_t)sc->esc_mac.octet[2]) |
374 (((uint16_t)sc->esc_mac.octet[3]) << 8);
375 sc->eeprom_data[NVM_MAC_ADDR+2] = ((uint16_t)sc->esc_mac.octet[4]) |
376 (((uint16_t)sc->esc_mac.octet[5]) << 8);
379 sc->eeprom_data[NVM_SUB_DEV_ID] = E82545_SUBDEV_ID;
380 sc->eeprom_data[NVM_SUB_VEN_ID] = E82545_VENDOR_ID_INTEL;
381 sc->eeprom_data[NVM_DEV_ID] = E82545_DEV_ID_82545EM_COPPER;
382 sc->eeprom_data[NVM_VEN_ID] = E82545_VENDOR_ID_INTEL;
384 /* fill in the checksum */
386 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
387 checksum += sc->eeprom_data[i];
389 checksum = NVM_SUM - checksum;
390 sc->eeprom_data[NVM_CHECKSUM_REG] = checksum;
391 DPRINTF("eeprom checksum: 0x%x\r\n", checksum);
395 e82545_write_mdi(struct e82545_softc *sc, uint8_t reg_addr,
396 uint8_t phy_addr, uint32_t data)
398 DPRINTF("Write mdi reg:0x%x phy:0x%x data: 0x%x\r\n", reg_addr, phy_addr, data);
402 e82545_read_mdi(struct e82545_softc *sc, uint8_t reg_addr,
405 //DPRINTF("Read mdi reg:0x%x phy:0x%x\r\n", reg_addr, phy_addr);
408 return (MII_SR_LINK_STATUS | MII_SR_AUTONEG_CAPS |
409 MII_SR_AUTONEG_COMPLETE);
410 case PHY_AUTONEG_ADV:
411 return NWAY_AR_SELECTOR_FIELD;
414 case PHY_1000T_STATUS:
415 return (SR_1000T_LP_FD_CAPS | SR_1000T_REMOTE_RX_STATUS |
416 SR_1000T_LOCAL_RX_STATUS);
418 return (M88E1011_I_PHY_ID >> 16) & 0xFFFF;
420 return (M88E1011_I_PHY_ID | E82545_REVISION_4) & 0xFFFF;
422 DPRINTF("Unknown mdi read reg:0x%x phy:0x%x\r\n", reg_addr, phy_addr);
429 e82545_eecd_strobe(struct e82545_softc *sc)
431 /* Microwire state machine */
433 DPRINTF("eeprom state machine srtobe "
434 "0x%x 0x%x 0x%x 0x%x\r\n",
435 sc->nvm_mode, sc->nvm_bits,
436 sc->nvm_opaddr, sc->nvm_data);*/
438 if (sc->nvm_bits == 0) {
439 DPRINTF("eeprom state machine not expecting data! "
440 "0x%x 0x%x 0x%x 0x%x\r\n",
441 sc->nvm_mode, sc->nvm_bits,
442 sc->nvm_opaddr, sc->nvm_data);
446 if (sc->nvm_mode == E82545_NVM_MODE_DATAOUT) {
448 if (sc->nvm_data & 0x8000) {
449 sc->eeprom_control |= E1000_EECD_DO;
451 sc->eeprom_control &= ~E1000_EECD_DO;
454 if (sc->nvm_bits == 0) {
455 /* read done, back to opcode mode. */
457 sc->nvm_mode = E82545_NVM_MODE_OPADDR;
458 sc->nvm_bits = E82545_NVM_OPADDR_BITS;
460 } else if (sc->nvm_mode == E82545_NVM_MODE_DATAIN) {
463 if (sc->eeprom_control & E1000_EECD_DI) {
466 if (sc->nvm_bits == 0) {
468 uint16_t op = sc->nvm_opaddr & E82545_NVM_OPCODE_MASK;
469 uint16_t addr = sc->nvm_opaddr & E82545_NVM_ADDR_MASK;
470 if (op != E82545_NVM_OPCODE_WRITE) {
471 DPRINTF("Illegal eeprom write op 0x%x\r\n",
473 } else if (addr >= E82545_NVM_EEPROM_SIZE) {
474 DPRINTF("Illegal eeprom write addr 0x%x\r\n",
477 DPRINTF("eeprom write eeprom[0x%x] = 0x%x\r\n",
479 sc->eeprom_data[addr] = sc->nvm_data;
481 /* back to opcode mode */
483 sc->nvm_mode = E82545_NVM_MODE_OPADDR;
484 sc->nvm_bits = E82545_NVM_OPADDR_BITS;
486 } else if (sc->nvm_mode == E82545_NVM_MODE_OPADDR) {
487 sc->nvm_opaddr <<= 1;
488 if (sc->eeprom_control & E1000_EECD_DI) {
491 if (sc->nvm_bits == 0) {
492 uint16_t op = sc->nvm_opaddr & E82545_NVM_OPCODE_MASK;
494 case E82545_NVM_OPCODE_EWEN:
495 DPRINTF("eeprom write enable: 0x%x\r\n",
497 /* back to opcode mode */
499 sc->nvm_mode = E82545_NVM_MODE_OPADDR;
500 sc->nvm_bits = E82545_NVM_OPADDR_BITS;
502 case E82545_NVM_OPCODE_READ:
504 uint16_t addr = sc->nvm_opaddr &
505 E82545_NVM_ADDR_MASK;
506 sc->nvm_mode = E82545_NVM_MODE_DATAOUT;
507 sc->nvm_bits = E82545_NVM_DATA_BITS;
508 if (addr < E82545_NVM_EEPROM_SIZE) {
509 sc->nvm_data = sc->eeprom_data[addr];
510 DPRINTF("eeprom read: eeprom[0x%x] = 0x%x\r\n",
513 DPRINTF("eeprom illegal read: 0x%x\r\n",
519 case E82545_NVM_OPCODE_WRITE:
520 sc->nvm_mode = E82545_NVM_MODE_DATAIN;
521 sc->nvm_bits = E82545_NVM_DATA_BITS;
525 DPRINTF("eeprom unknown op: 0x%x\r\r",
527 /* back to opcode mode */
529 sc->nvm_mode = E82545_NVM_MODE_OPADDR;
530 sc->nvm_bits = E82545_NVM_OPADDR_BITS;
534 DPRINTF("eeprom state machine wrong state! "
535 "0x%x 0x%x 0x%x 0x%x\r\n",
536 sc->nvm_mode, sc->nvm_bits,
537 sc->nvm_opaddr, sc->nvm_data);
542 e82545_itr_callback(int fd, enum ev_type type, void *param)
545 struct e82545_softc *sc = param;
547 pthread_mutex_lock(&sc->esc_mtx);
548 new = sc->esc_ICR & sc->esc_IMS;
549 if (new && !sc->esc_irq_asserted) {
550 DPRINTF("itr callback: lintr assert %x\r\n", new);
551 sc->esc_irq_asserted = 1;
552 pci_lintr_assert(sc->esc_pi);
554 mevent_delete(sc->esc_mevpitr);
555 sc->esc_mevpitr = NULL;
557 pthread_mutex_unlock(&sc->esc_mtx);
561 e82545_icr_assert(struct e82545_softc *sc, uint32_t bits)
565 DPRINTF("icr assert: 0x%x\r\n", bits);
568 * An interrupt is only generated if bits are set that
569 * aren't already in the ICR, these bits are unmasked,
570 * and there isn't an interrupt already pending.
572 new = bits & ~sc->esc_ICR & sc->esc_IMS;
576 DPRINTF("icr assert: masked %x, ims %x\r\n", new, sc->esc_IMS);
577 } else if (sc->esc_mevpitr != NULL) {
578 DPRINTF("icr assert: throttled %x, ims %x\r\n", new, sc->esc_IMS);
579 } else if (!sc->esc_irq_asserted) {
580 DPRINTF("icr assert: lintr assert %x\r\n", new);
581 sc->esc_irq_asserted = 1;
582 pci_lintr_assert(sc->esc_pi);
583 if (sc->esc_ITR != 0) {
584 sc->esc_mevpitr = mevent_add(
585 (sc->esc_ITR + 3905) / 3906, /* 256ns -> 1ms */
586 EVF_TIMER, e82545_itr_callback, sc);
592 e82545_ims_change(struct e82545_softc *sc, uint32_t bits)
597 * Changing the mask may allow previously asserted
598 * but masked interrupt requests to generate an interrupt.
600 new = bits & sc->esc_ICR & ~sc->esc_IMS;
604 DPRINTF("ims change: masked %x, ims %x\r\n", new, sc->esc_IMS);
605 } else if (sc->esc_mevpitr != NULL) {
606 DPRINTF("ims change: throttled %x, ims %x\r\n", new, sc->esc_IMS);
607 } else if (!sc->esc_irq_asserted) {
608 DPRINTF("ims change: lintr assert %x\n\r", new);
609 sc->esc_irq_asserted = 1;
610 pci_lintr_assert(sc->esc_pi);
611 if (sc->esc_ITR != 0) {
612 sc->esc_mevpitr = mevent_add(
613 (sc->esc_ITR + 3905) / 3906, /* 256ns -> 1ms */
614 EVF_TIMER, e82545_itr_callback, sc);
620 e82545_icr_deassert(struct e82545_softc *sc, uint32_t bits)
623 DPRINTF("icr deassert: 0x%x\r\n", bits);
624 sc->esc_ICR &= ~bits;
627 * If there are no longer any interrupt sources and there
628 * was an asserted interrupt, clear it
630 if (sc->esc_irq_asserted && !(sc->esc_ICR & sc->esc_IMS)) {
631 DPRINTF("icr deassert: lintr deassert %x\r\n", bits);
632 pci_lintr_deassert(sc->esc_pi);
633 sc->esc_irq_asserted = 0;
638 e82545_intr_write(struct e82545_softc *sc, uint32_t offset, uint32_t value)
641 DPRINTF("intr_write: off %x, val %x\n\r", offset, value);
645 e82545_icr_deassert(sc, value);
651 sc->esc_ICS = value; /* not used: store for debug */
652 e82545_icr_assert(sc, value);
655 e82545_ims_change(sc, value);
658 sc->esc_IMC = value; /* for debug */
659 sc->esc_IMS &= ~value;
660 // XXX clear interrupts if all ICR bits now masked
661 // and interrupt was pending ?
669 e82545_intr_read(struct e82545_softc *sc, uint32_t offset)
675 DPRINTF("intr_read: off %x\n\r", offset);
679 retval = sc->esc_ICR;
681 e82545_icr_deassert(sc, ~0);
684 retval = sc->esc_ITR;
687 /* write-only register */
690 retval = sc->esc_IMS;
693 /* write-only register */
703 e82545_devctl(struct e82545_softc *sc, uint32_t val)
706 sc->esc_CTRL = val & ~E1000_CTRL_RST;
708 if (val & E1000_CTRL_RST) {
709 DPRINTF("e1k: s/w reset, ctl %x\n", val);
712 /* XXX check for phy reset ? */
716 e82545_rx_update_rdba(struct e82545_softc *sc)
719 /* XXX verify desc base/len within phys mem range */
720 sc->esc_rdba = (uint64_t)sc->esc_RDBAH << 32 |
723 /* Cache host mapping of guest descriptor array */
724 sc->esc_rxdesc = paddr_guest2host(sc->esc_ctx,
725 sc->esc_rdba, sc->esc_RDLEN);
729 e82545_rx_ctl(struct e82545_softc *sc, uint32_t val)
733 on = ((val & E1000_RCTL_EN) == E1000_RCTL_EN);
735 /* Save RCTL after stripping reserved bits 31:27,24,21,14,11:10,0 */
736 sc->esc_RCTL = val & ~0xF9204c01;
738 DPRINTF("rx_ctl - %s RCTL %x, val %x\n",
739 on ? "on" : "off", sc->esc_RCTL, val);
741 /* state change requested */
742 if (on != sc->esc_rx_enabled) {
744 /* Catch disallowed/unimplemented settings */
745 //assert(!(val & E1000_RCTL_LBM_TCVR));
747 if (sc->esc_RCTL & E1000_RCTL_LBM_TCVR) {
748 sc->esc_rx_loopback = 1;
750 sc->esc_rx_loopback = 0;
753 e82545_rx_update_rdba(sc);
754 e82545_rx_enable(sc);
756 e82545_rx_disable(sc);
757 sc->esc_rx_loopback = 0;
759 sc->esc_rxdesc = NULL;
765 e82545_tx_update_tdba(struct e82545_softc *sc)
768 /* XXX verify desc base/len within phys mem range */
769 sc->esc_tdba = (uint64_t)sc->esc_TDBAH << 32 | sc->esc_TDBAL;
771 /* Cache host mapping of guest descriptor array */
772 sc->esc_txdesc = paddr_guest2host(sc->esc_ctx, sc->esc_tdba,
777 e82545_tx_ctl(struct e82545_softc *sc, uint32_t val)
781 on = ((val & E1000_TCTL_EN) == E1000_TCTL_EN);
783 /* ignore TCTL_EN settings that don't change state */
784 if (on == sc->esc_tx_enabled)
788 e82545_tx_update_tdba(sc);
789 e82545_tx_enable(sc);
791 e82545_tx_disable(sc);
793 sc->esc_txdesc = NULL;
796 /* Save TCTL value after stripping reserved bits 31:25,23,2,0 */
797 sc->esc_TCTL = val & ~0xFE800005;
801 e82545_bufsz(uint32_t rctl)
804 switch (rctl & (E1000_RCTL_BSEX | E1000_RCTL_SZ_256)) {
805 case (E1000_RCTL_SZ_2048): return (2048);
806 case (E1000_RCTL_SZ_1024): return (1024);
807 case (E1000_RCTL_SZ_512): return (512);
808 case (E1000_RCTL_SZ_256): return (256);
809 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_16384): return (16384);
810 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_8192): return (8192);
811 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_4096): return (4096);
813 return (256); /* Forbidden value. */
816 static uint8_t dummybuf[2048];
818 /* XXX one packet at a time until this is debugged */
820 e82545_tap_callback(int fd, enum ev_type type, void *param)
822 struct e82545_softc *sc = param;
823 struct e1000_rx_desc *rxd;
824 struct iovec vec[64];
825 int left, len, lim, maxpktsz, maxpktdesc, bufsz, i, n, size;
827 uint16_t *tp, tag, head;
829 pthread_mutex_lock(&sc->esc_mtx);
830 DPRINTF("rx_run: head %x, tail %x\r\n", sc->esc_RDH, sc->esc_RDT);
832 if (!sc->esc_rx_enabled || sc->esc_rx_loopback) {
833 DPRINTF("rx disabled (!%d || %d) -- packet(s) dropped\r\n",
834 sc->esc_rx_enabled, sc->esc_rx_loopback);
835 while (read(sc->esc_tapfd, dummybuf, sizeof(dummybuf)) > 0) {
839 bufsz = e82545_bufsz(sc->esc_RCTL);
840 maxpktsz = (sc->esc_RCTL & E1000_RCTL_LPE) ? 16384 : 1522;
841 maxpktdesc = (maxpktsz + bufsz - 1) / bufsz;
842 size = sc->esc_RDLEN / 16;
844 left = (size + sc->esc_RDT - head) % size;
845 if (left < maxpktdesc) {
846 DPRINTF("rx overflow (%d < %d) -- packet(s) dropped\r\n",
848 while (read(sc->esc_tapfd, dummybuf, sizeof(dummybuf)) > 0) {
853 sc->esc_rx_active = 1;
854 pthread_mutex_unlock(&sc->esc_mtx);
856 for (lim = size / 4; lim > 0 && left >= maxpktdesc; lim -= n) {
858 /* Grab rx descriptor pointed to by the head pointer */
859 for (i = 0; i < maxpktdesc; i++) {
860 rxd = &sc->esc_rxdesc[(head + i) % size];
861 vec[i].iov_base = paddr_guest2host(sc->esc_ctx,
862 rxd->buffer_addr, bufsz);
863 vec[i].iov_len = bufsz;
865 len = readv(sc->esc_tapfd, vec, maxpktdesc);
867 DPRINTF("tap: readv() returned %d\n", len);
872 * Adjust the packet length based on whether the CRC needs
873 * to be stripped or if the packet is less than the minimum
876 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
877 len = ETHER_MIN_LEN - ETHER_CRC_LEN;
878 if (!(sc->esc_RCTL & E1000_RCTL_SECRC))
879 len += ETHER_CRC_LEN;
880 n = (len + bufsz - 1) / bufsz;
882 DPRINTF("packet read %d bytes, %d segs, head %d\r\n",
885 /* Apply VLAN filter. */
886 tp = (uint16_t *)vec[0].iov_base + 6;
887 if ((sc->esc_RCTL & E1000_RCTL_VFE) &&
888 (ntohs(tp[0]) == sc->esc_VET)) {
889 tag = ntohs(tp[1]) & 0x0fff;
890 if ((sc->esc_fvlan[tag >> 5] &
891 (1 << (tag & 0x1f))) != 0) {
892 DPRINTF("known VLAN %d\r\n", tag);
894 DPRINTF("unknown VLAN %d\r\n", tag);
900 /* Update all consumed descriptors. */
901 for (i = 0; i < n - 1; i++) {
902 rxd = &sc->esc_rxdesc[(head + i) % size];
907 rxd->status = E1000_RXD_STAT_DD;
909 rxd = &sc->esc_rxdesc[(head + i) % size];
910 rxd->length = len % bufsz;
914 /* XXX signal no checksum for now */
915 rxd->status = E1000_RXD_STAT_PIF | E1000_RXD_STAT_IXSM |
916 E1000_RXD_STAT_EOP | E1000_RXD_STAT_DD;
918 /* Schedule receive interrupts. */
919 if (len <= sc->esc_RSRPD) {
920 cause |= E1000_ICR_SRPD | E1000_ICR_RXT0;
922 /* XXX: RDRT and RADV timers should be here. */
923 cause |= E1000_ICR_RXT0;
926 head = (head + n) % size;
931 pthread_mutex_lock(&sc->esc_mtx);
932 sc->esc_rx_active = 0;
933 if (sc->esc_rx_enabled == 0)
934 pthread_cond_signal(&sc->esc_rx_cond);
937 /* Respect E1000_RCTL_RDMTS */
938 left = (size + sc->esc_RDT - head) % size;
939 if (left < (size >> (((sc->esc_RCTL >> 8) & 3) + 1)))
940 cause |= E1000_ICR_RXDMT0;
941 /* Assert all accumulated interrupts. */
943 e82545_icr_assert(sc, cause);
945 DPRINTF("rx_run done: head %x, tail %x\r\n", sc->esc_RDH, sc->esc_RDT);
946 pthread_mutex_unlock(&sc->esc_mtx);
950 e82545_carry(uint32_t sum)
953 sum = (sum & 0xFFFF) + (sum >> 16);
960 e82545_buf_checksum(uint8_t *buf, int len)
965 /* Checksum all the pairs of bytes first... */
966 for (i = 0; i < (len & ~1U); i += 2)
967 sum += *((u_int16_t *)(buf + i));
970 * If there's a single byte left over, checksum it, too.
971 * Network byte order is big-endian, so the remaining byte is
975 sum += htons(buf[i] << 8);
977 return (e82545_carry(sum));
981 e82545_iov_checksum(struct iovec *iov, int iovcnt, int off, int len)
986 /* Skip completely unneeded vectors. */
987 while (iovcnt > 0 && iov->iov_len <= off && off > 0) {
993 /* Calculate checksum of requested range. */
995 while (len > 0 && iovcnt > 0) {
996 now = MIN(len, iov->iov_len - off);
997 s = e82545_buf_checksum(iov->iov_base + off, now);
998 sum += odd ? (s << 8) : s;
1006 return (e82545_carry(sum));
1010 * Return the transmit descriptor type.
1013 e82545_txdesc_type(uint32_t lower)
1019 if (lower & E1000_TXD_CMD_DEXT)
1020 type = lower & E1000_TXD_MASK;
1026 e82545_transmit_checksum(struct iovec *iov, int iovcnt, struct ck_info *ck)
1031 DPRINTF("tx cksum: iovcnt/s/off/len %d/%d/%d/%d\r\n",
1032 iovcnt, ck->ck_start, ck->ck_off, ck->ck_len);
1033 cklen = ck->ck_len ? ck->ck_len - ck->ck_start + 1 : INT_MAX;
1034 cksum = e82545_iov_checksum(iov, iovcnt, ck->ck_start, cklen);
1035 *(uint16_t *)((uint8_t *)iov[0].iov_base + ck->ck_off) = ~cksum;
1039 e82545_transmit_backend(struct e82545_softc *sc, struct iovec *iov, int iovcnt)
1042 if (sc->esc_tapfd == -1)
1045 (void) writev(sc->esc_tapfd, iov, iovcnt);
1049 e82545_transmit_done(struct e82545_softc *sc, uint16_t head, uint16_t tail,
1050 uint16_t dsize, int *tdwb)
1052 union e1000_tx_udesc *dsc;
1054 for ( ; head != tail; head = (head + 1) % dsize) {
1055 dsc = &sc->esc_txdesc[head];
1056 if (dsc->td.lower.data & E1000_TXD_CMD_RS) {
1057 dsc->td.upper.data |= E1000_TXD_STAT_DD;
1064 e82545_transmit(struct e82545_softc *sc, uint16_t head, uint16_t tail,
1065 uint16_t dsize, uint16_t *rhead, int *tdwb)
1067 uint8_t *hdr, *hdrp;
1068 struct iovec iovb[I82545_MAX_TXSEGS + 2];
1069 struct iovec tiov[I82545_MAX_TXSEGS + 2];
1070 struct e1000_context_desc *cd;
1071 struct ck_info ckinfo[2];
1073 union e1000_tx_udesc *dsc;
1074 int desc, dtype, len, ntype, iovcnt, tlen, hdrlen, vlen, tcp, tso;
1075 int mss, paylen, seg, tiovcnt, left, now, nleft, nnow, pv, pvoff;
1076 uint32_t tcpsum, tcpseq;
1077 uint16_t ipcs, tcpcs, ipid, ohead;
1079 ckinfo[0].ck_valid = ckinfo[1].ck_valid = 0;
1086 /* iovb[0/1] may be used for writable copy of headers. */
1089 for (desc = 0; ; desc++, head = (head + 1) % dsize) {
1094 dsc = &sc->esc_txdesc[head];
1095 dtype = e82545_txdesc_type(dsc->td.lower.data);
1099 case E1000_TXD_TYP_C:
1100 DPRINTF("tx ctxt desc idx %d: %016jx "
1102 head, dsc->td.buffer_addr,
1103 dsc->td.upper.data, dsc->td.lower.data);
1104 /* Save context and return */
1105 sc->esc_txctx = dsc->cd;
1107 case E1000_TXD_TYP_L:
1108 DPRINTF("tx legacy desc idx %d: %08x%08x\r\n",
1109 head, dsc->td.upper.data, dsc->td.lower.data);
1111 * legacy cksum start valid in first descriptor
1114 ckinfo[0].ck_start = dsc->td.upper.fields.css;
1116 case E1000_TXD_TYP_D:
1117 DPRINTF("tx data desc idx %d: %08x%08x\r\n",
1118 head, dsc->td.upper.data, dsc->td.lower.data);
1125 /* Descriptor type must be consistent */
1126 assert(dtype == ntype);
1127 DPRINTF("tx next desc idx %d: %08x%08x\r\n",
1128 head, dsc->td.upper.data, dsc->td.lower.data);
1131 len = (dtype == E1000_TXD_TYP_L) ? dsc->td.lower.flags.length :
1132 dsc->dd.lower.data & 0xFFFFF;
1135 /* Strip checksum supplied by guest. */
1136 if ((dsc->td.lower.data & E1000_TXD_CMD_EOP) != 0 &&
1137 (dsc->td.lower.data & E1000_TXD_CMD_IFCS) == 0)
1140 if (iovcnt < I82545_MAX_TXSEGS) {
1141 iov[iovcnt].iov_base = paddr_guest2host(
1142 sc->esc_ctx, dsc->td.buffer_addr, len);
1143 iov[iovcnt].iov_len = len;
1149 * Pull out info that is valid in the final descriptor
1150 * and exit descriptor loop.
1152 if (dsc->td.lower.data & E1000_TXD_CMD_EOP) {
1153 if (dtype == E1000_TXD_TYP_L) {
1154 if (dsc->td.lower.data & E1000_TXD_CMD_IC) {
1155 ckinfo[0].ck_valid = 1;
1157 dsc->td.lower.flags.cso;
1158 ckinfo[0].ck_len = 0;
1161 cd = &sc->esc_txctx;
1162 if (dsc->dd.lower.data & E1000_TXD_CMD_TSE)
1164 if (dsc->dd.upper.fields.popts &
1165 E1000_TXD_POPTS_IXSM)
1166 ckinfo[0].ck_valid = 1;
1167 if (dsc->dd.upper.fields.popts &
1168 E1000_TXD_POPTS_IXSM || tso) {
1169 ckinfo[0].ck_start =
1170 cd->lower_setup.ip_fields.ipcss;
1172 cd->lower_setup.ip_fields.ipcso;
1174 cd->lower_setup.ip_fields.ipcse;
1176 if (dsc->dd.upper.fields.popts &
1177 E1000_TXD_POPTS_TXSM)
1178 ckinfo[1].ck_valid = 1;
1179 if (dsc->dd.upper.fields.popts &
1180 E1000_TXD_POPTS_TXSM || tso) {
1181 ckinfo[1].ck_start =
1182 cd->upper_setup.tcp_fields.tucss;
1184 cd->upper_setup.tcp_fields.tucso;
1186 cd->upper_setup.tcp_fields.tucse;
1193 if (iovcnt > I82545_MAX_TXSEGS) {
1194 WPRINTF("tx too many descriptors (%d > %d) -- dropped\r\n",
1195 iovcnt, I82545_MAX_TXSEGS);
1200 /* Estimate writable space for VLAN header insertion. */
1201 if ((sc->esc_CTRL & E1000_CTRL_VME) &&
1202 (dsc->td.lower.data & E1000_TXD_CMD_VLE)) {
1203 hdrlen = ETHER_ADDR_LEN*2;
1204 vlen = ETHER_VLAN_ENCAP_LEN;
1207 /* Estimate required writable space for checksums. */
1208 if (ckinfo[0].ck_valid)
1209 hdrlen = MAX(hdrlen, ckinfo[0].ck_off + 2);
1210 if (ckinfo[1].ck_valid)
1211 hdrlen = MAX(hdrlen, ckinfo[1].ck_off + 2);
1212 /* Round up writable space to the first vector. */
1213 if (hdrlen != 0 && iov[0].iov_len > hdrlen &&
1214 iov[0].iov_len < hdrlen + 100)
1215 hdrlen = iov[0].iov_len;
1217 /* In case of TSO header length provided by software. */
1218 hdrlen = sc->esc_txctx.tcp_seg_setup.fields.hdr_len;
1221 /* Allocate, fill and prepend writable header vector. */
1223 hdr = __builtin_alloca(hdrlen + vlen);
1225 for (left = hdrlen, hdrp = hdr; left > 0;
1226 left -= now, hdrp += now) {
1227 now = MIN(left, iov->iov_len);
1228 memcpy(hdrp, iov->iov_base, now);
1229 iov->iov_base += now;
1230 iov->iov_len -= now;
1231 if (iov->iov_len == 0) {
1238 iov->iov_base = hdr;
1239 iov->iov_len = hdrlen;
1242 /* Insert VLAN tag. */
1244 hdr -= ETHER_VLAN_ENCAP_LEN;
1245 memmove(hdr, hdr + ETHER_VLAN_ENCAP_LEN, ETHER_ADDR_LEN*2);
1246 hdrlen += ETHER_VLAN_ENCAP_LEN;
1247 hdr[ETHER_ADDR_LEN*2 + 0] = sc->esc_VET >> 8;
1248 hdr[ETHER_ADDR_LEN*2 + 1] = sc->esc_VET & 0xff;
1249 hdr[ETHER_ADDR_LEN*2 + 2] = dsc->td.upper.fields.special >> 8;
1250 hdr[ETHER_ADDR_LEN*2 + 3] = dsc->td.upper.fields.special & 0xff;
1251 iov->iov_base = hdr;
1252 iov->iov_len += ETHER_VLAN_ENCAP_LEN;
1253 /* Correct checksum offsets after VLAN tag insertion. */
1254 ckinfo[0].ck_start += ETHER_VLAN_ENCAP_LEN;
1255 ckinfo[0].ck_off += ETHER_VLAN_ENCAP_LEN;
1256 if (ckinfo[0].ck_len != 0)
1257 ckinfo[0].ck_len += ETHER_VLAN_ENCAP_LEN;
1258 ckinfo[1].ck_start += ETHER_VLAN_ENCAP_LEN;
1259 ckinfo[1].ck_off += ETHER_VLAN_ENCAP_LEN;
1260 if (ckinfo[1].ck_len != 0)
1261 ckinfo[1].ck_len += ETHER_VLAN_ENCAP_LEN;
1264 /* Simple non-TSO case. */
1266 /* Calculate checksums and transmit. */
1267 if (ckinfo[0].ck_valid)
1268 e82545_transmit_checksum(iov, iovcnt, &ckinfo[0]);
1269 if (ckinfo[1].ck_valid)
1270 e82545_transmit_checksum(iov, iovcnt, &ckinfo[1]);
1271 e82545_transmit_backend(sc, iov, iovcnt);
1276 tcp = (sc->esc_txctx.cmd_and_length & E1000_TXD_CMD_TCP) != 0;
1277 mss = sc->esc_txctx.tcp_seg_setup.fields.mss;
1278 paylen = (sc->esc_txctx.cmd_and_length & 0x000fffff);
1279 DPRINTF("tx %s segmentation offload %d+%d/%d bytes %d iovs\r\n",
1280 tcp ? "TCP" : "UDP", hdrlen, paylen, mss, iovcnt);
1281 ipid = ntohs(*(uint16_t *)&hdr[ckinfo[0].ck_start + 4]);
1282 tcpseq = ntohl(*(uint32_t *)&hdr[ckinfo[1].ck_start + 4]);
1283 ipcs = *(uint16_t *)&hdr[ckinfo[0].ck_off];
1285 if (ckinfo[1].ck_valid) /* Save partial pseudo-header checksum. */
1286 tcpcs = *(uint16_t *)&hdr[ckinfo[1].ck_off];
1289 for (seg = 0, left = paylen; left > 0; seg++, left -= now) {
1290 now = MIN(left, mss);
1292 /* Construct IOVs for the segment. */
1293 /* Include whole original header. */
1294 tiov[0].iov_base = hdr;
1295 tiov[0].iov_len = hdrlen;
1297 /* Include respective part of payload IOV. */
1298 for (nleft = now; pv < iovcnt && nleft > 0; nleft -= nnow) {
1299 nnow = MIN(nleft, iov[pv].iov_len - pvoff);
1300 tiov[tiovcnt].iov_base = iov[pv].iov_base + pvoff;
1301 tiov[tiovcnt++].iov_len = nnow;
1302 if (pvoff + nnow == iov[pv].iov_len) {
1308 DPRINTF("tx segment %d %d+%d bytes %d iovs\r\n",
1309 seg, hdrlen, now, tiovcnt);
1311 /* Update IP header. */
1312 if (sc->esc_txctx.cmd_and_length & E1000_TXD_CMD_IP) {
1313 /* IPv4 -- set length and ID */
1314 *(uint16_t *)&hdr[ckinfo[0].ck_start + 2] =
1315 htons(hdrlen - ckinfo[0].ck_start + now);
1316 *(uint16_t *)&hdr[ckinfo[0].ck_start + 4] =
1319 /* IPv6 -- set length */
1320 *(uint16_t *)&hdr[ckinfo[0].ck_start + 4] =
1321 htons(hdrlen - ckinfo[0].ck_start - 40 +
1325 /* Update pseudo-header checksum. */
1327 tcpsum += htons(hdrlen - ckinfo[1].ck_start + now);
1329 /* Update TCP/UDP headers. */
1331 /* Update sequence number and FIN/PUSH flags. */
1332 *(uint32_t *)&hdr[ckinfo[1].ck_start + 4] =
1333 htonl(tcpseq + paylen - left);
1335 hdr[ckinfo[1].ck_start + 13] &=
1336 ~(TH_FIN | TH_PUSH);
1339 /* Update payload length. */
1340 *(uint32_t *)&hdr[ckinfo[1].ck_start + 4] =
1341 hdrlen - ckinfo[1].ck_start + now;
1344 /* Calculate checksums and transmit. */
1345 if (ckinfo[0].ck_valid) {
1346 *(uint16_t *)&hdr[ckinfo[0].ck_off] = ipcs;
1347 e82545_transmit_checksum(tiov, tiovcnt, &ckinfo[0]);
1349 if (ckinfo[1].ck_valid) {
1350 *(uint16_t *)&hdr[ckinfo[1].ck_off] =
1351 e82545_carry(tcpsum);
1352 e82545_transmit_checksum(tiov, tiovcnt, &ckinfo[1]);
1354 e82545_transmit_backend(sc, tiov, tiovcnt);
1358 head = (head + 1) % dsize;
1359 e82545_transmit_done(sc, ohead, head, dsize, tdwb);
1366 e82545_tx_run(struct e82545_softc *sc)
1369 uint16_t head, rhead, tail, size;
1370 int lim, tdwb, sent;
1374 size = sc->esc_TDLEN / 16;
1375 DPRINTF("tx_run: head %x, rhead %x, tail %x\r\n",
1376 sc->esc_TDH, sc->esc_TDHr, sc->esc_TDT);
1378 pthread_mutex_unlock(&sc->esc_mtx);
1381 for (lim = size / 4; sc->esc_tx_enabled && lim > 0; lim -= sent) {
1382 sent = e82545_transmit(sc, head, tail, size, &rhead, &tdwb);
1387 pthread_mutex_lock(&sc->esc_mtx);
1390 sc->esc_TDHr = rhead;
1393 cause |= E1000_ICR_TXDW;
1394 if (lim != size / 4 && sc->esc_TDH == sc->esc_TDT)
1395 cause |= E1000_ICR_TXQE;
1397 e82545_icr_assert(sc, cause);
1399 DPRINTF("tx_run done: head %x, rhead %x, tail %x\r\n",
1400 sc->esc_TDH, sc->esc_TDHr, sc->esc_TDT);
1404 e82545_tx_thread(void *param)
1406 struct e82545_softc *sc = param;
1408 pthread_mutex_lock(&sc->esc_mtx);
1410 while (!sc->esc_tx_enabled || sc->esc_TDHr == sc->esc_TDT) {
1411 if (sc->esc_tx_enabled && sc->esc_TDHr != sc->esc_TDT)
1413 sc->esc_tx_active = 0;
1414 if (sc->esc_tx_enabled == 0)
1415 pthread_cond_signal(&sc->esc_tx_cond);
1416 pthread_cond_wait(&sc->esc_tx_cond, &sc->esc_mtx);
1418 sc->esc_tx_active = 1;
1420 /* Process some tx descriptors. Lock dropped inside. */
1426 e82545_tx_start(struct e82545_softc *sc)
1429 if (sc->esc_tx_active == 0)
1430 pthread_cond_signal(&sc->esc_tx_cond);
1434 e82545_tx_enable(struct e82545_softc *sc)
1437 sc->esc_tx_enabled = 1;
1441 e82545_tx_disable(struct e82545_softc *sc)
1444 sc->esc_tx_enabled = 0;
1445 while (sc->esc_tx_active)
1446 pthread_cond_wait(&sc->esc_tx_cond, &sc->esc_mtx);
1450 e82545_rx_enable(struct e82545_softc *sc)
1453 sc->esc_rx_enabled = 1;
1457 e82545_rx_disable(struct e82545_softc *sc)
1460 sc->esc_rx_enabled = 0;
1461 while (sc->esc_rx_active)
1462 pthread_cond_wait(&sc->esc_rx_cond, &sc->esc_mtx);
1466 e82545_write_ra(struct e82545_softc *sc, int reg, uint32_t wval)
1474 eu = &sc->esc_uni[idx];
1478 eu->eu_valid = ((wval & E1000_RAH_AV) == E1000_RAH_AV);
1479 eu->eu_addrsel = (wval >> 16) & 0x3;
1480 eu->eu_eth.octet[5] = wval >> 8;
1481 eu->eu_eth.octet[4] = wval;
1484 eu->eu_eth.octet[3] = wval >> 24;
1485 eu->eu_eth.octet[2] = wval >> 16;
1486 eu->eu_eth.octet[1] = wval >> 8;
1487 eu->eu_eth.octet[0] = wval;
1492 e82545_read_ra(struct e82545_softc *sc, int reg)
1501 eu = &sc->esc_uni[idx];
1505 retval = (eu->eu_valid << 31) |
1506 (eu->eu_addrsel << 16) |
1507 (eu->eu_eth.octet[5] << 8) |
1508 eu->eu_eth.octet[4];
1511 retval = (eu->eu_eth.octet[3] << 24) |
1512 (eu->eu_eth.octet[2] << 16) |
1513 (eu->eu_eth.octet[1] << 8) |
1514 eu->eu_eth.octet[0];
1521 e82545_write_register(struct e82545_softc *sc, uint32_t offset, uint32_t value)
1526 DPRINTF("Unaligned register write offset:0x%x value:0x%x\r\n", offset, value);
1529 DPRINTF("Register write: 0x%x value: 0x%x\r\n", offset, value);
1533 case E1000_CTRL_DUP:
1534 e82545_devctl(sc, value);
1537 sc->esc_FCAL = value;
1540 sc->esc_FCAH = value & ~0xFFFF0000;
1543 sc->esc_FCT = value & ~0xFFFF0000;
1546 sc->esc_VET = value & ~0xFFFF0000;
1549 sc->esc_FCTTV = value & ~0xFFFF0000;
1552 sc->esc_LEDCTL = value & ~0x30303000;
1555 sc->esc_PBA = value & 0x0000FF80;
1562 e82545_intr_write(sc, offset, value);
1565 e82545_rx_ctl(sc, value);
1568 sc->esc_FCRTL = value & ~0xFFFF0007;
1571 sc->esc_FCRTH = value & ~0xFFFF0007;
1573 case E1000_RDBAL(0):
1574 sc->esc_RDBAL = value & ~0xF;
1575 if (sc->esc_rx_enabled) {
1576 /* Apparently legal: update cached address */
1577 e82545_rx_update_rdba(sc);
1580 case E1000_RDBAH(0):
1581 assert(!sc->esc_rx_enabled);
1582 sc->esc_RDBAH = value;
1584 case E1000_RDLEN(0):
1585 assert(!sc->esc_rx_enabled);
1586 sc->esc_RDLEN = value & ~0xFFF0007F;
1589 /* XXX should only ever be zero ? Range check ? */
1590 sc->esc_RDH = value;
1593 /* XXX if this opens up the rx ring, do something ? */
1594 sc->esc_RDT = value;
1597 /* ignore FPD bit 31 */
1598 sc->esc_RDTR = value & ~0xFFFF0000;
1600 case E1000_RXDCTL(0):
1601 sc->esc_RXDCTL = value & ~0xFEC0C0C0;
1604 sc->esc_RADV = value & ~0xFFFF0000;
1607 sc->esc_RSRPD = value & ~0xFFFFF000;
1610 sc->esc_RXCSUM = value & ~0xFFFFF800;
1613 sc->esc_TXCW = value & ~0x3FFF0000;
1616 e82545_tx_ctl(sc, value);
1619 sc->esc_TIPG = value;
1622 sc->esc_AIT = value;
1624 case E1000_TDBAL(0):
1625 sc->esc_TDBAL = value & ~0xF;
1626 if (sc->esc_tx_enabled) {
1627 /* Apparently legal */
1628 e82545_tx_update_tdba(sc);
1631 case E1000_TDBAH(0):
1632 //assert(!sc->esc_tx_enabled);
1633 sc->esc_TDBAH = value;
1635 case E1000_TDLEN(0):
1636 //assert(!sc->esc_tx_enabled);
1637 sc->esc_TDLEN = value & ~0xFFF0007F;
1640 //assert(!sc->esc_tx_enabled);
1641 /* XXX should only ever be zero ? Range check ? */
1642 sc->esc_TDHr = sc->esc_TDH = value;
1645 /* XXX range check ? */
1646 sc->esc_TDT = value;
1647 if (sc->esc_tx_enabled)
1648 e82545_tx_start(sc);
1651 sc->esc_TIDV = value & ~0xFFFF0000;
1653 case E1000_TXDCTL(0):
1654 //assert(!sc->esc_tx_enabled);
1655 sc->esc_TXDCTL = value & ~0xC0C0C0;
1658 sc->esc_TADV = value & ~0xFFFF0000;
1660 case E1000_RAL(0) ... E1000_RAH(15):
1661 /* convert to u32 offset */
1662 ridx = (offset - E1000_RAL(0)) >> 2;
1663 e82545_write_ra(sc, ridx, value);
1665 case E1000_MTA ... (E1000_MTA + (127*4)):
1666 sc->esc_fmcast[(offset - E1000_MTA) >> 2] = value;
1668 case E1000_VFTA ... (E1000_VFTA + (127*4)):
1669 sc->esc_fvlan[(offset - E1000_VFTA) >> 2] = value;
1673 //DPRINTF("EECD write 0x%x -> 0x%x\r\n", sc->eeprom_control, value);
1674 /* edge triggered low->high */
1675 uint32_t eecd_strobe = ((sc->eeprom_control & E1000_EECD_SK) ?
1676 0 : (value & E1000_EECD_SK));
1677 uint32_t eecd_mask = (E1000_EECD_SK|E1000_EECD_CS|
1678 E1000_EECD_DI|E1000_EECD_REQ);
1679 sc->eeprom_control &= ~eecd_mask;
1680 sc->eeprom_control |= (value & eecd_mask);
1681 /* grant/revoke immediately */
1682 if (value & E1000_EECD_REQ) {
1683 sc->eeprom_control |= E1000_EECD_GNT;
1685 sc->eeprom_control &= ~E1000_EECD_GNT;
1687 if (eecd_strobe && (sc->eeprom_control & E1000_EECD_CS)) {
1688 e82545_eecd_strobe(sc);
1694 uint8_t reg_addr = (uint8_t)((value & E1000_MDIC_REG_MASK) >>
1695 E1000_MDIC_REG_SHIFT);
1696 uint8_t phy_addr = (uint8_t)((value & E1000_MDIC_PHY_MASK) >>
1697 E1000_MDIC_PHY_SHIFT);
1699 (value & ~(E1000_MDIC_ERROR|E1000_MDIC_DEST));
1700 if ((value & E1000_MDIC_READY) != 0) {
1701 DPRINTF("Incorrect MDIC ready bit: 0x%x\r\n", value);
1704 switch (value & E82545_MDIC_OP_MASK) {
1705 case E1000_MDIC_OP_READ:
1706 sc->mdi_control &= ~E82545_MDIC_DATA_MASK;
1707 sc->mdi_control |= e82545_read_mdi(sc, reg_addr, phy_addr);
1709 case E1000_MDIC_OP_WRITE:
1710 e82545_write_mdi(sc, reg_addr, phy_addr,
1711 value & E82545_MDIC_DATA_MASK);
1714 DPRINTF("Unknown MDIC op: 0x%x\r\n", value);
1717 /* TODO: barrier? */
1718 sc->mdi_control |= E1000_MDIC_READY;
1719 if (value & E82545_MDIC_IE) {
1720 // TODO: generate interrupt
1728 DPRINTF("Unknown write register: 0x%x value:%x\r\n", offset, value);
1734 e82545_read_register(struct e82545_softc *sc, uint32_t offset)
1740 DPRINTF("Unaligned register read offset:0x%x\r\n", offset);
1744 DPRINTF("Register read: 0x%x\r\n", offset);
1748 retval = sc->esc_CTRL;
1751 retval = E1000_STATUS_FD | E1000_STATUS_LU |
1752 E1000_STATUS_SPEED_1000;
1755 retval = sc->esc_FCAL;
1758 retval = sc->esc_FCAH;
1761 retval = sc->esc_FCT;
1764 retval = sc->esc_VET;
1767 retval = sc->esc_FCTTV;
1770 retval = sc->esc_LEDCTL;
1773 retval = sc->esc_PBA;
1780 retval = e82545_intr_read(sc, offset);
1783 retval = sc->esc_RCTL;
1786 retval = sc->esc_FCRTL;
1789 retval = sc->esc_FCRTH;
1791 case E1000_RDBAL(0):
1792 retval = sc->esc_RDBAL;
1794 case E1000_RDBAH(0):
1795 retval = sc->esc_RDBAH;
1797 case E1000_RDLEN(0):
1798 retval = sc->esc_RDLEN;
1801 retval = sc->esc_RDH;
1804 retval = sc->esc_RDT;
1807 retval = sc->esc_RDTR;
1809 case E1000_RXDCTL(0):
1810 retval = sc->esc_RXDCTL;
1813 retval = sc->esc_RADV;
1816 retval = sc->esc_RSRPD;
1819 retval = sc->esc_RXCSUM;
1822 retval = sc->esc_TXCW;
1825 retval = sc->esc_TCTL;
1828 retval = sc->esc_TIPG;
1831 retval = sc->esc_AIT;
1833 case E1000_TDBAL(0):
1834 retval = sc->esc_TDBAL;
1836 case E1000_TDBAH(0):
1837 retval = sc->esc_TDBAH;
1839 case E1000_TDLEN(0):
1840 retval = sc->esc_TDLEN;
1843 retval = sc->esc_TDH;
1846 retval = sc->esc_TDT;
1849 retval = sc->esc_TIDV;
1851 case E1000_TXDCTL(0):
1852 retval = sc->esc_TXDCTL;
1855 retval = sc->esc_TADV;
1857 case E1000_RAL(0) ... E1000_RAH(15):
1858 /* convert to u32 offset */
1859 ridx = (offset - E1000_RAL(0)) >> 2;
1860 retval = e82545_read_ra(sc, ridx);
1862 case E1000_MTA ... (E1000_MTA + (127*4)):
1863 retval = sc->esc_fmcast[(offset - E1000_MTA) >> 2];
1865 case E1000_VFTA ... (E1000_VFTA + (127*4)):
1866 retval = sc->esc_fvlan[(offset - E1000_VFTA) >> 2];
1869 //DPRINTF("EECD read %x\r\n", sc->eeprom_control);
1870 retval = sc->eeprom_control;
1873 retval = sc->mdi_control;
1878 /* stats that we emulate. */
1880 retval = sc->missed_pkt_count;
1883 retval = sc->pkt_rx_by_size[0];
1886 retval = sc->pkt_rx_by_size[1];
1889 retval = sc->pkt_rx_by_size[2];
1892 retval = sc->pkt_rx_by_size[3];
1895 retval = sc->pkt_rx_by_size[4];
1898 retval = sc->pkt_rx_by_size[5];
1901 retval = sc->good_pkt_rx_count;
1904 retval = sc->bcast_pkt_rx_count;
1907 retval = sc->mcast_pkt_rx_count;
1911 retval = sc->good_pkt_tx_count;
1914 retval = (uint32_t)sc->good_octets_rx;
1917 retval = (uint32_t)(sc->good_octets_rx >> 32);
1921 retval = (uint32_t)sc->good_octets_tx;
1925 retval = (uint32_t)(sc->good_octets_tx >> 32);
1928 retval = sc->oversize_rx_count;
1931 retval = (uint32_t)(sc->good_octets_rx + sc->missed_octets);
1934 retval = (uint32_t)((sc->good_octets_rx +
1935 sc->missed_octets) >> 32);
1938 retval = sc->good_pkt_rx_count + sc->missed_pkt_count +
1939 sc->oversize_rx_count;
1942 retval = sc->pkt_tx_by_size[0];
1945 retval = sc->pkt_tx_by_size[1];
1948 retval = sc->pkt_tx_by_size[2];
1951 retval = sc->pkt_tx_by_size[3];
1954 retval = sc->pkt_tx_by_size[4];
1957 retval = sc->pkt_tx_by_size[5];
1960 retval = sc->mcast_pkt_tx_count;
1963 retval = sc->bcast_pkt_tx_count;
1966 retval = sc->tso_tx_count;
1968 /* stats that are always 0. */
1970 case E1000_ALGNERRC:
1999 DPRINTF("Unknown read register: 0x%x\r\n", offset);
2008 e82545_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
2009 uint64_t offset, int size, uint64_t value)
2011 struct e82545_softc *sc;
2013 //DPRINTF("Write bar:%d offset:0x%lx value:0x%lx size:%d\r\n", baridx, offset, value, size);
2017 pthread_mutex_lock(&sc->esc_mtx);
2024 DPRINTF("Wrong io addr write sz:%d value:0x%lx\r\n", size, value);
2026 sc->io_addr = (uint32_t)value;
2030 DPRINTF("Wrong io data write size:%d value:0x%lx\r\n", size, value);
2031 } else if (sc->io_addr > E82545_IO_REGISTER_MAX) {
2032 DPRINTF("Non-register io write addr:0x%x value:0x%lx\r\n", sc->io_addr, value);
2034 e82545_write_register(sc, sc->io_addr,
2038 DPRINTF("Unknown io bar write offset:0x%lx value:0x%lx size:%d\r\n", offset, value, size);
2042 case E82545_BAR_REGISTER:
2044 DPRINTF("Wrong register write size:%d offset:0x%lx value:0x%lx\r\n", size, offset, value);
2046 e82545_write_register(sc, (uint32_t)offset,
2050 DPRINTF("Unknown write bar:%d off:0x%lx val:0x%lx size:%d\r\n",
2051 baridx, offset, value, size);
2054 pthread_mutex_unlock(&sc->esc_mtx);
2058 e82545_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
2059 uint64_t offset, int size)
2061 struct e82545_softc *sc;
2064 //DPRINTF("Read bar:%d offset:0x%lx size:%d\r\n", baridx, offset, size);
2068 pthread_mutex_lock(&sc->esc_mtx);
2075 DPRINTF("Wrong io addr read sz:%d\r\n", size);
2077 retval = sc->io_addr;
2081 DPRINTF("Wrong io data read sz:%d\r\n", size);
2083 if (sc->io_addr > E82545_IO_REGISTER_MAX) {
2084 DPRINTF("Non-register io read addr:0x%x\r\n",
2087 retval = e82545_read_register(sc, sc->io_addr);
2090 DPRINTF("Unknown io bar read offset:0x%lx size:%d\r\n",
2095 case E82545_BAR_REGISTER:
2097 DPRINTF("Wrong register read size:%d offset:0x%lx\r\n",
2100 retval = e82545_read_register(sc, (uint32_t)offset);
2103 DPRINTF("Unknown read bar:%d offset:0x%lx size:%d\r\n",
2104 baridx, offset, size);
2108 pthread_mutex_unlock(&sc->esc_mtx);
2114 e82545_reset(struct e82545_softc *sc, int drvr)
2118 e82545_rx_disable(sc);
2119 e82545_tx_disable(sc);
2121 /* clear outstanding interrupts */
2122 if (sc->esc_irq_asserted)
2123 pci_lintr_deassert(sc->esc_pi);
2133 sc->esc_LEDCTL = 0x07061302;
2134 sc->esc_PBA = 0x00100030;
2136 /* start nvm in opcode mode. */
2138 sc->nvm_mode = E82545_NVM_MODE_OPADDR;
2139 sc->nvm_bits = E82545_NVM_OPADDR_BITS;
2140 sc->eeprom_control = E1000_EECD_PRES | E82545_EECD_FWE_EN;
2141 e82545_init_eeprom(sc);
2152 memset(sc->esc_fvlan, 0, sizeof(sc->esc_fvlan));
2153 memset(sc->esc_fmcast, 0, sizeof(sc->esc_fmcast));
2154 memset(sc->esc_uni, 0, sizeof(sc->esc_uni));
2156 /* XXX not necessary on 82545 ?? */
2157 sc->esc_uni[0].eu_valid = 1;
2158 memcpy(sc->esc_uni[0].eu_eth.octet, sc->esc_mac.octet,
2161 /* Clear RAH valid bits */
2162 for (i = 0; i < 16; i++)
2163 sc->esc_uni[i].eu_valid = 0;
2178 sc->esc_RXDCTL = (1 << 24) | (1 << 16); /* default GRAN/WTHRESH */
2192 sc->esc_txdesc = NULL;
2197 sc->esc_TDHr = sc->esc_TDH = 0;
2202 e82545_open_tap(struct e82545_softc *sc, char *opts)
2211 strcpy(tbuf, "/dev/");
2212 strlcat(tbuf, opts, sizeof(tbuf));
2214 sc->esc_tapfd = open(tbuf, O_RDWR);
2215 if (sc->esc_tapfd == -1) {
2216 DPRINTF("unable to open tap device %s\n", opts);
2221 * Set non-blocking and register for read
2222 * notifications with the event loop
2225 if (ioctl(sc->esc_tapfd, FIONBIO, &opt) < 0) {
2226 WPRINTF("tap device O_NONBLOCK failed: %d\n", errno);
2227 close(sc->esc_tapfd);
2231 sc->esc_mevp = mevent_add(sc->esc_tapfd,
2233 e82545_tap_callback,
2235 if (sc->esc_mevp == NULL) {
2236 DPRINTF("Could not register mevent %d\n", EVF_READ);
2237 close(sc->esc_tapfd);
2243 e82545_parsemac(char *mac_str, uint8_t *mac_addr)
2245 struct ether_addr *ea;
2247 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2249 tmpstr = strsep(&mac_str,"=");
2250 if ((mac_str != NULL) && (!strcmp(tmpstr,"mac"))) {
2251 ea = ether_aton(mac_str);
2252 if (ea == NULL || ETHER_IS_MULTICAST(ea->octet) ||
2253 memcmp(ea->octet, zero_addr, ETHER_ADDR_LEN) == 0) {
2254 fprintf(stderr, "Invalid MAC %s\n", mac_str);
2257 memcpy(mac_addr, ea->octet, ETHER_ADDR_LEN);
2263 e82545_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
2265 DPRINTF("Loading with options: %s\r\n", opts);
2268 unsigned char digest[16];
2270 struct e82545_softc *sc;
2275 /* Setup our softc */
2276 sc = calloc(sizeof(*sc), 1);
2282 pthread_mutex_init(&sc->esc_mtx, NULL);
2283 pthread_cond_init(&sc->esc_rx_cond, NULL);
2284 pthread_cond_init(&sc->esc_tx_cond, NULL);
2285 pthread_create(&sc->esc_tx_tid, NULL, e82545_tx_thread, sc);
2286 snprintf(nstr, sizeof(nstr), "e82545-%d:%d tx", pi->pi_slot,
2288 pthread_set_name_np(sc->esc_tx_tid, nstr);
2290 pci_set_cfgdata16(pi, PCIR_DEVICE, E82545_DEV_ID_82545EM_COPPER);
2291 pci_set_cfgdata16(pi, PCIR_VENDOR, E82545_VENDOR_ID_INTEL);
2292 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_NETWORK);
2293 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_NETWORK_ETHERNET);
2294 pci_set_cfgdata16(pi, PCIR_SUBDEV_0, E82545_SUBDEV_ID);
2295 pci_set_cfgdata16(pi, PCIR_SUBVEND_0, E82545_VENDOR_ID_INTEL);
2297 pci_set_cfgdata8(pi, PCIR_HDRTYPE, PCIM_HDRTYPE_NORMAL);
2298 pci_set_cfgdata8(pi, PCIR_INTPIN, 0x1);
2300 /* TODO: this card also supports msi, but the freebsd driver for it
2301 * does not, so I have not implemented it. */
2302 pci_lintr_request(pi);
2304 pci_emul_alloc_bar(pi, E82545_BAR_REGISTER, PCIBAR_MEM32,
2305 E82545_BAR_REGISTER_LEN);
2306 pci_emul_alloc_bar(pi, E82545_BAR_FLASH, PCIBAR_MEM32,
2307 E82545_BAR_FLASH_LEN);
2308 pci_emul_alloc_bar(pi, E82545_BAR_IO, PCIBAR_IO,
2312 * Attempt to open the tap device and read the MAC address
2313 * if specified. Copied from virtio-net, slightly modified.
2320 devname = vtopts = strdup(opts);
2321 (void) strsep(&vtopts, ",");
2323 if (vtopts != NULL) {
2324 err = e82545_parsemac(vtopts, sc->esc_mac.octet);
2332 if (strncmp(devname, "tap", 3) == 0 ||
2333 strncmp(devname, "vmnet", 5) == 0)
2334 e82545_open_tap(sc, devname);
2340 * The default MAC address is the standard NetApp OUI of 00-a0-98,
2341 * followed by an MD5 of the PCI slot/func number and dev name
2343 if (!mac_provided) {
2344 snprintf(nstr, sizeof(nstr), "%d-%d-%s", pi->pi_slot,
2345 pi->pi_func, vmname);
2348 MD5Update(&mdctx, nstr, strlen(nstr));
2349 MD5Final(digest, &mdctx);
2351 sc->esc_mac.octet[0] = 0x00;
2352 sc->esc_mac.octet[1] = 0xa0;
2353 sc->esc_mac.octet[2] = 0x98;
2354 sc->esc_mac.octet[3] = digest[0];
2355 sc->esc_mac.octet[4] = digest[1];
2356 sc->esc_mac.octet[5] = digest[2];
2359 /* H/w initiated reset */
2360 e82545_reset(sc, 0);
2365 struct pci_devemu pci_de_e82545 = {
2367 .pe_init = e82545_init,
2368 .pe_barwrite = e82545_write,
2369 .pe_barread = e82545_read
2371 PCI_EMUL_SET(pci_de_e82545);