2 * Copyright (c) 2011 NetApp, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/linker_set.h>
34 #include <sys/errno.h>
45 #include <machine/vmm.h>
57 #define CONF1_ADDR_PORT 0x0cf8
58 #define CONF1_DATA_PORT 0x0cfc
60 #define CONF1_ENABLE 0x80000000ul
62 #define MAXBUSES (PCI_BUSMAX + 1)
63 #define MAXSLOTS (PCI_SLOTMAX + 1)
64 #define MAXFUNCS (PCI_FUNCMAX + 1)
69 struct pci_devinst *fi_devi;
79 struct intxinfo si_intpins[4];
80 struct funcinfo si_funcs[MAXFUNCS];
84 uint16_t iobase, iolimit; /* I/O window */
85 uint32_t membase32, memlimit32; /* mmio window below 4GB */
86 uint64_t membase64, memlimit64; /* mmio window above 4GB */
87 struct slotinfo slotinfo[MAXSLOTS];
90 static struct businfo *pci_businfo[MAXBUSES];
92 SET_DECLARE(pci_devemu_set, struct pci_devemu);
94 static uint64_t pci_emul_iobase;
95 static uint64_t pci_emul_membase32;
96 static uint64_t pci_emul_membase64;
98 #define PCI_EMUL_IOBASE 0x2000
99 #define PCI_EMUL_IOLIMIT 0x10000
101 #define PCI_EMUL_ECFG_BASE 0xE0000000 /* 3.5GB */
102 #define PCI_EMUL_ECFG_SIZE (MAXBUSES * 1024 * 1024) /* 1MB per bus */
103 SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE);
105 #define PCI_EMUL_MEMLIMIT32 PCI_EMUL_ECFG_BASE
107 #define PCI_EMUL_MEMBASE64 0xD000000000UL
108 #define PCI_EMUL_MEMLIMIT64 0xFD00000000UL
110 static struct pci_devemu *pci_emul_finddev(char *name);
111 static void pci_lintr_route(struct pci_devinst *pi);
112 static void pci_lintr_update(struct pci_devinst *pi);
113 static void pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot,
114 int func, int coff, int bytes, uint32_t *val);
117 CFGWRITE(struct pci_devinst *pi, int coff, uint32_t val, int bytes)
121 pci_set_cfgdata8(pi, coff, val);
123 pci_set_cfgdata16(pi, coff, val);
125 pci_set_cfgdata32(pi, coff, val);
128 static __inline uint32_t
129 CFGREAD(struct pci_devinst *pi, int coff, int bytes)
133 return (pci_get_cfgdata8(pi, coff));
135 return (pci_get_cfgdata16(pi, coff));
137 return (pci_get_cfgdata32(pi, coff));
145 * Slot options are in the form:
147 * <bus>:<slot>:<func>,<emul>[,<config>]
148 * <slot>[:<func>],<emul>[,<config>]
152 * emul is a string describing the type of PCI device e.g. virtio-net
153 * config is an optional string, depending on the device, that can be
154 * used for configuration.
160 pci_parse_slot_usage(char *aopt)
163 fprintf(stderr, "Invalid PCI slot info field \"%s\"\n", aopt);
167 pci_parse_slot(char *opt)
171 char *emul, *config, *str, *cp;
172 int error, bnum, snum, fnum;
177 emul = config = NULL;
178 if ((cp = strchr(str, ',')) != NULL) {
181 if ((cp = strchr(emul, ',')) != NULL) {
186 pci_parse_slot_usage(opt);
190 /* <bus>:<slot>:<func> */
191 if (sscanf(str, "%d:%d:%d", &bnum, &snum, &fnum) != 3) {
194 if (sscanf(str, "%d:%d", &snum, &fnum) != 2) {
197 if (sscanf(str, "%d", &snum) != 1) {
203 if (bnum < 0 || bnum >= MAXBUSES || snum < 0 || snum >= MAXSLOTS ||
204 fnum < 0 || fnum >= MAXFUNCS) {
205 pci_parse_slot_usage(opt);
209 if (pci_businfo[bnum] == NULL)
210 pci_businfo[bnum] = calloc(1, sizeof(struct businfo));
212 bi = pci_businfo[bnum];
213 si = &bi->slotinfo[snum];
215 if (si->si_funcs[fnum].fi_name != NULL) {
216 fprintf(stderr, "pci slot %d:%d already occupied!\n",
221 if (pci_emul_finddev(emul) == NULL) {
222 fprintf(stderr, "pci slot %d:%d: unknown device \"%s\"\n",
228 si->si_funcs[fnum].fi_name = emul;
229 si->si_funcs[fnum].fi_param = config;
239 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset)
242 if (offset < pi->pi_msix.pba_offset)
245 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) {
253 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
256 int msix_entry_offset;
260 /* support only 4 or 8 byte writes */
261 if (size != 4 && size != 8)
265 * Return if table index is beyond what device supports
267 tab_index = offset / MSIX_TABLE_ENTRY_SIZE;
268 if (tab_index >= pi->pi_msix.table_count)
271 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
273 /* support only aligned writes */
274 if ((msix_entry_offset % size) != 0)
277 dest = (char *)(pi->pi_msix.table + tab_index);
278 dest += msix_entry_offset;
281 *((uint32_t *)dest) = value;
283 *((uint64_t *)dest) = value;
289 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size)
292 int msix_entry_offset;
294 uint64_t retval = ~0;
297 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X
298 * table but we also allow 1 byte access to accommodate reads from
301 if (size != 1 && size != 4 && size != 8)
304 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
306 /* support only aligned reads */
307 if ((msix_entry_offset % size) != 0) {
311 tab_index = offset / MSIX_TABLE_ENTRY_SIZE;
313 if (tab_index < pi->pi_msix.table_count) {
314 /* valid MSI-X Table access */
315 dest = (char *)(pi->pi_msix.table + tab_index);
316 dest += msix_entry_offset;
319 retval = *((uint8_t *)dest);
321 retval = *((uint32_t *)dest);
323 retval = *((uint64_t *)dest);
324 } else if (pci_valid_pba_offset(pi, offset)) {
325 /* return 0 for PBA access */
333 pci_msix_table_bar(struct pci_devinst *pi)
336 if (pi->pi_msix.table != NULL)
337 return (pi->pi_msix.table_bar);
343 pci_msix_pba_bar(struct pci_devinst *pi)
346 if (pi->pi_msix.table != NULL)
347 return (pi->pi_msix.pba_bar);
353 pci_emul_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
354 uint32_t *eax, void *arg)
356 struct pci_devinst *pdi = arg;
357 struct pci_devemu *pe = pdi->pi_d;
361 for (i = 0; i <= PCI_BARMAX; i++) {
362 if (pdi->pi_bar[i].type == PCIBAR_IO &&
363 port >= pdi->pi_bar[i].addr &&
364 port + bytes <= pdi->pi_bar[i].addr + pdi->pi_bar[i].size) {
365 offset = port - pdi->pi_bar[i].addr;
367 *eax = (*pe->pe_barread)(ctx, vcpu, pdi, i,
370 (*pe->pe_barwrite)(ctx, vcpu, pdi, i, offset,
379 pci_emul_mem_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
380 int size, uint64_t *val, void *arg1, long arg2)
382 struct pci_devinst *pdi = arg1;
383 struct pci_devemu *pe = pdi->pi_d;
385 int bidx = (int) arg2;
387 assert(bidx <= PCI_BARMAX);
388 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 ||
389 pdi->pi_bar[bidx].type == PCIBAR_MEM64);
390 assert(addr >= pdi->pi_bar[bidx].addr &&
391 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size);
393 offset = addr - pdi->pi_bar[bidx].addr;
395 if (dir == MEM_F_WRITE) {
397 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset,
398 4, *val & 0xffffffff);
399 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset + 4,
402 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset,
407 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx,
409 *val |= (*pe->pe_barread)(ctx, vcpu, pdi, bidx,
410 offset + 4, 4) << 32;
412 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx,
422 pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size,
427 assert((size & (size - 1)) == 0); /* must be a power of 2 */
429 base = roundup2(*baseptr, size);
431 if (base + size <= limit) {
433 *baseptr = base + size;
440 pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type,
444 return (pci_emul_alloc_pbar(pdi, idx, 0, type, size));
448 * Register (or unregister) the MMIO or I/O region associated with the BAR
449 * register 'idx' of an emulated pci device.
452 modify_bar_registration(struct pci_devinst *pi, int idx, int registration)
455 struct inout_port iop;
458 switch (pi->pi_bar[idx].type) {
460 bzero(&iop, sizeof(struct inout_port));
461 iop.name = pi->pi_name;
462 iop.port = pi->pi_bar[idx].addr;
463 iop.size = pi->pi_bar[idx].size;
465 iop.flags = IOPORT_F_INOUT;
466 iop.handler = pci_emul_io_handler;
468 error = register_inout(&iop);
470 error = unregister_inout(&iop);
474 bzero(&mr, sizeof(struct mem_range));
475 mr.name = pi->pi_name;
476 mr.base = pi->pi_bar[idx].addr;
477 mr.size = pi->pi_bar[idx].size;
480 mr.handler = pci_emul_mem_handler;
483 error = register_mem(&mr);
485 error = unregister_mem(&mr);
495 unregister_bar(struct pci_devinst *pi, int idx)
498 modify_bar_registration(pi, idx, 0);
502 register_bar(struct pci_devinst *pi, int idx)
505 modify_bar_registration(pi, idx, 1);
508 /* Are we decoding i/o port accesses for the emulated pci device? */
510 porten(struct pci_devinst *pi)
514 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
516 return (cmd & PCIM_CMD_PORTEN);
519 /* Are we decoding memory accesses for the emulated pci device? */
521 memen(struct pci_devinst *pi)
525 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
527 return (cmd & PCIM_CMD_MEMEN);
531 * Update the MMIO or I/O address that is decoded by the BAR register.
533 * If the pci device has enabled the address space decoding then intercept
534 * the address range decoded by the BAR register.
537 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type)
541 if (pi->pi_bar[idx].type == PCIBAR_IO)
547 unregister_bar(pi, idx);
552 pi->pi_bar[idx].addr = addr;
555 pi->pi_bar[idx].addr &= ~0xffffffffUL;
556 pi->pi_bar[idx].addr |= addr;
559 pi->pi_bar[idx].addr &= 0xffffffff;
560 pi->pi_bar[idx].addr |= addr;
567 register_bar(pi, idx);
571 pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx, uint64_t hostbase,
572 enum pcibar_type type, uint64_t size)
575 uint64_t *baseptr, limit, addr, mask, lobits, bar;
577 assert(idx >= 0 && idx <= PCI_BARMAX);
579 if ((size & (size - 1)) != 0)
580 size = 1UL << flsl(size); /* round up to a power of 2 */
582 /* Enforce minimum BAR sizes required by the PCI standard */
583 if (type == PCIBAR_IO) {
594 addr = mask = lobits = 0;
597 baseptr = &pci_emul_iobase;
598 limit = PCI_EMUL_IOLIMIT;
599 mask = PCIM_BAR_IO_BASE;
600 lobits = PCIM_BAR_IO_SPACE;
605 * Some drivers do not work well if the 64-bit BAR is allocated
606 * above 4GB. Allow for this by allocating small requests under
607 * 4GB unless then allocation size is larger than some arbitrary
608 * number (32MB currently).
610 if (size > 32 * 1024 * 1024) {
612 * XXX special case for device requiring peer-peer DMA
614 if (size == 0x100000000UL)
617 baseptr = &pci_emul_membase64;
618 limit = PCI_EMUL_MEMLIMIT64;
619 mask = PCIM_BAR_MEM_BASE;
620 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 |
621 PCIM_BAR_MEM_PREFETCH;
624 baseptr = &pci_emul_membase32;
625 limit = PCI_EMUL_MEMLIMIT32;
626 mask = PCIM_BAR_MEM_BASE;
627 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64;
631 baseptr = &pci_emul_membase32;
632 limit = PCI_EMUL_MEMLIMIT32;
633 mask = PCIM_BAR_MEM_BASE;
634 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32;
637 printf("pci_emul_alloc_base: invalid bar type %d\n", type);
641 if (baseptr != NULL) {
642 error = pci_emul_alloc_resource(baseptr, limit, size, &addr);
647 pdi->pi_bar[idx].type = type;
648 pdi->pi_bar[idx].addr = addr;
649 pdi->pi_bar[idx].size = size;
651 /* Initialize the BAR register in config space */
652 bar = (addr & mask) | lobits;
653 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar);
655 if (type == PCIBAR_MEM64) {
656 assert(idx + 1 <= PCI_BARMAX);
657 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64;
658 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32);
661 register_bar(pdi, idx);
666 #define CAP_START_OFFSET 0x40
668 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen)
670 int i, capoff, reallen;
675 reallen = roundup2(caplen, 4); /* dword aligned */
677 sts = pci_get_cfgdata16(pi, PCIR_STATUS);
678 if ((sts & PCIM_STATUS_CAPPRESENT) == 0)
679 capoff = CAP_START_OFFSET;
681 capoff = pi->pi_capend + 1;
683 /* Check if we have enough space */
684 if (capoff + reallen > PCI_REGMAX + 1)
687 /* Set the previous capability pointer */
688 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) {
689 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff);
690 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT);
692 pci_set_cfgdata8(pi, pi->pi_prevcap + 1, capoff);
694 /* Copy the capability */
695 for (i = 0; i < caplen; i++)
696 pci_set_cfgdata8(pi, capoff + i, capdata[i]);
698 /* Set the next capability pointer */
699 pci_set_cfgdata8(pi, capoff + 1, 0);
701 pi->pi_prevcap = capoff;
702 pi->pi_capend = capoff + reallen - 1;
706 static struct pci_devemu *
707 pci_emul_finddev(char *name)
709 struct pci_devemu **pdpp, *pdp;
711 SET_FOREACH(pdpp, pci_devemu_set) {
713 if (!strcmp(pdp->pe_emu, name)) {
722 pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int bus, int slot,
723 int func, struct funcinfo *fi)
725 struct pci_devinst *pdi;
728 pdi = calloc(1, sizeof(struct pci_devinst));
734 pthread_mutex_init(&pdi->pi_lintr.lock, NULL);
735 pdi->pi_lintr.pin = 0;
736 pdi->pi_lintr.state = IDLE;
737 pdi->pi_lintr.pirq_pin = 0;
738 pdi->pi_lintr.ioapic_irq = 0;
740 snprintf(pdi->pi_name, PI_NAMESZ, "%s-pci-%d", pde->pe_emu, slot);
742 /* Disable legacy interrupts */
743 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255);
744 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0);
746 pci_set_cfgdata8(pdi, PCIR_COMMAND,
747 PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
749 err = (*pde->pe_init)(ctx, pdi, fi->fi_param);
759 pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr)
763 CTASSERT(sizeof(struct msicap) == 14);
765 /* Number of msi messages must be a power of 2 between 1 and 32 */
766 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32);
767 mmc = ffs(msgnum) - 1;
769 bzero(msicap, sizeof(struct msicap));
770 msicap->capid = PCIY_MSI;
771 msicap->nextptr = nextptr;
772 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1);
776 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum)
778 struct msicap msicap;
780 pci_populate_msicap(&msicap, msgnum, 0);
782 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap)));
786 pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum,
787 uint32_t msix_tab_size)
789 CTASSERT(sizeof(struct msixcap) == 12);
791 assert(msix_tab_size % 4096 == 0);
793 bzero(msixcap, sizeof(struct msixcap));
794 msixcap->capid = PCIY_MSIX;
797 * Message Control Register, all fields set to
798 * zero except for the Table Size.
799 * Note: Table size N is encoded as N-1
801 msixcap->msgctrl = msgnum - 1;
805 * - MSI-X table start at offset 0
806 * - PBA table starts at a 4K aligned offset after the MSI-X table
808 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK;
809 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK);
813 pci_msix_table_init(struct pci_devinst *pi, int table_entries)
817 assert(table_entries > 0);
818 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES);
820 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE;
821 pi->pi_msix.table = calloc(1, table_size);
823 /* set mask bit of vector control register */
824 for (i = 0; i < table_entries; i++)
825 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK;
829 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum)
832 struct msixcap msixcap;
834 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES);
835 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0);
837 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE;
839 /* Align table size to nearest 4K */
840 tab_size = roundup2(tab_size, 4096);
842 pi->pi_msix.table_bar = barnum;
843 pi->pi_msix.pba_bar = barnum;
844 pi->pi_msix.table_offset = 0;
845 pi->pi_msix.table_count = msgnum;
846 pi->pi_msix.pba_offset = tab_size;
847 pi->pi_msix.pba_size = PBA_SIZE(msgnum);
849 pci_msix_table_init(pi, msgnum);
851 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size);
853 /* allocate memory for MSI-X Table and PBA */
854 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32,
855 tab_size + pi->pi_msix.pba_size);
857 return (pci_emul_add_capability(pi, (u_char *)&msixcap,
862 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
863 int bytes, uint32_t val)
865 uint16_t msgctrl, rwmask;
868 off = offset - capoff;
869 /* Message Control Register */
870 if (off == 2 && bytes == 2) {
871 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK;
872 msgctrl = pci_get_cfgdata16(pi, offset);
874 msgctrl |= val & rwmask;
877 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE;
878 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK;
879 pci_lintr_update(pi);
882 CFGWRITE(pi, offset, val, bytes);
886 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
887 int bytes, uint32_t val)
889 uint16_t msgctrl, rwmask, msgdata, mme;
893 * If guest is writing to the message control register make sure
894 * we do not overwrite read-only fields.
896 if ((offset - capoff) == 2 && bytes == 2) {
897 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE;
898 msgctrl = pci_get_cfgdata16(pi, offset);
900 msgctrl |= val & rwmask;
903 addrlo = pci_get_cfgdata32(pi, capoff + 4);
904 if (msgctrl & PCIM_MSICTRL_64BIT)
905 msgdata = pci_get_cfgdata16(pi, capoff + 12);
907 msgdata = pci_get_cfgdata16(pi, capoff + 8);
909 mme = msgctrl & PCIM_MSICTRL_MME_MASK;
910 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0;
911 if (pi->pi_msi.enabled) {
912 pi->pi_msi.addr = addrlo;
913 pi->pi_msi.msg_data = msgdata;
914 pi->pi_msi.maxmsgnum = 1 << (mme >> 4);
916 pi->pi_msi.maxmsgnum = 0;
918 pci_lintr_update(pi);
921 CFGWRITE(pi, offset, val, bytes);
925 pciecap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
926 int bytes, uint32_t val)
929 /* XXX don't write to the readonly parts */
930 CFGWRITE(pi, offset, val, bytes);
933 #define PCIECAP_VERSION 0x2
935 pci_emul_add_pciecap(struct pci_devinst *pi, int type)
938 struct pciecap pciecap;
940 CTASSERT(sizeof(struct pciecap) == 60);
942 if (type != PCIEM_TYPE_ROOT_PORT)
945 bzero(&pciecap, sizeof(pciecap));
947 pciecap.capid = PCIY_EXPRESS;
948 pciecap.pcie_capabilities = PCIECAP_VERSION | PCIEM_TYPE_ROOT_PORT;
949 pciecap.link_capabilities = 0x411; /* gen1, x1 */
950 pciecap.link_status = 0x11; /* gen1, x1 */
952 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap));
957 * This function assumes that 'coff' is in the capabilities region of the
961 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val)
964 uint8_t capoff, nextoff;
966 /* Do not allow un-aligned writes */
967 if ((offset & (bytes - 1)) != 0)
970 /* Find the capability that we want to update */
971 capoff = CAP_START_OFFSET;
973 nextoff = pci_get_cfgdata8(pi, capoff + 1);
976 if (offset >= capoff && offset < nextoff)
981 assert(offset >= capoff);
984 * Capability ID and Next Capability Pointer are readonly.
985 * However, some o/s's do 4-byte writes that include these.
986 * For this case, trim the write back to 2 bytes and adjust
989 if (offset == capoff || offset == capoff + 1) {
990 if (offset == capoff && bytes == 4) {
998 capid = pci_get_cfgdata8(pi, capoff);
1001 msicap_cfgwrite(pi, capoff, offset, bytes, val);
1004 msixcap_cfgwrite(pi, capoff, offset, bytes, val);
1007 pciecap_cfgwrite(pi, capoff, offset, bytes, val);
1015 pci_emul_iscap(struct pci_devinst *pi, int offset)
1019 sts = pci_get_cfgdata16(pi, PCIR_STATUS);
1020 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) {
1021 if (offset >= CAP_START_OFFSET && offset <= pi->pi_capend)
1028 pci_emul_fallback_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
1029 int size, uint64_t *val, void *arg1, long arg2)
1032 * Ignore writes; return 0xff's for reads. The mem read code
1033 * will take care of truncating to the correct size.
1035 if (dir == MEM_F_READ) {
1036 *val = 0xffffffffffffffff;
1043 pci_emul_ecfg_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
1044 int bytes, uint64_t *val, void *arg1, long arg2)
1046 int bus, slot, func, coff, in;
1048 coff = addr & 0xfff;
1049 func = (addr >> 12) & 0x7;
1050 slot = (addr >> 15) & 0x1f;
1051 bus = (addr >> 20) & 0xff;
1052 in = (dir == MEM_F_READ);
1055 pci_cfgrw(ctx, vcpu, in, bus, slot, func, coff, bytes, (uint32_t *)val);
1063 return (PCI_EMUL_ECFG_BASE);
1066 #define BUSIO_ROUNDUP 32
1067 #define BUSMEM_ROUNDUP (1024 * 1024)
1070 init_pci(struct vmctx *ctx)
1072 struct mem_range mr;
1073 struct pci_devemu *pde;
1075 struct slotinfo *si;
1076 struct funcinfo *fi;
1078 int bus, slot, func;
1081 pci_emul_iobase = PCI_EMUL_IOBASE;
1082 pci_emul_membase32 = vm_get_lowmem_limit(ctx);
1083 pci_emul_membase64 = PCI_EMUL_MEMBASE64;
1085 for (bus = 0; bus < MAXBUSES; bus++) {
1086 if ((bi = pci_businfo[bus]) == NULL)
1089 * Keep track of the i/o and memory resources allocated to
1092 bi->iobase = pci_emul_iobase;
1093 bi->membase32 = pci_emul_membase32;
1094 bi->membase64 = pci_emul_membase64;
1096 for (slot = 0; slot < MAXSLOTS; slot++) {
1097 si = &bi->slotinfo[slot];
1098 for (func = 0; func < MAXFUNCS; func++) {
1099 fi = &si->si_funcs[func];
1100 if (fi->fi_name == NULL)
1102 pde = pci_emul_finddev(fi->fi_name);
1103 assert(pde != NULL);
1104 error = pci_emul_init(ctx, pde, bus, slot,
1112 * Add some slop to the I/O and memory resources decoded by
1113 * this bus to give a guest some flexibility if it wants to
1114 * reprogram the BARs.
1116 pci_emul_iobase += BUSIO_ROUNDUP;
1117 pci_emul_iobase = roundup2(pci_emul_iobase, BUSIO_ROUNDUP);
1118 bi->iolimit = pci_emul_iobase;
1120 pci_emul_membase32 += BUSMEM_ROUNDUP;
1121 pci_emul_membase32 = roundup2(pci_emul_membase32,
1123 bi->memlimit32 = pci_emul_membase32;
1125 pci_emul_membase64 += BUSMEM_ROUNDUP;
1126 pci_emul_membase64 = roundup2(pci_emul_membase64,
1128 bi->memlimit64 = pci_emul_membase64;
1132 * PCI backends are initialized before routing INTx interrupts
1133 * so that LPC devices are able to reserve ISA IRQs before
1134 * routing PIRQ pins.
1136 for (bus = 0; bus < MAXBUSES; bus++) {
1137 if ((bi = pci_businfo[bus]) == NULL)
1140 for (slot = 0; slot < MAXSLOTS; slot++) {
1141 si = &bi->slotinfo[slot];
1142 for (func = 0; func < MAXFUNCS; func++) {
1143 fi = &si->si_funcs[func];
1144 if (fi->fi_devi == NULL)
1146 pci_lintr_route(fi->fi_devi);
1153 * The guest physical memory map looks like the following:
1154 * [0, lowmem) guest system memory
1155 * [lowmem, lowmem_limit) memory hole (may be absent)
1156 * [lowmem_limit, 0xE0000000) PCI hole (32-bit BAR allocation)
1157 * [0xE0000000, 0xF0000000) PCI extended config window
1158 * [0xF0000000, 4GB) LAPIC, IOAPIC, HPET, firmware
1159 * [4GB, 4GB + highmem)
1163 * Accesses to memory addresses that are not allocated to system
1164 * memory or PCI devices return 0xff's.
1166 lowmem = vm_get_lowmem_size(ctx);
1167 bzero(&mr, sizeof(struct mem_range));
1168 mr.name = "PCI hole";
1169 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE;
1171 mr.size = (4ULL * 1024 * 1024 * 1024) - lowmem;
1172 mr.handler = pci_emul_fallback_handler;
1173 error = register_mem_fallback(&mr);
1176 /* PCI extended config space */
1177 bzero(&mr, sizeof(struct mem_range));
1178 mr.name = "PCI ECFG";
1179 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE;
1180 mr.base = PCI_EMUL_ECFG_BASE;
1181 mr.size = PCI_EMUL_ECFG_SIZE;
1182 mr.handler = pci_emul_ecfg_handler;
1183 error = register_mem(&mr);
1190 pci_apic_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq,
1194 dsdt_line(" Package ()");
1196 dsdt_line(" 0x%X,", slot << 16 | 0xffff);
1197 dsdt_line(" 0x%02X,", pin - 1);
1198 dsdt_line(" Zero,");
1199 dsdt_line(" 0x%X", ioapic_irq);
1204 pci_pirq_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq,
1209 name = lpc_pirq_name(pirq_pin);
1212 dsdt_line(" Package ()");
1214 dsdt_line(" 0x%X,", slot << 16 | 0xffff);
1215 dsdt_line(" 0x%02X,", pin - 1);
1216 dsdt_line(" %s,", name);
1223 * A bhyve virtual machine has a flat PCI hierarchy with a root port
1224 * corresponding to each PCI bus.
1227 pci_bus_write_dsdt(int bus)
1230 struct slotinfo *si;
1231 struct pci_devinst *pi;
1232 int count, func, slot;
1235 * If there are no devices on this 'bus' then just return.
1237 if ((bi = pci_businfo[bus]) == NULL) {
1239 * Bus 0 is special because it decodes the I/O ports used
1240 * for PCI config space access even if there are no devices
1247 dsdt_line(" Device (PC%02X)", bus);
1249 dsdt_line(" Name (_HID, EisaId (\"PNP0A03\"))");
1250 dsdt_line(" Name (_ADR, Zero)");
1252 dsdt_line(" Method (_BBN, 0, NotSerialized)");
1254 dsdt_line(" Return (0x%08X)", bus);
1256 dsdt_line(" Name (_CRS, ResourceTemplate ()");
1258 dsdt_line(" WordBusNumber (ResourceProducer, MinFixed, "
1259 "MaxFixed, PosDecode,");
1260 dsdt_line(" 0x0000, // Granularity");
1261 dsdt_line(" 0x%04X, // Range Minimum", bus);
1262 dsdt_line(" 0x%04X, // Range Maximum", bus);
1263 dsdt_line(" 0x0000, // Translation Offset");
1264 dsdt_line(" 0x0001, // Length");
1269 dsdt_fixed_ioport(0xCF8, 8);
1272 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, "
1273 "PosDecode, EntireRange,");
1274 dsdt_line(" 0x0000, // Granularity");
1275 dsdt_line(" 0x0000, // Range Minimum");
1276 dsdt_line(" 0x0CF7, // Range Maximum");
1277 dsdt_line(" 0x0000, // Translation Offset");
1278 dsdt_line(" 0x0CF8, // Length");
1279 dsdt_line(" ,, , TypeStatic)");
1281 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, "
1282 "PosDecode, EntireRange,");
1283 dsdt_line(" 0x0000, // Granularity");
1284 dsdt_line(" 0x0D00, // Range Minimum");
1285 dsdt_line(" 0x%04X, // Range Maximum",
1286 PCI_EMUL_IOBASE - 1);
1287 dsdt_line(" 0x0000, // Translation Offset");
1288 dsdt_line(" 0x%04X, // Length",
1289 PCI_EMUL_IOBASE - 0x0D00);
1290 dsdt_line(" ,, , TypeStatic)");
1300 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, "
1301 "PosDecode, EntireRange,");
1302 dsdt_line(" 0x0000, // Granularity");
1303 dsdt_line(" 0x%04X, // Range Minimum", bi->iobase);
1304 dsdt_line(" 0x%04X, // Range Maximum",
1306 dsdt_line(" 0x0000, // Translation Offset");
1307 dsdt_line(" 0x%04X, // Length",
1308 bi->iolimit - bi->iobase);
1309 dsdt_line(" ,, , TypeStatic)");
1311 /* mmio window (32-bit) */
1312 dsdt_line(" DWordMemory (ResourceProducer, PosDecode, "
1313 "MinFixed, MaxFixed, NonCacheable, ReadWrite,");
1314 dsdt_line(" 0x00000000, // Granularity");
1315 dsdt_line(" 0x%08X, // Range Minimum\n", bi->membase32);
1316 dsdt_line(" 0x%08X, // Range Maximum\n",
1317 bi->memlimit32 - 1);
1318 dsdt_line(" 0x00000000, // Translation Offset");
1319 dsdt_line(" 0x%08X, // Length\n",
1320 bi->memlimit32 - bi->membase32);
1321 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)");
1323 /* mmio window (64-bit) */
1324 dsdt_line(" QWordMemory (ResourceProducer, PosDecode, "
1325 "MinFixed, MaxFixed, NonCacheable, ReadWrite,");
1326 dsdt_line(" 0x0000000000000000, // Granularity");
1327 dsdt_line(" 0x%016lX, // Range Minimum\n", bi->membase64);
1328 dsdt_line(" 0x%016lX, // Range Maximum\n",
1329 bi->memlimit64 - 1);
1330 dsdt_line(" 0x0000000000000000, // Translation Offset");
1331 dsdt_line(" 0x%016lX, // Length\n",
1332 bi->memlimit64 - bi->membase64);
1333 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)");
1336 count = pci_count_lintr(bus);
1339 dsdt_line("Name (PPRT, Package ()");
1341 pci_walk_lintr(bus, pci_pirq_prt_entry, NULL);
1343 dsdt_line("Name (APRT, Package ()");
1345 pci_walk_lintr(bus, pci_apic_prt_entry, NULL);
1347 dsdt_line("Method (_PRT, 0, NotSerialized)");
1349 dsdt_line(" If (PICM)");
1351 dsdt_line(" Return (APRT)");
1355 dsdt_line(" Return (PPRT)");
1362 for (slot = 0; slot < MAXSLOTS; slot++) {
1363 si = &bi->slotinfo[slot];
1364 for (func = 0; func < MAXFUNCS; func++) {
1365 pi = si->si_funcs[func].fi_devi;
1366 if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL)
1367 pi->pi_d->pe_write_dsdt(pi);
1376 pci_write_dsdt(void)
1381 dsdt_line("Name (PICM, 0x00)");
1382 dsdt_line("Method (_PIC, 1, NotSerialized)");
1384 dsdt_line(" Store (Arg0, PICM)");
1387 dsdt_line("Scope (_SB)");
1389 for (bus = 0; bus < MAXBUSES; bus++)
1390 pci_bus_write_dsdt(bus);
1396 pci_bus_configured(int bus)
1398 assert(bus >= 0 && bus < MAXBUSES);
1399 return (pci_businfo[bus] != NULL);
1403 pci_msi_enabled(struct pci_devinst *pi)
1405 return (pi->pi_msi.enabled);
1409 pci_msi_maxmsgnum(struct pci_devinst *pi)
1411 if (pi->pi_msi.enabled)
1412 return (pi->pi_msi.maxmsgnum);
1418 pci_msix_enabled(struct pci_devinst *pi)
1421 return (pi->pi_msix.enabled && !pi->pi_msi.enabled);
1425 pci_generate_msix(struct pci_devinst *pi, int index)
1427 struct msix_table_entry *mte;
1429 if (!pci_msix_enabled(pi))
1432 if (pi->pi_msix.function_mask)
1435 if (index >= pi->pi_msix.table_count)
1438 mte = &pi->pi_msix.table[index];
1439 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) {
1440 /* XXX Set PBA bit if interrupt is disabled */
1441 vm_lapic_msi(pi->pi_vmctx, mte->addr, mte->msg_data);
1446 pci_generate_msi(struct pci_devinst *pi, int index)
1449 if (pci_msi_enabled(pi) && index < pci_msi_maxmsgnum(pi)) {
1450 vm_lapic_msi(pi->pi_vmctx, pi->pi_msi.addr,
1451 pi->pi_msi.msg_data + index);
1456 pci_lintr_permitted(struct pci_devinst *pi)
1460 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
1461 return (!(pi->pi_msi.enabled || pi->pi_msix.enabled ||
1462 (cmd & PCIM_CMD_INTxDIS)));
1466 pci_lintr_request(struct pci_devinst *pi)
1469 struct slotinfo *si;
1470 int bestpin, bestcount, pin;
1472 bi = pci_businfo[pi->pi_bus];
1476 * Just allocate a pin from our slot. The pin will be
1477 * assigned IRQs later when interrupts are routed.
1479 si = &bi->slotinfo[pi->pi_slot];
1481 bestcount = si->si_intpins[0].ii_count;
1482 for (pin = 1; pin < 4; pin++) {
1483 if (si->si_intpins[pin].ii_count < bestcount) {
1485 bestcount = si->si_intpins[pin].ii_count;
1489 si->si_intpins[bestpin].ii_count++;
1490 pi->pi_lintr.pin = bestpin + 1;
1491 pci_set_cfgdata8(pi, PCIR_INTPIN, bestpin + 1);
1495 pci_lintr_route(struct pci_devinst *pi)
1498 struct intxinfo *ii;
1500 if (pi->pi_lintr.pin == 0)
1503 bi = pci_businfo[pi->pi_bus];
1505 ii = &bi->slotinfo[pi->pi_slot].si_intpins[pi->pi_lintr.pin - 1];
1508 * Attempt to allocate an I/O APIC pin for this intpin if one
1509 * is not yet assigned.
1511 if (ii->ii_ioapic_irq == 0)
1512 ii->ii_ioapic_irq = ioapic_pci_alloc_irq();
1513 assert(ii->ii_ioapic_irq > 0);
1516 * Attempt to allocate a PIRQ pin for this intpin if one is
1519 if (ii->ii_pirq_pin == 0)
1520 ii->ii_pirq_pin = pirq_alloc_pin(pi->pi_vmctx);
1521 assert(ii->ii_pirq_pin > 0);
1523 pi->pi_lintr.ioapic_irq = ii->ii_ioapic_irq;
1524 pi->pi_lintr.pirq_pin = ii->ii_pirq_pin;
1525 pci_set_cfgdata8(pi, PCIR_INTLINE, pirq_irq(ii->ii_pirq_pin));
1529 pci_lintr_assert(struct pci_devinst *pi)
1532 assert(pi->pi_lintr.pin > 0);
1534 pthread_mutex_lock(&pi->pi_lintr.lock);
1535 if (pi->pi_lintr.state == IDLE) {
1536 if (pci_lintr_permitted(pi)) {
1537 pi->pi_lintr.state = ASSERTED;
1540 pi->pi_lintr.state = PENDING;
1542 pthread_mutex_unlock(&pi->pi_lintr.lock);
1546 pci_lintr_deassert(struct pci_devinst *pi)
1549 assert(pi->pi_lintr.pin > 0);
1551 pthread_mutex_lock(&pi->pi_lintr.lock);
1552 if (pi->pi_lintr.state == ASSERTED) {
1553 pi->pi_lintr.state = IDLE;
1554 pci_irq_deassert(pi);
1555 } else if (pi->pi_lintr.state == PENDING)
1556 pi->pi_lintr.state = IDLE;
1557 pthread_mutex_unlock(&pi->pi_lintr.lock);
1561 pci_lintr_update(struct pci_devinst *pi)
1564 pthread_mutex_lock(&pi->pi_lintr.lock);
1565 if (pi->pi_lintr.state == ASSERTED && !pci_lintr_permitted(pi)) {
1566 pci_irq_deassert(pi);
1567 pi->pi_lintr.state = PENDING;
1568 } else if (pi->pi_lintr.state == PENDING && pci_lintr_permitted(pi)) {
1569 pi->pi_lintr.state = ASSERTED;
1572 pthread_mutex_unlock(&pi->pi_lintr.lock);
1576 pci_count_lintr(int bus)
1578 int count, slot, pin;
1579 struct slotinfo *slotinfo;
1582 if (pci_businfo[bus] != NULL) {
1583 for (slot = 0; slot < MAXSLOTS; slot++) {
1584 slotinfo = &pci_businfo[bus]->slotinfo[slot];
1585 for (pin = 0; pin < 4; pin++) {
1586 if (slotinfo->si_intpins[pin].ii_count != 0)
1595 pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg)
1598 struct slotinfo *si;
1599 struct intxinfo *ii;
1602 if ((bi = pci_businfo[bus]) == NULL)
1605 for (slot = 0; slot < MAXSLOTS; slot++) {
1606 si = &bi->slotinfo[slot];
1607 for (pin = 0; pin < 4; pin++) {
1608 ii = &si->si_intpins[pin];
1609 if (ii->ii_count != 0)
1610 cb(bus, slot, pin + 1, ii->ii_pirq_pin,
1611 ii->ii_ioapic_irq, arg);
1617 * Return 1 if the emulated device in 'slot' is a multi-function device.
1618 * Return 0 otherwise.
1621 pci_emul_is_mfdev(int bus, int slot)
1624 struct slotinfo *si;
1628 if ((bi = pci_businfo[bus]) != NULL) {
1629 si = &bi->slotinfo[slot];
1630 for (f = 0; f < MAXFUNCS; f++) {
1631 if (si->si_funcs[f].fi_devi != NULL) {
1636 return (numfuncs > 1);
1640 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on
1641 * whether or not is a multi-function being emulated in the pci 'slot'.
1644 pci_emul_hdrtype_fixup(int bus, int slot, int off, int bytes, uint32_t *rv)
1648 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) {
1649 mfdev = pci_emul_is_mfdev(bus, slot);
1659 *rv &= ~(PCIM_MFDEV << 16);
1661 *rv |= (PCIM_MFDEV << 16);
1669 pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes)
1672 uint32_t cmd, cmd2, changed, old, readonly;
1674 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */
1677 * From PCI Local Bus Specification 3.0 sections 6.2.2 and 6.2.3.
1679 * XXX Bits 8, 11, 12, 13, 14 and 15 in the status register are
1680 * 'write 1 to clear'. However these bits are not set to '1' by
1681 * any device emulation so it is simpler to treat them as readonly.
1683 rshift = (coff & 0x3) * 8;
1684 readonly = 0xFFFFF880 >> rshift;
1686 old = CFGREAD(pi, coff, bytes);
1688 new |= (old & readonly);
1689 CFGWRITE(pi, coff, new, bytes); /* update config */
1691 cmd2 = pci_get_cfgdata16(pi, PCIR_COMMAND); /* get updated value */
1692 changed = cmd ^ cmd2;
1695 * If the MMIO or I/O address space decoding has changed then
1696 * register/unregister all BARs that decode that address space.
1698 for (i = 0; i <= PCI_BARMAX; i++) {
1699 switch (pi->pi_bar[i].type) {
1701 case PCIBAR_MEMHI64:
1704 /* I/O address space decoding changed? */
1705 if (changed & PCIM_CMD_PORTEN) {
1707 register_bar(pi, i);
1709 unregister_bar(pi, i);
1714 /* MMIO address space decoding changed? */
1715 if (changed & PCIM_CMD_MEMEN) {
1717 register_bar(pi, i);
1719 unregister_bar(pi, i);
1728 * If INTx has been unmasked and is pending, assert the
1731 pci_lintr_update(pi);
1735 pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot, int func,
1736 int coff, int bytes, uint32_t *eax)
1739 struct slotinfo *si;
1740 struct pci_devinst *pi;
1741 struct pci_devemu *pe;
1743 uint64_t addr, bar, mask;
1745 if ((bi = pci_businfo[bus]) != NULL) {
1746 si = &bi->slotinfo[slot];
1747 pi = si->si_funcs[func].fi_devi;
1752 * Just return if there is no device at this slot:func or if the
1753 * the guest is doing an un-aligned access.
1755 if (pi == NULL || (bytes != 1 && bytes != 2 && bytes != 4) ||
1756 (coff & (bytes - 1)) != 0) {
1763 * Ignore all writes beyond the standard config space and return all
1766 if (coff >= PCI_REGMAX + 1) {
1770 * Extended capabilities begin at offset 256 in config
1771 * space. Absence of extended capabilities is signaled
1772 * with all 0s in the extended capability header at
1775 if (coff <= PCI_REGMAX + 4)
1787 /* Let the device emulation override the default handler */
1788 if (pe->pe_cfgread != NULL) {
1789 needcfg = pe->pe_cfgread(ctx, vcpu, pi, coff, bytes,
1796 *eax = CFGREAD(pi, coff, bytes);
1798 pci_emul_hdrtype_fixup(bus, slot, coff, bytes, eax);
1800 /* Let the device emulation override the default handler */
1801 if (pe->pe_cfgwrite != NULL &&
1802 (*pe->pe_cfgwrite)(ctx, vcpu, pi, coff, bytes, *eax) == 0)
1806 * Special handling for write to BAR registers
1808 if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)) {
1810 * Ignore writes to BAR registers that are not
1813 if (bytes != 4 || (coff & 0x3) != 0)
1815 idx = (coff - PCIR_BAR(0)) / 4;
1816 mask = ~(pi->pi_bar[idx].size - 1);
1817 switch (pi->pi_bar[idx].type) {
1819 pi->pi_bar[idx].addr = bar = 0;
1824 bar = addr | PCIM_BAR_IO_SPACE;
1826 * Register the new BAR value for interception
1828 if (addr != pi->pi_bar[idx].addr) {
1829 update_bar_address(pi, addr, idx,
1834 addr = bar = *eax & mask;
1835 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32;
1836 if (addr != pi->pi_bar[idx].addr) {
1837 update_bar_address(pi, addr, idx,
1842 addr = bar = *eax & mask;
1843 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 |
1844 PCIM_BAR_MEM_PREFETCH;
1845 if (addr != (uint32_t)pi->pi_bar[idx].addr) {
1846 update_bar_address(pi, addr, idx,
1850 case PCIBAR_MEMHI64:
1851 mask = ~(pi->pi_bar[idx - 1].size - 1);
1852 addr = ((uint64_t)*eax << 32) & mask;
1854 if (bar != pi->pi_bar[idx - 1].addr >> 32) {
1855 update_bar_address(pi, addr, idx - 1,
1862 pci_set_cfgdata32(pi, coff, bar);
1864 } else if (pci_emul_iscap(pi, coff)) {
1865 pci_emul_capwrite(pi, coff, bytes, *eax);
1866 } else if (coff >= PCIR_COMMAND && coff < PCIR_REVID) {
1867 pci_emul_cmdsts_write(pi, coff, *eax, bytes);
1869 CFGWRITE(pi, coff, *eax, bytes);
1874 static int cfgenable, cfgbus, cfgslot, cfgfunc, cfgoff;
1877 pci_emul_cfgaddr(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
1878 uint32_t *eax, void *arg)
1884 *eax = (bytes == 2) ? 0xffff : 0xff;
1889 x = (cfgbus << 16) | (cfgslot << 11) | (cfgfunc << 8) | cfgoff;
1895 cfgenable = (x & CONF1_ENABLE) == CONF1_ENABLE;
1896 cfgoff = x & PCI_REGMAX;
1897 cfgfunc = (x >> 8) & PCI_FUNCMAX;
1898 cfgslot = (x >> 11) & PCI_SLOTMAX;
1899 cfgbus = (x >> 16) & PCI_BUSMAX;
1904 INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr);
1907 pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
1908 uint32_t *eax, void *arg)
1912 assert(bytes == 1 || bytes == 2 || bytes == 4);
1914 coff = cfgoff + (port - CONF1_DATA_PORT);
1916 pci_cfgrw(ctx, vcpu, in, cfgbus, cfgslot, cfgfunc, coff, bytes,
1919 /* Ignore accesses to cfgdata if not enabled by cfgaddr */
1926 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata);
1927 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata);
1928 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata);
1929 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata);
1931 #define PCI_EMUL_TEST
1932 #ifdef PCI_EMUL_TEST
1934 * Define a dummy test device
1938 struct pci_emul_dsoftc {
1939 uint8_t ioregs[DIOSZ];
1940 uint8_t memregs[2][DMEMSZ];
1943 #define PCI_EMUL_MSI_MSGS 4
1944 #define PCI_EMUL_MSIX_MSGS 16
1947 pci_emul_dinit(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
1950 struct pci_emul_dsoftc *sc;
1952 sc = calloc(1, sizeof(struct pci_emul_dsoftc));
1956 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001);
1957 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD);
1958 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02);
1960 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS);
1963 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ);
1966 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ);
1969 error = pci_emul_alloc_bar(pi, 2, PCIBAR_MEM32, DMEMSZ);
1976 pci_emul_diow(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
1977 uint64_t offset, int size, uint64_t value)
1980 struct pci_emul_dsoftc *sc = pi->pi_arg;
1983 if (offset + size > DIOSZ) {
1984 printf("diow: iow too large, offset %ld size %d\n",
1990 sc->ioregs[offset] = value & 0xff;
1991 } else if (size == 2) {
1992 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff;
1993 } else if (size == 4) {
1994 *(uint32_t *)&sc->ioregs[offset] = value;
1996 printf("diow: iow unknown size %d\n", size);
2000 * Special magic value to generate an interrupt
2002 if (offset == 4 && size == 4 && pci_msi_enabled(pi))
2003 pci_generate_msi(pi, value % pci_msi_maxmsgnum(pi));
2005 if (value == 0xabcdef) {
2006 for (i = 0; i < pci_msi_maxmsgnum(pi); i++)
2007 pci_generate_msi(pi, i);
2011 if (baridx == 1 || baridx == 2) {
2012 if (offset + size > DMEMSZ) {
2013 printf("diow: memw too large, offset %ld size %d\n",
2018 i = baridx - 1; /* 'memregs' index */
2021 sc->memregs[i][offset] = value;
2022 } else if (size == 2) {
2023 *(uint16_t *)&sc->memregs[i][offset] = value;
2024 } else if (size == 4) {
2025 *(uint32_t *)&sc->memregs[i][offset] = value;
2026 } else if (size == 8) {
2027 *(uint64_t *)&sc->memregs[i][offset] = value;
2029 printf("diow: memw unknown size %d\n", size);
2033 * magic interrupt ??
2038 printf("diow: unknown bar idx %d\n", baridx);
2043 pci_emul_dior(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
2044 uint64_t offset, int size)
2046 struct pci_emul_dsoftc *sc = pi->pi_arg;
2051 if (offset + size > DIOSZ) {
2052 printf("dior: ior too large, offset %ld size %d\n",
2058 value = sc->ioregs[offset];
2059 } else if (size == 2) {
2060 value = *(uint16_t *) &sc->ioregs[offset];
2061 } else if (size == 4) {
2062 value = *(uint32_t *) &sc->ioregs[offset];
2064 printf("dior: ior unknown size %d\n", size);
2068 if (baridx == 1 || baridx == 2) {
2069 if (offset + size > DMEMSZ) {
2070 printf("dior: memr too large, offset %ld size %d\n",
2075 i = baridx - 1; /* 'memregs' index */
2078 value = sc->memregs[i][offset];
2079 } else if (size == 2) {
2080 value = *(uint16_t *) &sc->memregs[i][offset];
2081 } else if (size == 4) {
2082 value = *(uint32_t *) &sc->memregs[i][offset];
2083 } else if (size == 8) {
2084 value = *(uint64_t *) &sc->memregs[i][offset];
2086 printf("dior: ior unknown size %d\n", size);
2092 printf("dior: unknown bar idx %d\n", baridx);
2099 struct pci_devemu pci_dummy = {
2101 .pe_init = pci_emul_dinit,
2102 .pe_barwrite = pci_emul_diow,
2103 .pe_barread = pci_emul_dior
2105 PCI_EMUL_SET(pci_dummy);
2107 #endif /* PCI_EMUL_TEST */