2 * Copyright (c) 2011 NetApp, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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32 #include <sys/types.h>
33 #include <sys/queue.h>
34 #include <sys/kernel.h>
35 #include <sys/_pthreadtypes.h>
37 #include <dev/pci/pcireg.h>
41 #define PCI_BARMAX PCIR_MAX_BAR_0 /* BAR registers in a Type 0 header */
42 #define PCIY_RESERVED 0x00
49 char *pe_emu; /* Name of device emulation */
51 /* instance creation */
52 int (*pe_init)(struct vmctx *, struct pci_devinst *,
55 /* ACPI DSDT enumeration */
56 void (*pe_write_dsdt)(struct pci_devinst *);
58 /* config space read/write callbacks */
59 int (*pe_cfgwrite)(struct vmctx *ctx, int vcpu,
60 struct pci_devinst *pi, int offset,
61 int bytes, uint32_t val);
62 int (*pe_cfgread)(struct vmctx *ctx, int vcpu,
63 struct pci_devinst *pi, int offset,
64 int bytes, uint32_t *retval);
66 /* BAR read/write callbacks */
67 void (*pe_barwrite)(struct vmctx *ctx, int vcpu,
68 struct pci_devinst *pi, int baridx,
69 uint64_t offset, int size, uint64_t value);
70 uint64_t (*pe_barread)(struct vmctx *ctx, int vcpu,
71 struct pci_devinst *pi, int baridx,
72 uint64_t offset, int size);
74 #define PCI_EMUL_SET(x) DATA_SET(pci_devemu_set, x);
85 enum pcibar_type type; /* io or memory */
92 struct msix_table_entry {
95 uint32_t vector_control;
99 * In case the structure is modified to hold extra information, use a define
100 * for the size that should be emulated.
102 #define MSIX_TABLE_ENTRY_SIZE 16
103 #define MAX_MSIX_TABLE_ENTRIES 2048
104 #define PBA_TABLE_ENTRY_SIZE 8
113 struct pci_devemu *pi_d;
114 struct vmctx *pi_vmctx;
115 uint8_t pi_bus, pi_slot, pi_func;
116 char pi_name[PI_NAMESZ];
121 enum lintr_stat state;
123 pthread_mutex_t lock;
142 struct msix_table_entry *table; /* allocated at runtime */
145 void *pi_arg; /* devemu-private data */
147 u_char pi_cfgdata[PCI_REGMAX + 1];
148 struct pcibar pi_bar[PCI_BARMAX + 1];
164 uint32_t table_info; /* bar index and offset within it */
165 uint32_t pba_info; /* bar index and offset within it */
171 uint16_t pcie_capabilities;
173 uint32_t dev_capabilities; /* all devices */
174 uint16_t dev_control;
177 uint32_t link_capabilities; /* devices with links */
178 uint16_t link_control;
179 uint16_t link_status;
181 uint32_t slot_capabilities; /* ports with slots */
182 uint16_t slot_control;
183 uint16_t slot_status;
185 uint16_t root_control; /* root ports */
186 uint16_t root_capabilities;
187 uint32_t root_status;
189 uint32_t dev_capabilities2; /* all devices */
190 uint16_t dev_control2;
191 uint16_t dev_status2;
193 uint32_t link_capabilities2; /* devices with links */
194 uint16_t link_control2;
195 uint16_t link_status2;
197 uint32_t slot_capabilities2; /* ports with slots */
198 uint16_t slot_control2;
199 uint16_t slot_status2;
202 typedef void (*pci_lintr_cb)(int slot, int pin, int ioapic_irq, void *arg);
204 int init_pci(struct vmctx *ctx);
205 void msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
206 int bytes, uint32_t val);
207 void msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
208 int bytes, uint32_t val);
209 void pci_callback(void);
210 int pci_emul_alloc_bar(struct pci_devinst *pdi, int idx,
211 enum pcibar_type type, uint64_t size);
212 int pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx,
213 uint64_t hostbase, enum pcibar_type type, uint64_t size);
214 int pci_emul_add_msicap(struct pci_devinst *pi, int msgnum);
215 int pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type);
216 void pci_generate_msi(struct pci_devinst *pi, int msgnum);
217 void pci_generate_msix(struct pci_devinst *pi, int msgnum);
218 void pci_lintr_assert(struct pci_devinst *pi);
219 void pci_lintr_deassert(struct pci_devinst *pi);
220 int pci_lintr_request(struct pci_devinst *pi);
221 int pci_msi_enabled(struct pci_devinst *pi);
222 int pci_msix_enabled(struct pci_devinst *pi);
223 int pci_msix_table_bar(struct pci_devinst *pi);
224 int pci_msix_pba_bar(struct pci_devinst *pi);
225 int pci_msi_msgnum(struct pci_devinst *pi);
226 int pci_parse_slot(char *opt);
227 void pci_populate_msicap(struct msicap *cap, int msgs, int nextptr);
228 int pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum);
229 int pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
231 uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size);
232 int pci_count_lintr(void);
233 void pci_walk_lintr(pci_lintr_cb cb, void *arg);
234 void pci_write_dsdt(void);
237 pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val)
239 assert(offset <= PCI_REGMAX);
240 *(uint8_t *)(pi->pi_cfgdata + offset) = val;
244 pci_set_cfgdata16(struct pci_devinst *pi, int offset, uint16_t val)
246 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
247 *(uint16_t *)(pi->pi_cfgdata + offset) = val;
251 pci_set_cfgdata32(struct pci_devinst *pi, int offset, uint32_t val)
253 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);
254 *(uint32_t *)(pi->pi_cfgdata + offset) = val;
257 static __inline uint8_t
258 pci_get_cfgdata8(struct pci_devinst *pi, int offset)
260 assert(offset <= PCI_REGMAX);
261 return (*(uint8_t *)(pi->pi_cfgdata + offset));
264 static __inline uint16_t
265 pci_get_cfgdata16(struct pci_devinst *pi, int offset)
267 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
268 return (*(uint16_t *)(pi->pi_cfgdata + offset));
271 static __inline uint32_t
272 pci_get_cfgdata32(struct pci_devinst *pi, int offset)
274 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);
275 return (*(uint32_t *)(pi->pi_cfgdata + offset));
278 #endif /* _PCI_EMUL_H_ */