2 * Copyright (c) 2013 Neel Natu <neel@freebsd.org>
3 * Copyright (c) 2013 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/types.h>
34 #include <machine/vmm.h>
47 #include "uart_emul.h"
52 SET_DECLARE(lpc_dsdt_set, struct lpc_dsdt);
53 SET_DECLARE(lpc_sysres_set, struct lpc_sysres);
55 #define ELCR_PORT 0x4d0
56 SYSRES_IO(ELCR_PORT, 2);
58 #define IO_TIMER1_PORT 0x40
60 #define NMISC_PORT 0x61
61 SYSRES_IO(NMISC_PORT, 1);
63 static struct pci_devinst *lpc_bridge;
65 #define LPC_UART_NUM 2
66 static struct lpc_uart_softc {
67 struct uart_softc *uart_softc;
72 } lpc_uart_softc[LPC_UART_NUM];
74 static const char *lpc_uart_names[LPC_UART_NUM] = { "COM1", "COM2" };
77 * LPC device configuration is in the following form:
78 * <lpc_device_name>[,<options>]
79 * For e.g. "com1,stdio"
82 lpc_device_parse(const char *opts)
85 char *str, *cpy, *lpcdev;
88 str = cpy = strdup(opts);
89 lpcdev = strsep(&str, ",");
91 for (unit = 0; unit < LPC_UART_NUM; unit++) {
92 if (strcasecmp(lpcdev, lpc_uart_names[unit]) == 0) {
93 lpc_uart_softc[unit].opts = str;
108 lpc_uart_intr_assert(void *arg)
110 struct lpc_uart_softc *sc = arg;
112 assert(sc->irq >= 0);
114 vm_isa_pulse_irq(lpc_bridge->pi_vmctx, sc->irq, sc->irq);
118 lpc_uart_intr_deassert(void *arg)
121 * The COM devices on the LPC bus generate edge triggered interrupts,
122 * so nothing more to do here.
127 lpc_uart_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
128 uint32_t *eax, void *arg)
131 struct lpc_uart_softc *sc = arg;
133 offset = port - sc->iobase;
138 *eax = uart_read(sc->uart_softc, offset);
140 uart_write(sc->uart_softc, offset, *eax);
144 *eax = uart_read(sc->uart_softc, offset);
145 *eax |= uart_read(sc->uart_softc, offset + 1) << 8;
147 uart_write(sc->uart_softc, offset, *eax);
148 uart_write(sc->uart_softc, offset + 1, *eax >> 8);
161 struct lpc_uart_softc *sc;
162 struct inout_port iop;
167 for (unit = 0; unit < LPC_UART_NUM; unit++) {
168 sc = &lpc_uart_softc[unit];
169 name = lpc_uart_names[unit];
171 if (uart_legacy_alloc(unit, &sc->iobase, &sc->irq) != 0) {
172 fprintf(stderr, "Unable to allocate resources for "
173 "LPC device %s\n", name);
176 pci_irq_reserve(sc->irq);
178 sc->uart_softc = uart_init(lpc_uart_intr_assert,
179 lpc_uart_intr_deassert, sc);
181 if (uart_set_backend(sc->uart_softc, sc->opts) != 0) {
182 fprintf(stderr, "Unable to initialize backend '%s' "
183 "for LPC device %s\n", sc->opts, name);
187 bzero(&iop, sizeof(struct inout_port));
189 iop.port = sc->iobase;
190 iop.size = UART_IO_BAR_SIZE;
191 iop.flags = IOPORT_F_INOUT;
192 iop.handler = lpc_uart_io_handler;
195 error = register_inout(&iop);
204 pci_lpc_write_dsdt(struct pci_devinst *pi)
206 struct lpc_dsdt **ldpp, *ldp;
209 dsdt_line("Device (ISA)");
211 dsdt_line(" Name (_ADR, 0x%04X%04X)", pi->pi_slot, pi->pi_func);
212 dsdt_line(" OperationRegion (LPCR, PCI_Config, 0x00, 0x100)");
213 dsdt_line(" Field (LPCR, AnyAcc, NoLock, Preserve)");
215 dsdt_line(" Offset (0x60),");
216 dsdt_line(" PIRA, 8,");
217 dsdt_line(" PIRB, 8,");
218 dsdt_line(" PIRC, 8,");
219 dsdt_line(" PIRD, 8,");
220 dsdt_line(" Offset (0x68),");
221 dsdt_line(" PIRE, 8,");
222 dsdt_line(" PIRF, 8,");
223 dsdt_line(" PIRG, 8,");
224 dsdt_line(" PIRH, 8");
229 SET_FOREACH(ldpp, lpc_dsdt_set) {
235 dsdt_line("Device (PIC)");
237 dsdt_line(" Name (_HID, EisaId (\"PNP0000\"))");
238 dsdt_line(" Name (_CRS, ResourceTemplate ()");
241 dsdt_fixed_ioport(IO_ICU1, 2);
242 dsdt_fixed_ioport(IO_ICU2, 2);
249 dsdt_line("Device (TIMR)");
251 dsdt_line(" Name (_HID, EisaId (\"PNP0100\"))");
252 dsdt_line(" Name (_CRS, ResourceTemplate ()");
255 dsdt_fixed_ioport(IO_TIMER1_PORT, 4);
266 pci_lpc_sysres_dsdt(void)
268 struct lpc_sysres **lspp, *lsp;
271 dsdt_line("Device (SIO)");
273 dsdt_line(" Name (_HID, EisaId (\"PNP0C02\"))");
274 dsdt_line(" Name (_CRS, ResourceTemplate ()");
278 SET_FOREACH(lspp, lpc_sysres_set) {
282 dsdt_fixed_ioport(lsp->base, lsp->length);
285 dsdt_fixed_mem32(lsp->base, lsp->length);
294 LPC_DSDT(pci_lpc_sysres_dsdt);
297 pci_lpc_uart_dsdt(void)
299 struct lpc_uart_softc *sc;
302 for (unit = 0; unit < LPC_UART_NUM; unit++) {
303 sc = &lpc_uart_softc[unit];
307 dsdt_line("Device (%s)", lpc_uart_names[unit]);
309 dsdt_line(" Name (_HID, EisaId (\"PNP0501\"))");
310 dsdt_line(" Name (_UID, %d)", unit + 1);
311 dsdt_line(" Name (_CRS, ResourceTemplate ()");
314 dsdt_fixed_ioport(sc->iobase, UART_IO_BAR_SIZE);
315 dsdt_fixed_irq(sc->irq);
321 LPC_DSDT(pci_lpc_uart_dsdt);
324 pci_lpc_cfgwrite(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
325 int coff, int bytes, uint32_t val)
331 if (coff >= 0x60 && coff <= 0x63)
332 pirq_pin = coff - 0x60 + 1;
333 if (coff >= 0x68 && coff <= 0x6b)
334 pirq_pin = coff - 0x68 + 5;
336 pirq_write(ctx, pirq_pin, val);
337 pci_set_cfgdata8(pi, coff, pirq_read(pirq_pin));
345 pci_lpc_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
346 int baridx, uint64_t offset, int size, uint64_t value)
351 pci_lpc_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
352 int baridx, uint64_t offset, int size)
357 #define LPC_DEV 0x7000
358 #define LPC_VENDOR 0x8086
361 pci_lpc_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
365 * Do not allow more than one LPC bridge to be configured.
367 if (lpc_bridge != NULL) {
368 fprintf(stderr, "Only one LPC bridge is allowed.\n");
373 * Enforce that the LPC can only be configured on bus 0. This
374 * simplifies the ACPI DSDT because it can provide a decode for
375 * all legacy i/o ports behind bus 0.
377 if (pi->pi_bus != 0) {
378 fprintf(stderr, "LPC bridge can be present only on bus 0.\n");
385 /* initialize config space */
386 pci_set_cfgdata16(pi, PCIR_DEVICE, LPC_DEV);
387 pci_set_cfgdata16(pi, PCIR_VENDOR, LPC_VENDOR);
388 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_BRIDGE);
389 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_BRIDGE_ISA);
397 lpc_pirq_name(int pin)
401 if (lpc_bridge == NULL)
403 asprintf(&name, "\\_SB.PC00.ISA.LNK%c,", 'A' + pin - 1);
408 lpc_pirq_routed(void)
412 if (lpc_bridge == NULL)
415 for (pin = 0; pin < 4; pin++)
416 pci_set_cfgdata8(lpc_bridge, 0x60 + pin, pirq_read(pin + 1));
417 for (pin = 0; pin < 4; pin++)
418 pci_set_cfgdata8(lpc_bridge, 0x68 + pin, pirq_read(pin + 5));
421 struct pci_devemu pci_de_lpc = {
423 .pe_init = pci_lpc_init,
424 .pe_write_dsdt = pci_lpc_write_dsdt,
425 .pe_cfgwrite = pci_lpc_cfgwrite,
426 .pe_barwrite = pci_lpc_write,
427 .pe_barread = pci_lpc_read
429 PCI_EMUL_SET(pci_de_lpc);