2 * Copyright (c) 2013 Neel Natu <neel@freebsd.org>
3 * Copyright (c) 2013 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/types.h>
34 #include <machine/vmm.h>
35 #include <machine/vmm_dev.h>
48 #include "uart_emul.h"
53 SET_DECLARE(lpc_dsdt_set, struct lpc_dsdt);
54 SET_DECLARE(lpc_sysres_set, struct lpc_sysres);
56 #define ELCR_PORT 0x4d0
57 SYSRES_IO(ELCR_PORT, 2);
59 #define IO_TIMER1_PORT 0x40
61 #define NMISC_PORT 0x61
62 SYSRES_IO(NMISC_PORT, 1);
64 static struct pci_devinst *lpc_bridge;
66 #define LPC_UART_NUM 2
67 static struct lpc_uart_softc {
68 struct uart_softc *uart_softc;
73 } lpc_uart_softc[LPC_UART_NUM];
75 static const char *lpc_uart_names[LPC_UART_NUM] = { "COM1", "COM2" };
78 * LPC device configuration is in the following form:
79 * <lpc_device_name>[,<options>]
80 * For e.g. "com1,stdio"
83 lpc_device_parse(const char *opts)
86 char *str, *cpy, *lpcdev;
89 str = cpy = strdup(opts);
90 lpcdev = strsep(&str, ",");
92 for (unit = 0; unit < LPC_UART_NUM; unit++) {
93 if (strcasecmp(lpcdev, lpc_uart_names[unit]) == 0) {
94 lpc_uart_softc[unit].opts = str;
109 lpc_uart_intr_assert(void *arg)
111 struct lpc_uart_softc *sc = arg;
113 assert(sc->irq >= 0);
115 vm_isa_pulse_irq(lpc_bridge->pi_vmctx, sc->irq, sc->irq);
119 lpc_uart_intr_deassert(void *arg)
122 * The COM devices on the LPC bus generate edge triggered interrupts,
123 * so nothing more to do here.
128 lpc_uart_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
129 uint32_t *eax, void *arg)
132 struct lpc_uart_softc *sc = arg;
134 offset = port - sc->iobase;
139 *eax = uart_read(sc->uart_softc, offset);
141 uart_write(sc->uart_softc, offset, *eax);
145 *eax = uart_read(sc->uart_softc, offset);
146 *eax |= uart_read(sc->uart_softc, offset + 1) << 8;
148 uart_write(sc->uart_softc, offset, *eax);
149 uart_write(sc->uart_softc, offset + 1, *eax >> 8);
162 struct lpc_uart_softc *sc;
163 struct inout_port iop;
168 for (unit = 0; unit < LPC_UART_NUM; unit++) {
169 sc = &lpc_uart_softc[unit];
170 name = lpc_uart_names[unit];
172 if (uart_legacy_alloc(unit, &sc->iobase, &sc->irq) != 0) {
173 fprintf(stderr, "Unable to allocate resources for "
174 "LPC device %s\n", name);
177 pci_irq_reserve(sc->irq);
179 sc->uart_softc = uart_init(lpc_uart_intr_assert,
180 lpc_uart_intr_deassert, sc);
182 if (uart_set_backend(sc->uart_softc, sc->opts) != 0) {
183 fprintf(stderr, "Unable to initialize backend '%s' "
184 "for LPC device %s\n", sc->opts, name);
188 bzero(&iop, sizeof(struct inout_port));
190 iop.port = sc->iobase;
191 iop.size = UART_IO_BAR_SIZE;
192 iop.flags = IOPORT_F_INOUT;
193 iop.handler = lpc_uart_io_handler;
196 error = register_inout(&iop);
205 pci_lpc_write_dsdt(struct pci_devinst *pi)
207 struct lpc_dsdt **ldpp, *ldp;
210 dsdt_line("Device (ISA)");
212 dsdt_line(" Name (_ADR, 0x%04X%04X)", pi->pi_slot, pi->pi_func);
213 dsdt_line(" OperationRegion (LPCR, PCI_Config, 0x00, 0x100)");
214 dsdt_line(" Field (LPCR, AnyAcc, NoLock, Preserve)");
216 dsdt_line(" Offset (0x60),");
217 dsdt_line(" PIRA, 8,");
218 dsdt_line(" PIRB, 8,");
219 dsdt_line(" PIRC, 8,");
220 dsdt_line(" PIRD, 8,");
221 dsdt_line(" Offset (0x68),");
222 dsdt_line(" PIRE, 8,");
223 dsdt_line(" PIRF, 8,");
224 dsdt_line(" PIRG, 8,");
225 dsdt_line(" PIRH, 8");
230 SET_FOREACH(ldpp, lpc_dsdt_set) {
236 dsdt_line("Device (PIC)");
238 dsdt_line(" Name (_HID, EisaId (\"PNP0000\"))");
239 dsdt_line(" Name (_CRS, ResourceTemplate ()");
242 dsdt_fixed_ioport(IO_ICU1, 2);
243 dsdt_fixed_ioport(IO_ICU2, 2);
250 dsdt_line("Device (TIMR)");
252 dsdt_line(" Name (_HID, EisaId (\"PNP0100\"))");
253 dsdt_line(" Name (_CRS, ResourceTemplate ()");
256 dsdt_fixed_ioport(IO_TIMER1_PORT, 4);
267 pci_lpc_sysres_dsdt(void)
269 struct lpc_sysres **lspp, *lsp;
272 dsdt_line("Device (SIO)");
274 dsdt_line(" Name (_HID, EisaId (\"PNP0C02\"))");
275 dsdt_line(" Name (_CRS, ResourceTemplate ()");
279 SET_FOREACH(lspp, lpc_sysres_set) {
283 dsdt_fixed_ioport(lsp->base, lsp->length);
286 dsdt_fixed_mem32(lsp->base, lsp->length);
295 LPC_DSDT(pci_lpc_sysres_dsdt);
298 pci_lpc_uart_dsdt(void)
300 struct lpc_uart_softc *sc;
303 for (unit = 0; unit < LPC_UART_NUM; unit++) {
304 sc = &lpc_uart_softc[unit];
308 dsdt_line("Device (%s)", lpc_uart_names[unit]);
310 dsdt_line(" Name (_HID, EisaId (\"PNP0501\"))");
311 dsdt_line(" Name (_UID, %d)", unit + 1);
312 dsdt_line(" Name (_CRS, ResourceTemplate ()");
315 dsdt_fixed_ioport(sc->iobase, UART_IO_BAR_SIZE);
316 dsdt_fixed_irq(sc->irq);
322 LPC_DSDT(pci_lpc_uart_dsdt);
325 pci_lpc_cfgwrite(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
326 int coff, int bytes, uint32_t val)
332 if (coff >= 0x60 && coff <= 0x63)
333 pirq_pin = coff - 0x60 + 1;
334 if (coff >= 0x68 && coff <= 0x6b)
335 pirq_pin = coff - 0x68 + 5;
337 pirq_write(ctx, pirq_pin, val);
338 pci_set_cfgdata8(pi, coff, pirq_read(pirq_pin));
346 pci_lpc_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
347 int baridx, uint64_t offset, int size, uint64_t value)
352 pci_lpc_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
353 int baridx, uint64_t offset, int size)
358 #define LPC_DEV 0x7000
359 #define LPC_VENDOR 0x8086
362 pci_lpc_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
366 * Do not allow more than one LPC bridge to be configured.
368 if (lpc_bridge != NULL) {
369 fprintf(stderr, "Only one LPC bridge is allowed.\n");
374 * Enforce that the LPC can only be configured on bus 0. This
375 * simplifies the ACPI DSDT because it can provide a decode for
376 * all legacy i/o ports behind bus 0.
378 if (pi->pi_bus != 0) {
379 fprintf(stderr, "LPC bridge can be present only on bus 0.\n");
386 /* initialize config space */
387 pci_set_cfgdata16(pi, PCIR_DEVICE, LPC_DEV);
388 pci_set_cfgdata16(pi, PCIR_VENDOR, LPC_VENDOR);
389 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_BRIDGE);
390 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_BRIDGE_ISA);
398 lpc_pirq_name(int pin)
402 if (lpc_bridge == NULL)
404 asprintf(&name, "\\_SB.PC00.ISA.LNK%c,", 'A' + pin - 1);
409 lpc_pirq_routed(void)
413 if (lpc_bridge == NULL)
416 for (pin = 0; pin < 4; pin++)
417 pci_set_cfgdata8(lpc_bridge, 0x60 + pin, pirq_read(pin + 1));
418 for (pin = 0; pin < 4; pin++)
419 pci_set_cfgdata8(lpc_bridge, 0x68 + pin, pirq_read(pin + 5));
422 struct pci_devemu pci_de_lpc = {
424 .pe_init = pci_lpc_init,
425 .pe_write_dsdt = pci_lpc_write_dsdt,
426 .pe_cfgwrite = pci_lpc_cfgwrite,
427 .pe_barwrite = pci_lpc_write,
428 .pe_barread = pci_lpc_read
430 PCI_EMUL_SET(pci_de_lpc);