2 * Copyright (c) 2011 NetApp, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/types.h>
35 #include <sys/pciio.h>
36 #include <sys/ioctl.h>
38 #include <dev/io/iodev.h>
39 #include <dev/pci/pcireg.h>
41 #include <machine/iodev.h>
50 #include <machine/vmm.h>
56 #define _PATH_DEVPCI "/dev/pci"
60 #define _PATH_DEVIO "/dev/io"
64 #define _PATH_MEM "/dev/mem"
67 #define LEGACY_SUPPORT 1
69 #define MSIX_TABLE_COUNT(ctrl) (((ctrl) & PCIM_MSIXCTRL_TABLE_SIZE) + 1)
70 #define MSIX_CAPLEN 12
72 static int pcifd = -1;
74 static int memfd = -1;
76 struct passthru_softc {
77 struct pci_devinst *psc_pi;
78 struct pcibar psc_bar[PCI_BARMAX + 1];
87 struct pcisel psc_sel;
91 msi_caplen(int msgctrl)
95 len = 10; /* minimum length of msi capability */
97 if (msgctrl & PCIM_MSICTRL_64BIT)
102 * Ignore the 'mask' and 'pending' bits in the MSI capability.
103 * We'll let the guest manipulate them directly.
105 if (msgctrl & PCIM_MSICTRL_VECTOR)
113 read_config(const struct pcisel *sel, long reg, int width)
117 bzero(&pi, sizeof(pi));
122 if (ioctl(pcifd, PCIOCREAD, &pi) < 0)
123 return (0); /* XXX */
129 write_config(const struct pcisel *sel, long reg, int width, uint32_t data)
133 bzero(&pi, sizeof(pi));
139 (void)ioctl(pcifd, PCIOCWRITE, &pi); /* XXX */
142 #ifdef LEGACY_SUPPORT
144 passthru_add_msicap(struct pci_devinst *pi, int msgnum, int nextptr)
147 struct msicap msicap;
150 pci_populate_msicap(&msicap, msgnum, nextptr);
154 * Copy the msi capability structure in the last 16 bytes of the
155 * config space. This is wrong because it could shadow something
156 * useful to the device.
158 capoff = 256 - roundup(sizeof(msicap), 4);
159 capdata = (u_char *)&msicap;
160 for (i = 0; i < sizeof(msicap); i++)
161 pci_set_cfgdata8(pi, capoff + i, capdata[i]);
165 #endif /* LEGACY_SUPPORT */
168 cfginitmsi(struct passthru_softc *sc)
170 int i, ptr, capptr, cap, sts, caplen, table_size;
173 struct pci_devinst *pi;
174 struct msixcap msixcap;
175 uint32_t *msixcap_ptr;
181 * Parse the capabilities and cache the location of the MSI
182 * and MSI-X capabilities.
184 sts = read_config(&sel, PCIR_STATUS, 2);
185 if (sts & PCIM_STATUS_CAPPRESENT) {
186 ptr = read_config(&sel, PCIR_CAP_PTR, 1);
187 while (ptr != 0 && ptr != 0xff) {
188 cap = read_config(&sel, ptr + PCICAP_ID, 1);
189 if (cap == PCIY_MSI) {
191 * Copy the MSI capability into the config
192 * space of the emulated pci device
194 sc->psc_msi.capoff = ptr;
195 sc->psc_msi.msgctrl = read_config(&sel,
197 sc->psc_msi.emulated = 0;
198 caplen = msi_caplen(sc->psc_msi.msgctrl);
201 u32 = read_config(&sel, capptr, 4);
202 pci_set_cfgdata32(pi, capptr, u32);
206 } else if (cap == PCIY_MSIX) {
208 * Copy the MSI-X capability
210 sc->psc_msix.capoff = ptr;
212 msixcap_ptr = (uint32_t*) &msixcap;
215 u32 = read_config(&sel, capptr, 4);
217 pci_set_cfgdata32(pi, capptr, u32);
223 ptr = read_config(&sel, ptr + PCICAP_NEXTPTR, 1);
227 if (sc->psc_msix.capoff != 0) {
228 pi->pi_msix.pba_bar =
229 msixcap.pba_info & PCIM_MSIX_BIR_MASK;
230 pi->pi_msix.pba_offset =
231 msixcap.pba_info & ~PCIM_MSIX_BIR_MASK;
232 pi->pi_msix.table_bar =
233 msixcap.table_info & PCIM_MSIX_BIR_MASK;
234 pi->pi_msix.table_offset =
235 msixcap.table_info & ~PCIM_MSIX_BIR_MASK;
236 pi->pi_msix.table_count = MSIX_TABLE_COUNT(msixcap.msgctrl);
237 pi->pi_msix.pba_size = PBA_SIZE(pi->pi_msix.table_count);
239 /* Allocate the emulated MSI-X table array */
240 table_size = pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
241 pi->pi_msix.table = calloc(1, table_size);
243 /* Mask all table entries */
244 for (i = 0; i < pi->pi_msix.table_count; i++) {
245 pi->pi_msix.table[i].vector_control |=
246 PCIM_MSIX_VCTRL_MASK;
250 #ifdef LEGACY_SUPPORT
252 * If the passthrough device does not support MSI then craft a
253 * MSI capability for it. We link the new MSI capability at the
254 * head of the list of capabilities.
256 if ((sts & PCIM_STATUS_CAPPRESENT) != 0 && sc->psc_msi.capoff == 0) {
258 origptr = read_config(&sel, PCIR_CAP_PTR, 1);
259 msiptr = passthru_add_msicap(pi, 1, origptr);
260 sc->psc_msi.capoff = msiptr;
261 sc->psc_msi.msgctrl = pci_get_cfgdata16(pi, msiptr + 2);
262 sc->psc_msi.emulated = 1;
263 pci_set_cfgdata8(pi, PCIR_CAP_PTR, msiptr);
267 /* Make sure one of the capabilities is present */
268 if (sc->psc_msi.capoff == 0 && sc->psc_msix.capoff == 0)
275 msix_table_read(struct passthru_softc *sc, uint64_t offset, int size)
277 struct pci_devinst *pi;
278 struct msix_table_entry *entry;
288 if (offset >= pi->pi_msix.pba_offset &&
289 offset < pi->pi_msix.pba_offset + pi->pi_msix.pba_size) {
292 src8 = (uint8_t *)(pi->pi_msix.pba_page + offset -
293 pi->pi_msix.pba_page_offset);
297 src16 = (uint16_t *)(pi->pi_msix.pba_page + offset -
298 pi->pi_msix.pba_page_offset);
302 src32 = (uint32_t *)(pi->pi_msix.pba_page + offset -
303 pi->pi_msix.pba_page_offset);
307 src64 = (uint64_t *)(pi->pi_msix.pba_page + offset -
308 pi->pi_msix.pba_page_offset);
317 if (offset < pi->pi_msix.table_offset)
320 offset -= pi->pi_msix.table_offset;
321 index = offset / MSIX_TABLE_ENTRY_SIZE;
322 if (index >= pi->pi_msix.table_count)
325 entry = &pi->pi_msix.table[index];
326 entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
330 src8 = (uint8_t *)((void *)entry + entry_offset);
334 src16 = (uint16_t *)((void *)entry + entry_offset);
338 src32 = (uint32_t *)((void *)entry + entry_offset);
342 src64 = (uint64_t *)((void *)entry + entry_offset);
353 msix_table_write(struct vmctx *ctx, int vcpu, struct passthru_softc *sc,
354 uint64_t offset, int size, uint64_t data)
356 struct pci_devinst *pi;
357 struct msix_table_entry *entry;
363 uint32_t vector_control;
367 if (offset >= pi->pi_msix.pba_offset &&
368 offset < pi->pi_msix.pba_offset + pi->pi_msix.pba_size) {
371 dest8 = (uint8_t *)(pi->pi_msix.pba_page + offset -
372 pi->pi_msix.pba_page_offset);
376 dest16 = (uint16_t *)(pi->pi_msix.pba_page + offset -
377 pi->pi_msix.pba_page_offset);
381 dest32 = (uint32_t *)(pi->pi_msix.pba_page + offset -
382 pi->pi_msix.pba_page_offset);
386 dest64 = (uint64_t *)(pi->pi_msix.pba_page + offset -
387 pi->pi_msix.pba_page_offset);
396 if (offset < pi->pi_msix.table_offset)
399 offset -= pi->pi_msix.table_offset;
400 index = offset / MSIX_TABLE_ENTRY_SIZE;
401 if (index >= pi->pi_msix.table_count)
404 entry = &pi->pi_msix.table[index];
405 entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
407 /* Only 4 byte naturally-aligned writes are supported */
409 assert(entry_offset % 4 == 0);
411 vector_control = entry->vector_control;
412 dest32 = (uint32_t *)((void *)entry + entry_offset);
414 /* If MSI-X hasn't been enabled, do nothing */
415 if (pi->pi_msix.enabled) {
416 /* If the entry is masked, don't set it up */
417 if ((entry->vector_control & PCIM_MSIX_VCTRL_MASK) == 0 ||
418 (vector_control & PCIM_MSIX_VCTRL_MASK) == 0) {
419 (void)vm_setup_pptdev_msix(ctx, vcpu,
420 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
421 sc->psc_sel.pc_func, index, entry->addr,
422 entry->msg_data, entry->vector_control);
428 init_msix_table(struct vmctx *ctx, struct passthru_softc *sc, uint64_t base)
432 size_t len, remaining;
433 uint32_t table_size, table_offset;
434 uint32_t pba_size, pba_offset;
436 struct pci_devinst *pi = sc->psc_pi;
438 assert(pci_msix_table_bar(pi) >= 0 && pci_msix_pba_bar(pi) >= 0);
440 b = sc->psc_sel.pc_bus;
441 s = sc->psc_sel.pc_dev;
442 f = sc->psc_sel.pc_func;
445 * If the MSI-X table BAR maps memory intended for
446 * other uses, it is at least assured that the table
447 * either resides in its own page within the region,
448 * or it resides in a page shared with only the PBA.
450 table_offset = rounddown2(pi->pi_msix.table_offset, 4096);
452 table_size = pi->pi_msix.table_offset - table_offset;
453 table_size += pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
454 table_size = roundup2(table_size, 4096);
456 idx = pi->pi_msix.table_bar;
457 start = pi->pi_bar[idx].addr;
458 remaining = pi->pi_bar[idx].size;
460 if (pi->pi_msix.pba_bar == pi->pi_msix.table_bar) {
461 pba_offset = pi->pi_msix.pba_offset;
462 pba_size = pi->pi_msix.pba_size;
463 if (pba_offset >= table_offset + table_size ||
464 table_offset >= pba_offset + pba_size) {
466 * If the PBA does not share a page with the MSI-x
467 * tables, no PBA emulation is required.
469 pi->pi_msix.pba_page = NULL;
470 pi->pi_msix.pba_page_offset = 0;
473 * The PBA overlaps with either the first or last
474 * page of the MSI-X table region. Map the
477 if (pba_offset <= table_offset)
478 pi->pi_msix.pba_page_offset = table_offset;
480 pi->pi_msix.pba_page_offset = table_offset +
482 pi->pi_msix.pba_page = mmap(NULL, 4096, PROT_READ |
483 PROT_WRITE, MAP_SHARED, memfd, start +
484 pi->pi_msix.pba_page_offset);
485 if (pi->pi_msix.pba_page == MAP_FAILED) {
487 "Failed to map PBA page for MSI-X on %d/%d/%d",
494 /* Map everything before the MSI-X table */
495 if (table_offset > 0) {
497 error = vm_map_pptdev_mmio(ctx, b, s, f, start, len, base);
506 /* Skip the MSI-X table */
509 remaining -= table_size;
511 /* Map everything beyond the end of the MSI-X table */
514 error = vm_map_pptdev_mmio(ctx, b, s, f, start, len, base);
523 cfginitbar(struct vmctx *ctx, struct passthru_softc *sc)
526 struct pci_devinst *pi;
527 struct pci_bar_io bar;
528 enum pcibar_type bartype;
534 * Initialize BAR registers
536 for (i = 0; i <= PCI_BARMAX; i++) {
537 bzero(&bar, sizeof(bar));
538 bar.pbi_sel = sc->psc_sel;
539 bar.pbi_reg = PCIR_BAR(i);
541 if (ioctl(pcifd, PCIOCGETBAR, &bar) < 0)
544 if (PCI_BAR_IO(bar.pbi_base)) {
546 base = bar.pbi_base & PCIM_BAR_IO_BASE;
548 switch (bar.pbi_base & PCIM_BAR_MEM_TYPE) {
549 case PCIM_BAR_MEM_64:
550 bartype = PCIBAR_MEM64;
553 bartype = PCIBAR_MEM32;
556 base = bar.pbi_base & PCIM_BAR_MEM_BASE;
558 size = bar.pbi_length;
560 if (bartype != PCIBAR_IO) {
561 if (((base | size) & PAGE_MASK) != 0) {
562 warnx("passthru device %d/%d/%d BAR %d: "
563 "base %#lx or size %#lx not page aligned\n",
564 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
565 sc->psc_sel.pc_func, i, base, size);
570 /* Cache information about the "real" BAR */
571 sc->psc_bar[i].type = bartype;
572 sc->psc_bar[i].size = size;
573 sc->psc_bar[i].addr = base;
575 /* Allocate the BAR in the guest I/O or MMIO space */
576 error = pci_emul_alloc_pbar(pi, i, base, bartype, size);
580 /* The MSI-X table needs special handling */
581 if (i == pci_msix_table_bar(pi)) {
582 error = init_msix_table(ctx, sc, base);
585 } else if (bartype != PCIBAR_IO) {
586 /* Map the physical BAR in the guest MMIO space */
587 error = vm_map_pptdev_mmio(ctx, sc->psc_sel.pc_bus,
588 sc->psc_sel.pc_dev, sc->psc_sel.pc_func,
589 pi->pi_bar[i].addr, pi->pi_bar[i].size, base);
595 * 64-bit BAR takes up two slots so skip the next one.
597 if (bartype == PCIBAR_MEM64) {
599 assert(i <= PCI_BARMAX);
600 sc->psc_bar[i].type = PCIBAR_MEMHI64;
607 cfginit(struct vmctx *ctx, struct pci_devinst *pi, int bus, int slot, int func)
610 struct passthru_softc *sc;
615 bzero(&sc->psc_sel, sizeof(struct pcisel));
616 sc->psc_sel.pc_bus = bus;
617 sc->psc_sel.pc_dev = slot;
618 sc->psc_sel.pc_func = func;
620 if (cfginitmsi(sc) != 0) {
621 warnx("failed to initialize MSI for PCI %d/%d/%d",
626 if (cfginitbar(ctx, sc) != 0) {
627 warnx("failed to initialize BARs for PCI %d/%d/%d",
632 error = 0; /* success */
638 passthru_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
640 int bus, slot, func, error, memflags;
641 struct passthru_softc *sc;
646 memflags = vm_get_memflags(ctx);
647 if (!(memflags & VM_MEM_F_WIRED)) {
648 warnx("passthru requires guest memory to be wired");
653 pcifd = open(_PATH_DEVPCI, O_RDWR, 0);
655 warn("failed to open %s", _PATH_DEVPCI);
661 iofd = open(_PATH_DEVIO, O_RDWR, 0);
663 warn("failed to open %s", _PATH_DEVIO);
669 memfd = open(_PATH_MEM, O_RDWR, 0);
671 warn("failed to open %s", _PATH_MEM);
677 sscanf(opts, "%d/%d/%d", &bus, &slot, &func) != 3) {
678 warnx("invalid passthru options");
682 if (vm_assign_pptdev(ctx, bus, slot, func) != 0) {
683 warnx("PCI device at %d/%d/%d is not using the ppt(4) driver",
688 sc = calloc(1, sizeof(struct passthru_softc));
693 /* initialize config space */
694 if ((error = cfginit(ctx, pi, bus, slot, func)) != 0)
697 error = 0; /* success */
701 vm_unassign_pptdev(ctx, bus, slot, func);
709 if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1))
716 msicap_access(struct passthru_softc *sc, int coff)
720 if (sc->psc_msi.capoff == 0)
723 caplen = msi_caplen(sc->psc_msi.msgctrl);
725 if (coff >= sc->psc_msi.capoff && coff < sc->psc_msi.capoff + caplen)
732 msixcap_access(struct passthru_softc *sc, int coff)
734 if (sc->psc_msix.capoff == 0)
737 return (coff >= sc->psc_msix.capoff &&
738 coff < sc->psc_msix.capoff + MSIX_CAPLEN);
742 passthru_cfgread(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
743 int coff, int bytes, uint32_t *rv)
745 struct passthru_softc *sc;
750 * PCI BARs and MSI capability is emulated.
752 if (bar_access(coff) || msicap_access(sc, coff))
755 #ifdef LEGACY_SUPPORT
757 * Emulate PCIR_CAP_PTR if this device does not support MSI capability
760 if (sc->psc_msi.emulated) {
761 if (coff >= PCIR_CAP_PTR && coff < PCIR_CAP_PTR + 4)
766 /* Everything else just read from the device's config space */
767 *rv = read_config(&sc->psc_sel, coff, bytes);
773 passthru_cfgwrite(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
774 int coff, int bytes, uint32_t val)
776 int error, msix_table_entries, i;
777 struct passthru_softc *sc;
782 * PCI BARs are emulated
784 if (bar_access(coff))
788 * MSI capability is emulated
790 if (msicap_access(sc, coff)) {
791 msicap_cfgwrite(pi, sc->psc_msi.capoff, coff, bytes, val);
793 error = vm_setup_pptdev_msi(ctx, vcpu, sc->psc_sel.pc_bus,
794 sc->psc_sel.pc_dev, sc->psc_sel.pc_func,
795 pi->pi_msi.addr, pi->pi_msi.msg_data,
796 pi->pi_msi.maxmsgnum);
798 err(1, "vm_setup_pptdev_msi");
802 if (msixcap_access(sc, coff)) {
803 msixcap_cfgwrite(pi, sc->psc_msix.capoff, coff, bytes, val);
804 if (pi->pi_msix.enabled) {
805 msix_table_entries = pi->pi_msix.table_count;
806 for (i = 0; i < msix_table_entries; i++) {
807 error = vm_setup_pptdev_msix(ctx, vcpu,
808 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
809 sc->psc_sel.pc_func, i,
810 pi->pi_msix.table[i].addr,
811 pi->pi_msix.table[i].msg_data,
812 pi->pi_msix.table[i].vector_control);
815 err(1, "vm_setup_pptdev_msix");
821 #ifdef LEGACY_SUPPORT
823 * If this device does not support MSI natively then we cannot let
824 * the guest disable legacy interrupts from the device. It is the
825 * legacy interrupt that is triggering the virtual MSI to the guest.
827 if (sc->psc_msi.emulated && pci_msi_enabled(pi)) {
828 if (coff == PCIR_COMMAND && bytes == 2)
829 val &= ~PCIM_CMD_INTxDIS;
833 write_config(&sc->psc_sel, coff, bytes, val);
839 passthru_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
840 uint64_t offset, int size, uint64_t value)
842 struct passthru_softc *sc;
843 struct iodev_pio_req pio;
847 if (baridx == pci_msix_table_bar(pi)) {
848 msix_table_write(ctx, vcpu, sc, offset, size, value);
850 assert(pi->pi_bar[baridx].type == PCIBAR_IO);
851 bzero(&pio, sizeof(struct iodev_pio_req));
852 pio.access = IODEV_PIO_WRITE;
853 pio.port = sc->psc_bar[baridx].addr + offset;
857 (void)ioctl(iofd, IODEV_PIO, &pio);
862 passthru_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
863 uint64_t offset, int size)
865 struct passthru_softc *sc;
866 struct iodev_pio_req pio;
871 if (baridx == pci_msix_table_bar(pi)) {
872 val = msix_table_read(sc, offset, size);
874 assert(pi->pi_bar[baridx].type == PCIBAR_IO);
875 bzero(&pio, sizeof(struct iodev_pio_req));
876 pio.access = IODEV_PIO_READ;
877 pio.port = sc->psc_bar[baridx].addr + offset;
881 (void)ioctl(iofd, IODEV_PIO, &pio);
889 struct pci_devemu passthru = {
890 .pe_emu = "passthru",
891 .pe_init = passthru_init,
892 .pe_cfgwrite = passthru_cfgwrite,
893 .pe_cfgread = passthru_cfgread,
894 .pe_barwrite = passthru_write,
895 .pe_barread = passthru_read,
897 PCI_EMUL_SET(passthru);