2 * Copyright (c) 2011 NetApp, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/types.h>
34 #include <machine/vmm.h>
36 #include <machine/clock.h>
52 #define TIMER_SEL_MASK 0xc0
53 #define TIMER_RW_MASK 0x30
54 #define TIMER_MODE_MASK 0x0f
55 #define TIMER_SEL_READBACK 0xc0
57 #define TIMER_DIV(freq, hz) (((freq) + (hz) / 2) / (hz))
59 #define PIT_8254_FREQ 1193182
60 static const int nsecs_per_tick = 1000000000 / PIT_8254_FREQ;
65 struct timeval tv; /* uptime when counter was loaded */
67 uint16_t initial; /* initial counter value */
77 timevalfix(struct timeval *t1)
80 if (t1->tv_usec < 0) {
82 t1->tv_usec += 1000000;
84 if (t1->tv_usec >= 1000000) {
86 t1->tv_usec -= 1000000;
91 timevalsub(struct timeval *t1, const struct timeval *t2)
94 t1->tv_sec -= t2->tv_sec;
95 t1->tv_usec -= t2->tv_usec;
99 static uint64_t pit_mev_count;
102 pit_mevent_cb(int fd, enum ev_type type, void *param)
110 vm_ioapic_pulse_irq(c->ctx, 2);
113 * Delete the timer for one-shots
115 if (c->mode != TIMER_RATEGEN) {
116 mevent_delete(c->tevp);
122 pit_timer_start(struct vmctx *ctx, struct counter *c)
126 if (c->initial != 0) {
127 msecs = c->initial * nsecs_per_tick / 1000000;
132 c->tevp = mevent_add(msecs, EVF_TIMER, pit_mevent_cb,
138 pit_update_counter(struct counter *c, int latch)
142 uint64_t delta_nsecs, delta_ticks;
144 /* cannot latch a new value until the old one has been consumed */
145 if (latch && c->olbyte != 0)
148 if (c->initial == 0 || c->initial == 1) {
150 * XXX the program that runs the VM can be stopped and
151 * restarted at any time. This means that state that was
152 * created by the guest is destroyed between invocations
155 * If the counter's initial value is not programmed we
156 * assume a value that would be set to generate 100
157 * interrupts per second.
159 c->initial = TIMER_DIV(PIT_8254_FREQ, 100);
160 gettimeofday(&c->tv, NULL);
163 (void)gettimeofday(&tv2, NULL);
164 timevalsub(&tv2, &c->tv);
165 delta_nsecs = tv2.tv_sec * 1000000000 + tv2.tv_usec * 1000;
166 delta_ticks = delta_nsecs / nsecs_per_tick;
168 lval = c->initial - delta_ticks % c->initial;
172 c->ol[1] = lval; /* LSB */
173 c->ol[0] = lval >> 8; /* MSB */
180 pit_8254_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
181 uint32_t *eax, void *arg)
187 static struct counter counter[3];
194 if (port == TIMER_MODE) {
196 sel = val & TIMER_SEL_MASK;
197 rw = val & TIMER_RW_MASK;
198 mode = val & TIMER_MODE_MASK;
200 if (sel == TIMER_SEL_READBACK)
202 if (rw != TIMER_LATCH && rw != TIMER_16BIT)
205 if (rw != TIMER_LATCH) {
207 * Counter mode is not affected when issuing a
210 if (mode != TIMER_INTTC &&
211 mode != TIMER_RATEGEN &&
212 mode != TIMER_SQWAVE &&
213 mode != TIMER_SWSTROBE)
217 c = &counter[sel >> 6];
220 if (rw == TIMER_LATCH)
221 pit_update_counter(c, 1);
223 c->olbyte = 0; /* reset latch after reprogramming */
229 assert(port >= TIMER_CNTR0 && port <= TIMER_CNTR2);
230 c = &counter[port - TIMER_CNTR0];
234 * The spec says that once the output latch is completely
235 * read it should revert to "following" the counter. Use
236 * the free running counter for this case (i.e. Linux
237 * TSC calibration). Assuming the access mode is 16-bit,
238 * toggle the MSB/LSB bit on each read.
240 if (c->olbyte == 0) {
243 tmp = pit_update_counter(c, 0);
250 *eax = c->ol[--c->olbyte];
252 c->cr[c->crbyte++] = *eax;
253 if (c->crbyte == 2) {
256 c->initial = c->cr[0] | (uint16_t)c->cr[1] << 8;
257 /* Start an interval timer for counter 0 */
259 pit_timer_start(ctx, c);
262 gettimeofday(&c->tv, NULL);
269 INOUT_PORT(8254, TIMER_MODE, IOPORT_F_OUT, pit_8254_handler);
270 INOUT_PORT(8254, TIMER_CNTR0, IOPORT_F_INOUT, pit_8254_handler);
271 INOUT_PORT(8254, TIMER_CNTR1, IOPORT_F_INOUT, pit_8254_handler);
272 INOUT_PORT(8254, TIMER_CNTR2, IOPORT_F_INOUT, pit_8254_handler);
279 dsdt_line("Device (TIMR)");
281 dsdt_line(" Name (_HID, EisaId (\"PNP0100\"))");
282 dsdt_line(" Name (_CRS, ResourceTemplate ()");
285 dsdt_fixed_ioport(IO_TIMER1, 4);