2 * Copyright (c) 2014 Neel Natu <neel@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/_iovec.h>
35 #include <x86/segments.h>
36 #include <x86/specialreg.h>
37 #include <machine/vmm.h>
38 #include <machine/vmm_instruction_emul.h>
51 * Using 'struct i386tss' is tempting but causes myriad sign extension
52 * issues because all of its fields are defined as signed integers.
94 static_assert(sizeof(struct tss32) == 104, "compile-time assertion failed");
96 #define SEL_START(sel) (((sel) & ~0x7))
97 #define SEL_LIMIT(sel) (((sel) | 0x7))
98 #define TSS_BUSY(type) (((type) & 0x2) != 0)
101 GETREG(struct vmctx *ctx, int vcpu, int reg)
106 error = vm_get_register(ctx, vcpu, reg, &val);
112 SETREG(struct vmctx *ctx, int vcpu, int reg, uint64_t val)
116 error = vm_set_register(ctx, vcpu, reg, val);
120 static struct seg_desc
121 usd_to_seg_desc(struct user_segment_descriptor *usd)
123 struct seg_desc seg_desc;
125 seg_desc.base = (u_int)USD_GETBASE(usd);
127 seg_desc.limit = (u_int)(USD_GETLIMIT(usd) << 12) | 0xfff;
129 seg_desc.limit = (u_int)USD_GETLIMIT(usd);
130 seg_desc.access = usd->sd_type | usd->sd_dpl << 5 | usd->sd_p << 7;
131 seg_desc.access |= usd->sd_xx << 12;
132 seg_desc.access |= usd->sd_def32 << 14;
133 seg_desc.access |= usd->sd_gran << 15;
139 * Inject an exception with an error code that is a segment selector.
140 * The format of the error code is described in section 6.13, "Error Code",
141 * Intel SDM volume 3.
143 * Bit 0 (EXT) denotes whether the exception occurred during delivery
144 * of an external event like an interrupt.
146 * Bit 1 (IDT) indicates whether the selector points to a gate descriptor
149 * Bit 2(GDT/LDT) has the usual interpretation of Table Indicator (TI).
152 sel_exception(struct vmctx *ctx, int vcpu, int vector, uint16_t sel, int ext)
155 * Bit 2 from the selector is retained as-is in the error code.
157 * Bit 1 can be safely cleared because none of the selectors
158 * encountered during task switch emulation refer to a task
161 * Bit 0 is set depending on the value of 'ext'.
166 vm_inject_fault(ctx, vcpu, vector, 1, sel);
170 * Return 0 if the selector 'sel' in within the limits of the GDT/LDT
171 * and non-zero otherwise.
174 desc_table_limit_check(struct vmctx *ctx, int vcpu, uint16_t sel)
177 uint32_t limit, access;
180 reg = ISLDT(sel) ? VM_REG_GUEST_LDTR : VM_REG_GUEST_GDTR;
181 error = vm_get_desc(ctx, vcpu, reg, &base, &limit, &access);
184 if (reg == VM_REG_GUEST_LDTR) {
185 if (SEG_DESC_UNUSABLE(access) || !SEG_DESC_PRESENT(access))
189 if (limit < SEL_LIMIT(sel))
196 * Read/write the segment descriptor 'desc' into the GDT/LDT slot referenced
197 * by the selector 'sel'.
199 * Returns 0 on success.
200 * Returns 1 if an exception was injected into the guest.
201 * Returns -1 otherwise.
204 desc_table_rw(struct vmctx *ctx, int vcpu, struct vm_guest_paging *paging,
205 uint16_t sel, struct user_segment_descriptor *desc, bool doread,
210 uint32_t limit, access;
213 reg = ISLDT(sel) ? VM_REG_GUEST_LDTR : VM_REG_GUEST_GDTR;
214 error = vm_get_desc(ctx, vcpu, reg, &base, &limit, &access);
216 assert(limit >= SEL_LIMIT(sel));
218 error = vm_copy_setup(ctx, vcpu, paging, base + SEL_START(sel),
219 sizeof(*desc), doread ? PROT_READ : PROT_WRITE, iov, nitems(iov),
221 if (error || *faultptr)
225 vm_copyin(ctx, vcpu, iov, desc, sizeof(*desc));
227 vm_copyout(ctx, vcpu, desc, iov, sizeof(*desc));
232 desc_table_read(struct vmctx *ctx, int vcpu, struct vm_guest_paging *paging,
233 uint16_t sel, struct user_segment_descriptor *desc, int *faultptr)
235 return (desc_table_rw(ctx, vcpu, paging, sel, desc, true, faultptr));
239 desc_table_write(struct vmctx *ctx, int vcpu, struct vm_guest_paging *paging,
240 uint16_t sel, struct user_segment_descriptor *desc, int *faultptr)
242 return (desc_table_rw(ctx, vcpu, paging, sel, desc, false, faultptr));
246 * Read the TSS descriptor referenced by 'sel' into 'desc'.
248 * Returns 0 on success.
249 * Returns 1 if an exception was injected into the guest.
250 * Returns -1 otherwise.
253 read_tss_descriptor(struct vmctx *ctx, int vcpu, struct vm_task_switch *ts,
254 uint16_t sel, struct user_segment_descriptor *desc, int *faultptr)
256 struct vm_guest_paging sup_paging;
260 assert(IDXSEL(sel) != 0);
262 /* Fetch the new TSS descriptor */
263 if (desc_table_limit_check(ctx, vcpu, sel)) {
264 if (ts->reason == TSR_IRET)
265 sel_exception(ctx, vcpu, IDT_TS, sel, ts->ext);
267 sel_exception(ctx, vcpu, IDT_GP, sel, ts->ext);
271 sup_paging = ts->paging;
272 sup_paging.cpl = 0; /* implicit supervisor mode */
273 error = desc_table_read(ctx, vcpu, &sup_paging, sel, desc, faultptr);
278 code_desc(int sd_type)
280 /* code descriptor */
281 return ((sd_type & 0x18) == 0x18);
285 stack_desc(int sd_type)
287 /* writable data descriptor */
288 return ((sd_type & 0x1A) == 0x12);
292 data_desc(int sd_type)
294 /* data descriptor or a readable code descriptor */
295 return ((sd_type & 0x18) == 0x10 || (sd_type & 0x1A) == 0x1A);
299 ldt_desc(int sd_type)
302 return (sd_type == SDT_SYSLDT);
306 * Validate the descriptor 'seg_desc' associated with 'segment'.
309 validate_seg_desc(struct vmctx *ctx, int vcpu, struct vm_task_switch *ts,
310 int segment, struct seg_desc *seg_desc, int *faultptr)
312 struct vm_guest_paging sup_paging;
313 struct user_segment_descriptor usd;
317 bool ldtseg, codeseg, stackseg, dataseg, conforming;
319 ldtseg = codeseg = stackseg = dataseg = false;
321 case VM_REG_GUEST_LDTR:
324 case VM_REG_GUEST_CS:
327 case VM_REG_GUEST_SS:
330 case VM_REG_GUEST_DS:
331 case VM_REG_GUEST_ES:
332 case VM_REG_GUEST_FS:
333 case VM_REG_GUEST_GS:
340 /* Get the segment selector */
341 sel = GETREG(ctx, vcpu, segment);
343 /* LDT selector must point into the GDT */
344 if (ldtseg && ISLDT(sel)) {
345 sel_exception(ctx, vcpu, IDT_TS, sel, ts->ext);
349 /* Descriptor table limit check */
350 if (desc_table_limit_check(ctx, vcpu, sel)) {
351 sel_exception(ctx, vcpu, IDT_TS, sel, ts->ext);
356 if (IDXSEL(sel) == 0) {
357 /* Code and stack segment selectors cannot be NULL */
358 if (codeseg || stackseg) {
359 sel_exception(ctx, vcpu, IDT_TS, sel, ts->ext);
364 seg_desc->access = 0x10000; /* unusable */
368 /* Read the descriptor from the GDT/LDT */
369 sup_paging = ts->paging;
370 sup_paging.cpl = 0; /* implicit supervisor mode */
371 error = desc_table_read(ctx, vcpu, &sup_paging, sel, &usd, faultptr);
372 if (error || *faultptr)
375 /* Verify that the descriptor type is compatible with the segment */
376 if ((ldtseg && !ldt_desc(usd.sd_type)) ||
377 (codeseg && !code_desc(usd.sd_type)) ||
378 (dataseg && !data_desc(usd.sd_type)) ||
379 (stackseg && !stack_desc(usd.sd_type))) {
380 sel_exception(ctx, vcpu, IDT_TS, sel, ts->ext);
384 /* Segment must be marked present */
392 sel_exception(ctx, vcpu, idtvec, sel, ts->ext);
396 cs = GETREG(ctx, vcpu, VM_REG_GUEST_CS);
397 cpl = cs & SEL_RPL_MASK;
398 rpl = sel & SEL_RPL_MASK;
401 if (stackseg && (rpl != cpl || dpl != cpl)) {
402 sel_exception(ctx, vcpu, IDT_TS, sel, ts->ext);
407 conforming = (usd.sd_type & 0x4) ? true : false;
408 if ((conforming && (cpl < dpl)) ||
409 (!conforming && (cpl != dpl))) {
410 sel_exception(ctx, vcpu, IDT_TS, sel, ts->ext);
417 * A data segment is always non-conforming except when it's
418 * descriptor is a readable, conforming code segment.
420 if (code_desc(usd.sd_type) && (usd.sd_type & 0x4) != 0)
425 if (!conforming && (rpl > dpl || cpl > dpl)) {
426 sel_exception(ctx, vcpu, IDT_TS, sel, ts->ext);
430 *seg_desc = usd_to_seg_desc(&usd);
435 tss32_save(struct vmctx *ctx, int vcpu, struct vm_task_switch *task_switch,
436 uint32_t eip, struct tss32 *tss, struct iovec *iov)
439 /* General purpose registers */
440 tss->tss_eax = GETREG(ctx, vcpu, VM_REG_GUEST_RAX);
441 tss->tss_ecx = GETREG(ctx, vcpu, VM_REG_GUEST_RCX);
442 tss->tss_edx = GETREG(ctx, vcpu, VM_REG_GUEST_RDX);
443 tss->tss_ebx = GETREG(ctx, vcpu, VM_REG_GUEST_RBX);
444 tss->tss_esp = GETREG(ctx, vcpu, VM_REG_GUEST_RSP);
445 tss->tss_ebp = GETREG(ctx, vcpu, VM_REG_GUEST_RBP);
446 tss->tss_esi = GETREG(ctx, vcpu, VM_REG_GUEST_RSI);
447 tss->tss_edi = GETREG(ctx, vcpu, VM_REG_GUEST_RDI);
449 /* Segment selectors */
450 tss->tss_es = GETREG(ctx, vcpu, VM_REG_GUEST_ES);
451 tss->tss_cs = GETREG(ctx, vcpu, VM_REG_GUEST_CS);
452 tss->tss_ss = GETREG(ctx, vcpu, VM_REG_GUEST_SS);
453 tss->tss_ds = GETREG(ctx, vcpu, VM_REG_GUEST_DS);
454 tss->tss_fs = GETREG(ctx, vcpu, VM_REG_GUEST_FS);
455 tss->tss_gs = GETREG(ctx, vcpu, VM_REG_GUEST_GS);
458 tss->tss_eflags = GETREG(ctx, vcpu, VM_REG_GUEST_RFLAGS);
459 if (task_switch->reason == TSR_IRET)
460 tss->tss_eflags &= ~PSL_NT;
463 /* Copy updated old TSS into guest memory */
464 vm_copyout(ctx, vcpu, tss, iov, sizeof(struct tss32));
468 update_seg_desc(struct vmctx *ctx, int vcpu, int reg, struct seg_desc *sd)
472 error = vm_set_desc(ctx, vcpu, reg, sd->base, sd->limit, sd->access);
477 * Update the vcpu registers to reflect the state of the new task.
480 tss32_restore(struct vmctx *ctx, int vcpu, struct vm_task_switch *ts,
481 uint16_t ot_sel, struct tss32 *tss, struct iovec *iov, int *faultptr)
483 struct seg_desc seg_desc, seg_desc2;
484 uint64_t *pdpte, maxphyaddr, reserved;
490 if (ts->reason != TSR_IRET && ts->reason != TSR_JMP) {
491 tss->tss_link = ot_sel;
495 eflags = tss->tss_eflags;
500 SETREG(ctx, vcpu, VM_REG_GUEST_LDTR, tss->tss_ldt);
503 if (ts->paging.paging_mode != PAGING_MODE_FLAT) {
504 if (ts->paging.paging_mode == PAGING_MODE_PAE) {
506 * XXX Assuming 36-bit MAXPHYADDR.
508 maxphyaddr = (1UL << 36) - 1;
509 pdpte = paddr_guest2host(ctx, tss->tss_cr3 & ~0x1f, 32);
510 for (i = 0; i < 4; i++) {
511 /* Check reserved bits if the PDPTE is valid */
512 if (!(pdpte[i] & 0x1))
515 * Bits 2:1, 8:5 and bits above the processor's
516 * maximum physical address are reserved.
518 reserved = ~maxphyaddr | 0x1E6;
519 if (pdpte[i] & reserved) {
520 vm_inject_gp(ctx, vcpu);
524 SETREG(ctx, vcpu, VM_REG_GUEST_PDPTE0, pdpte[0]);
525 SETREG(ctx, vcpu, VM_REG_GUEST_PDPTE1, pdpte[1]);
526 SETREG(ctx, vcpu, VM_REG_GUEST_PDPTE2, pdpte[2]);
527 SETREG(ctx, vcpu, VM_REG_GUEST_PDPTE3, pdpte[3]);
529 SETREG(ctx, vcpu, VM_REG_GUEST_CR3, tss->tss_cr3);
530 ts->paging.cr3 = tss->tss_cr3;
534 SETREG(ctx, vcpu, VM_REG_GUEST_RFLAGS, eflags);
535 SETREG(ctx, vcpu, VM_REG_GUEST_RIP, tss->tss_eip);
537 /* General purpose registers */
538 SETREG(ctx, vcpu, VM_REG_GUEST_RAX, tss->tss_eax);
539 SETREG(ctx, vcpu, VM_REG_GUEST_RCX, tss->tss_ecx);
540 SETREG(ctx, vcpu, VM_REG_GUEST_RDX, tss->tss_edx);
541 SETREG(ctx, vcpu, VM_REG_GUEST_RBX, tss->tss_ebx);
542 SETREG(ctx, vcpu, VM_REG_GUEST_RSP, tss->tss_esp);
543 SETREG(ctx, vcpu, VM_REG_GUEST_RBP, tss->tss_ebp);
544 SETREG(ctx, vcpu, VM_REG_GUEST_RSI, tss->tss_esi);
545 SETREG(ctx, vcpu, VM_REG_GUEST_RDI, tss->tss_edi);
547 /* Segment selectors */
548 SETREG(ctx, vcpu, VM_REG_GUEST_ES, tss->tss_es);
549 SETREG(ctx, vcpu, VM_REG_GUEST_CS, tss->tss_cs);
550 SETREG(ctx, vcpu, VM_REG_GUEST_SS, tss->tss_ss);
551 SETREG(ctx, vcpu, VM_REG_GUEST_DS, tss->tss_ds);
552 SETREG(ctx, vcpu, VM_REG_GUEST_FS, tss->tss_fs);
553 SETREG(ctx, vcpu, VM_REG_GUEST_GS, tss->tss_gs);
556 * If this is a nested task then write out the new TSS to update
557 * the previous link field.
560 vm_copyout(ctx, vcpu, tss, iov, sizeof(*tss));
562 /* Validate segment descriptors */
563 error = validate_seg_desc(ctx, vcpu, ts, VM_REG_GUEST_LDTR, &seg_desc,
565 if (error || *faultptr)
567 update_seg_desc(ctx, vcpu, VM_REG_GUEST_LDTR, &seg_desc);
570 * Section "Checks on Guest Segment Registers", Intel SDM, Vol 3.
572 * The SS and CS attribute checks on VM-entry are inter-dependent so
573 * we need to make sure that both segments are valid before updating
574 * either of them. This ensures that the VMCS state can pass the
575 * VM-entry checks so the guest can handle any exception injected
576 * during task switch emulation.
578 error = validate_seg_desc(ctx, vcpu, ts, VM_REG_GUEST_CS, &seg_desc,
580 if (error || *faultptr)
583 error = validate_seg_desc(ctx, vcpu, ts, VM_REG_GUEST_SS, &seg_desc2,
585 if (error || *faultptr)
587 update_seg_desc(ctx, vcpu, VM_REG_GUEST_CS, &seg_desc);
588 update_seg_desc(ctx, vcpu, VM_REG_GUEST_SS, &seg_desc2);
589 ts->paging.cpl = tss->tss_cs & SEL_RPL_MASK;
591 error = validate_seg_desc(ctx, vcpu, ts, VM_REG_GUEST_DS, &seg_desc,
593 if (error || *faultptr)
595 update_seg_desc(ctx, vcpu, VM_REG_GUEST_DS, &seg_desc);
597 error = validate_seg_desc(ctx, vcpu, ts, VM_REG_GUEST_ES, &seg_desc,
599 if (error || *faultptr)
601 update_seg_desc(ctx, vcpu, VM_REG_GUEST_ES, &seg_desc);
603 error = validate_seg_desc(ctx, vcpu, ts, VM_REG_GUEST_FS, &seg_desc,
605 if (error || *faultptr)
607 update_seg_desc(ctx, vcpu, VM_REG_GUEST_FS, &seg_desc);
609 error = validate_seg_desc(ctx, vcpu, ts, VM_REG_GUEST_GS, &seg_desc,
611 if (error || *faultptr)
613 update_seg_desc(ctx, vcpu, VM_REG_GUEST_GS, &seg_desc);
619 * Push an error code on the stack of the new task. This is needed if the
620 * task switch was triggered by a hardware exception that causes an error
621 * code to be saved (e.g. #PF).
624 push_errcode(struct vmctx *ctx, int vcpu, struct vm_guest_paging *paging,
625 int task_type, uint32_t errcode, int *faultptr)
628 struct seg_desc seg_desc;
629 int stacksize, bytes, error;
630 uint64_t gla, cr0, rflags;
636 cr0 = GETREG(ctx, vcpu, VM_REG_GUEST_CR0);
637 rflags = GETREG(ctx, vcpu, VM_REG_GUEST_RFLAGS);
638 stacksel = GETREG(ctx, vcpu, VM_REG_GUEST_SS);
640 error = vm_get_desc(ctx, vcpu, VM_REG_GUEST_SS, &seg_desc.base,
641 &seg_desc.limit, &seg_desc.access);
645 * Section "Error Code" in the Intel SDM vol 3: the error code is
646 * pushed on the stack as a doubleword or word (depending on the
647 * default interrupt, trap or task gate size).
649 if (task_type == SDT_SYS386BSY || task_type == SDT_SYS386TSS)
655 * PUSH instruction from Intel SDM vol 2: the 'B' flag in the
656 * stack-segment descriptor determines the size of the stack
657 * pointer outside of 64-bit mode.
659 if (SEG_DESC_DEF32(seg_desc.access))
664 esp = GETREG(ctx, vcpu, VM_REG_GUEST_RSP);
667 if (vie_calculate_gla(paging->cpu_mode, VM_REG_GUEST_SS,
668 &seg_desc, esp, bytes, stacksize, PROT_WRITE, &gla)) {
669 sel_exception(ctx, vcpu, IDT_SS, stacksel, 1);
674 if (vie_alignment_check(paging->cpl, bytes, cr0, rflags, gla)) {
675 vm_inject_ac(ctx, vcpu, 1);
680 error = vm_copy_setup(ctx, vcpu, paging, gla, bytes, PROT_WRITE,
681 iov, nitems(iov), faultptr);
682 if (error || *faultptr)
685 vm_copyout(ctx, vcpu, &errcode, iov, bytes);
686 SETREG(ctx, vcpu, VM_REG_GUEST_RSP, esp);
691 * Evaluate return value from helper functions and potentially return to
694 #define CHKERR(error,fault) \
696 assert((error == 0) || (error == EFAULT)); \
698 return (VMEXIT_ABORT); \
700 return (VMEXIT_CONTINUE); \
704 vmexit_task_switch(struct vmctx *ctx, struct vm_exit *vmexit, int *pvcpu)
707 struct tss32 oldtss, newtss;
708 struct vm_task_switch *task_switch;
709 struct vm_guest_paging *paging, sup_paging;
710 struct user_segment_descriptor nt_desc, ot_desc;
711 struct iovec nt_iov[2], ot_iov[2];
712 uint64_t cr0, ot_base;
713 uint32_t eip, ot_lim, access;
714 int error, ext, fault, minlimit, nt_type, ot_type, vcpu;
715 enum task_switch_reason reason;
716 uint16_t nt_sel, ot_sel;
718 task_switch = &vmexit->u.task_switch;
719 nt_sel = task_switch->tsssel;
720 ext = vmexit->u.task_switch.ext;
721 reason = vmexit->u.task_switch.reason;
722 paging = &vmexit->u.task_switch.paging;
725 assert(paging->cpu_mode == CPU_MODE_PROTECTED);
728 * Calculate the instruction pointer to store in the old TSS.
730 eip = vmexit->rip + vmexit->inst_length;
733 * Section 4.6, "Access Rights" in Intel SDM Vol 3.
734 * The following page table accesses are implicitly supervisor mode:
735 * - accesses to GDT or LDT to load segment descriptors
736 * - accesses to the task state segment during task switch
738 sup_paging = *paging;
739 sup_paging.cpl = 0; /* implicit supervisor mode */
741 /* Fetch the new TSS descriptor */
742 error = read_tss_descriptor(ctx, vcpu, task_switch, nt_sel, &nt_desc,
744 CHKERR(error, fault);
746 nt = usd_to_seg_desc(&nt_desc);
748 /* Verify the type of the new TSS */
749 nt_type = SEG_DESC_TYPE(nt.access);
750 if (nt_type != SDT_SYS386BSY && nt_type != SDT_SYS386TSS &&
751 nt_type != SDT_SYS286BSY && nt_type != SDT_SYS286TSS) {
752 sel_exception(ctx, vcpu, IDT_TS, nt_sel, ext);
756 /* TSS descriptor must have present bit set */
757 if (!SEG_DESC_PRESENT(nt.access)) {
758 sel_exception(ctx, vcpu, IDT_NP, nt_sel, ext);
763 * TSS must have a minimum length of 104 bytes for a 32-bit TSS and
764 * 44 bytes for a 16-bit TSS.
766 if (nt_type == SDT_SYS386BSY || nt_type == SDT_SYS386TSS)
768 else if (nt_type == SDT_SYS286BSY || nt_type == SDT_SYS286TSS)
773 assert(minlimit > 0);
774 if (nt.limit < minlimit) {
775 sel_exception(ctx, vcpu, IDT_TS, nt_sel, ext);
779 /* TSS must be busy if task switch is due to IRET */
780 if (reason == TSR_IRET && !TSS_BUSY(nt_type)) {
781 sel_exception(ctx, vcpu, IDT_TS, nt_sel, ext);
786 * TSS must be available (not busy) if task switch reason is
787 * CALL, JMP, exception or interrupt.
789 if (reason != TSR_IRET && TSS_BUSY(nt_type)) {
790 sel_exception(ctx, vcpu, IDT_GP, nt_sel, ext);
794 /* Fetch the new TSS */
795 error = vm_copy_setup(ctx, vcpu, &sup_paging, nt.base, minlimit + 1,
796 PROT_READ | PROT_WRITE, nt_iov, nitems(nt_iov), &fault);
797 CHKERR(error, fault);
798 vm_copyin(ctx, vcpu, nt_iov, &newtss, minlimit + 1);
800 /* Get the old TSS selector from the guest's task register */
801 ot_sel = GETREG(ctx, vcpu, VM_REG_GUEST_TR);
802 if (ISLDT(ot_sel) || IDXSEL(ot_sel) == 0) {
804 * This might happen if a task switch was attempted without
805 * ever loading the task register with LTR. In this case the
806 * TR would contain the values from power-on:
807 * (sel = 0, base = 0, limit = 0xffff).
809 sel_exception(ctx, vcpu, IDT_TS, ot_sel, task_switch->ext);
813 /* Get the old TSS base and limit from the guest's task register */
814 error = vm_get_desc(ctx, vcpu, VM_REG_GUEST_TR, &ot_base, &ot_lim,
817 assert(!SEG_DESC_UNUSABLE(access) && SEG_DESC_PRESENT(access));
818 ot_type = SEG_DESC_TYPE(access);
819 assert(ot_type == SDT_SYS386BSY || ot_type == SDT_SYS286BSY);
821 /* Fetch the old TSS descriptor */
822 error = read_tss_descriptor(ctx, vcpu, task_switch, ot_sel, &ot_desc,
824 CHKERR(error, fault);
826 /* Get the old TSS */
827 error = vm_copy_setup(ctx, vcpu, &sup_paging, ot_base, minlimit + 1,
828 PROT_READ | PROT_WRITE, ot_iov, nitems(ot_iov), &fault);
829 CHKERR(error, fault);
830 vm_copyin(ctx, vcpu, ot_iov, &oldtss, minlimit + 1);
833 * Clear the busy bit in the old TSS descriptor if the task switch
834 * due to an IRET or JMP instruction.
836 if (reason == TSR_IRET || reason == TSR_JMP) {
837 ot_desc.sd_type &= ~0x2;
838 error = desc_table_write(ctx, vcpu, &sup_paging, ot_sel,
840 CHKERR(error, fault);
843 if (nt_type == SDT_SYS286BSY || nt_type == SDT_SYS286TSS) {
844 fprintf(stderr, "Task switch to 16-bit TSS not supported\n");
845 return (VMEXIT_ABORT);
848 /* Save processor state in old TSS */
849 tss32_save(ctx, vcpu, task_switch, eip, &oldtss, ot_iov);
852 * If the task switch was triggered for any reason other than IRET
853 * then set the busy bit in the new TSS descriptor.
855 if (reason != TSR_IRET) {
856 nt_desc.sd_type |= 0x2;
857 error = desc_table_write(ctx, vcpu, &sup_paging, nt_sel,
859 CHKERR(error, fault);
862 /* Update task register to point at the new TSS */
863 SETREG(ctx, vcpu, VM_REG_GUEST_TR, nt_sel);
865 /* Update the hidden descriptor state of the task register */
866 nt = usd_to_seg_desc(&nt_desc);
867 update_seg_desc(ctx, vcpu, VM_REG_GUEST_TR, &nt);
870 cr0 = GETREG(ctx, vcpu, VM_REG_GUEST_CR0);
871 SETREG(ctx, vcpu, VM_REG_GUEST_CR0, cr0 | CR0_TS);
874 * We are now committed to the task switch. Any exceptions encountered
875 * after this point will be handled in the context of the new task and
876 * the saved instruction pointer will belong to the new task.
878 error = vm_set_register(ctx, vcpu, VM_REG_GUEST_RIP, newtss.tss_eip);
881 /* Load processor state from new TSS */
882 error = tss32_restore(ctx, vcpu, task_switch, ot_sel, &newtss, nt_iov,
884 CHKERR(error, fault);
887 * Section "Interrupt Tasks" in Intel SDM, Vol 3: if an exception
888 * caused an error code to be generated, this error code is copied
889 * to the stack of the new task.
891 if (task_switch->errcode_valid) {
892 assert(task_switch->ext);
893 assert(task_switch->reason == TSR_IDT_GATE);
894 error = push_errcode(ctx, vcpu, &task_switch->paging, nt_type,
895 task_switch->errcode, &fault);
896 CHKERR(error, fault);
900 * Treatment of virtual-NMI blocking if NMI is delivered through
903 * Section "Architectural State Before A VM Exit", Intel SDM, Vol3:
904 * If the virtual NMIs VM-execution control is 1, VM entry injects
905 * an NMI, and delivery of the NMI causes a task switch that causes
906 * a VM exit, virtual-NMI blocking is in effect before the VM exit
909 * Thus, virtual-NMI blocking is in effect at the time of the task
914 * Treatment of virtual-NMI unblocking on IRET from NMI handler task.
916 * Section "Changes to Instruction Behavior in VMX Non-Root Operation"
917 * If "virtual NMIs" control is 1 IRET removes any virtual-NMI blocking.
918 * This unblocking of virtual-NMI occurs even if IRET causes a fault.
920 * Thus, virtual-NMI blocking is cleared at the time of the task switch
925 * If the task switch was triggered by an event delivered through
926 * the IDT then extinguish the pending event from the vcpu's
929 if (task_switch->reason == TSR_IDT_GATE) {
930 error = vm_set_intinfo(ctx, vcpu, 0);
935 * XXX should inject debug exception if 'T' bit is 1
938 return (VMEXIT_CONTINUE);