2 * Copyright (c) 2012 NetApp, Inc.
3 * Copyright (c) 2013 Neel Natu <neel@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/types.h>
34 #include <dev/ic/ns16550.h>
47 #include "uart_emul.h"
49 #define COM1_BASE 0x3F8
51 #define COM2_BASE 0x2F8
54 #define DEFAULT_RCLK 1843200
55 #define DEFAULT_BAUD 9600
57 #define FCR_RX_MASK 0xC0
62 #define MSR_DELTA_MASK 0x0f
65 #define REG_SCR com_scr
70 static bool uart_stdio; /* stdio in use for i/o */
71 static struct termios tio_stdio_orig;
78 { COM1_BASE, COM1_IRQ, false},
79 { COM2_BASE, COM2_IRQ, false},
82 #define UART_NLDEVS (sizeof(uart_lres) / sizeof(uart_lres[0]))
86 int rindex; /* index to read from */
87 int windex; /* index to write to */
88 int num; /* number of characters in the fifo */
89 int size; /* size of the fifo */
94 int fd; /* tty device file descriptor */
95 struct termios tio_orig, tio_new; /* I/O Terminals */
99 pthread_mutex_t mtx; /* protects all softc elements */
100 uint8_t data; /* Data register (R/W) */
101 uint8_t ier; /* Interrupt enable register (R/W) */
102 uint8_t lcr; /* Line control register (R/W) */
103 uint8_t mcr; /* Modem control register (R/W) */
104 uint8_t lsr; /* Line status register (R/W) */
105 uint8_t msr; /* Modem status register (R/W) */
106 uint8_t fcr; /* FIFO control register (W) */
107 uint8_t scr; /* Scratch register (R/W) */
109 uint8_t dll; /* Baudrate divisor latch LSB */
110 uint8_t dlh; /* Baudrate divisor latch MSB */
116 bool thre_int_pending; /* THRE interrupt pending */
119 uart_intr_func_t intr_assert;
120 uart_intr_func_t intr_deassert;
123 static void uart_drain(int fd, enum ev_type ev, void *arg);
129 tcsetattr(STDIN_FILENO, TCSANOW, &tio_stdio_orig);
133 ttyopen(struct ttyfd *tf)
136 tcgetattr(tf->fd, &tf->tio_orig);
138 tf->tio_new = tf->tio_orig;
139 cfmakeraw(&tf->tio_new);
140 tf->tio_new.c_cflag |= CLOCAL;
141 tcsetattr(tf->fd, TCSANOW, &tf->tio_new);
143 if (tf->fd == STDIN_FILENO) {
144 tio_stdio_orig = tf->tio_orig;
150 ttyread(struct ttyfd *tf)
154 if (read(tf->fd, &rb, 1) == 1)
161 ttywrite(struct ttyfd *tf, unsigned char wb)
164 (void)write(tf->fd, &wb, 1);
168 rxfifo_reset(struct uart_softc *sc, int size)
176 bzero(fifo, sizeof(struct fifo));
179 if (sc->tty.opened) {
181 * Flush any unread input from the tty buffer.
184 nread = read(sc->tty.fd, flushbuf, sizeof(flushbuf));
185 if (nread != sizeof(flushbuf))
190 * Enable mevent to trigger when new characters are available
193 error = mevent_enable(sc->mev);
199 rxfifo_available(struct uart_softc *sc)
204 return (fifo->num < fifo->size);
208 rxfifo_putchar(struct uart_softc *sc, uint8_t ch)
215 if (fifo->num < fifo->size) {
216 fifo->buf[fifo->windex] = ch;
217 fifo->windex = (fifo->windex + 1) % fifo->size;
219 if (!rxfifo_available(sc)) {
220 if (sc->tty.opened) {
222 * Disable mevent callback if the FIFO is full.
224 error = mevent_disable(sc->mev);
234 rxfifo_getchar(struct uart_softc *sc)
237 int c, error, wasfull;
242 if (!rxfifo_available(sc))
244 c = fifo->buf[fifo->rindex];
245 fifo->rindex = (fifo->rindex + 1) % fifo->size;
248 if (sc->tty.opened) {
249 error = mevent_enable(sc->mev);
259 rxfifo_numchars(struct uart_softc *sc)
261 struct fifo *fifo = &sc->rxfifo;
267 uart_opentty(struct uart_softc *sc)
271 sc->mev = mevent_add(sc->tty.fd, EVF_READ, uart_drain, sc);
272 assert(sc->mev != NULL);
276 * The IIR returns a prioritized interrupt reason:
277 * - receive data available
278 * - transmit holding register empty
279 * - modem status change
281 * Return an interrupt reason if one is available.
284 uart_intr_reason(struct uart_softc *sc)
287 if ((sc->lsr & LSR_OE) != 0 && (sc->ier & IER_ERLS) != 0)
289 else if (rxfifo_numchars(sc) > 0 && (sc->ier & IER_ERXRDY) != 0)
291 else if (sc->thre_int_pending && (sc->ier & IER_ETXRDY) != 0)
293 else if ((sc->msr & MSR_DELTA_MASK) != 0 && (sc->ier & IER_EMSC) != 0)
300 uart_reset(struct uart_softc *sc)
304 divisor = DEFAULT_RCLK / DEFAULT_BAUD / 16;
306 sc->dlh = divisor >> 16;
308 rxfifo_reset(sc, 1); /* no fifo until enabled by software */
312 * Toggle the COM port's intr pin depending on whether or not we have an
313 * interrupt condition to report to the processor.
316 uart_toggle_intr(struct uart_softc *sc)
320 intr_reason = uart_intr_reason(sc);
322 if (intr_reason == IIR_NOPEND)
323 (*sc->intr_deassert)(sc->arg);
325 (*sc->intr_assert)(sc->arg);
329 uart_drain(int fd, enum ev_type ev, void *arg)
331 struct uart_softc *sc;
336 assert(fd == sc->tty.fd);
337 assert(ev == EVF_READ);
340 * This routine is called in the context of the mevent thread
341 * to take out the softc lock to protect against concurrent
342 * access from a vCPU i/o exit
344 pthread_mutex_lock(&sc->mtx);
346 if ((sc->mcr & MCR_LOOPBACK) != 0) {
347 (void) ttyread(&sc->tty);
349 while (rxfifo_available(sc) &&
350 ((ch = ttyread(&sc->tty)) != -1)) {
351 rxfifo_putchar(sc, ch);
353 uart_toggle_intr(sc);
356 pthread_mutex_unlock(&sc->mtx);
360 uart_write(struct uart_softc *sc, int offset, uint8_t value)
365 pthread_mutex_lock(&sc->mtx);
368 * Take care of the special case DLAB accesses first
370 if ((sc->lcr & LCR_DLAB) != 0) {
371 if (offset == REG_DLL) {
376 if (offset == REG_DLH) {
384 if (sc->mcr & MCR_LOOPBACK) {
385 if (rxfifo_putchar(sc, value) != 0)
387 } else if (sc->tty.opened) {
388 ttywrite(&sc->tty, value);
389 } /* else drop on floor */
390 sc->thre_int_pending = true;
394 * Apply mask so that bits 4-7 are 0
395 * Also enables bits 0-3 only if they're 1
397 sc->ier = value & 0x0F;
401 * When moving from FIFO and 16450 mode and vice versa,
402 * the FIFO contents are reset.
404 if ((sc->fcr & FCR_ENABLE) ^ (value & FCR_ENABLE)) {
405 fifosz = (value & FCR_ENABLE) ? FIFOSZ : 1;
406 rxfifo_reset(sc, fifosz);
410 * The FCR_ENABLE bit must be '1' for the programming
411 * of other FCR bits to be effective.
413 if ((value & FCR_ENABLE) == 0) {
416 if ((value & FCR_RCV_RST) != 0)
417 rxfifo_reset(sc, FIFOSZ);
420 (FCR_ENABLE | FCR_DMA | FCR_RX_MASK);
427 /* Apply mask so that bits 5-7 are 0 */
428 sc->mcr = value & 0x1F;
431 if (sc->mcr & MCR_LOOPBACK) {
433 * In the loopback mode certain bits from the
434 * MCR are reflected back into MSR
436 if (sc->mcr & MCR_RTS)
438 if (sc->mcr & MCR_DTR)
440 if (sc->mcr & MCR_OUT1)
442 if (sc->mcr & MCR_OUT2)
447 * Detect if there has been any change between the
448 * previous and the new value of MSR. If there is
449 * then assert the appropriate MSR delta bit.
451 if ((msr & MSR_CTS) ^ (sc->msr & MSR_CTS))
453 if ((msr & MSR_DSR) ^ (sc->msr & MSR_DSR))
455 if ((msr & MSR_DCD) ^ (sc->msr & MSR_DCD))
457 if ((sc->msr & MSR_RI) != 0 && (msr & MSR_RI) == 0)
461 * Update the value of MSR while retaining the delta
464 sc->msr &= MSR_DELTA_MASK;
469 * Line status register is not meant to be written to
470 * during normal operation.
475 * As far as I can tell MSR is a read-only register.
486 uart_toggle_intr(sc);
487 pthread_mutex_unlock(&sc->mtx);
491 uart_read(struct uart_softc *sc, int offset)
493 uint8_t iir, intr_reason, reg;
495 pthread_mutex_lock(&sc->mtx);
498 * Take care of the special case DLAB accesses first
500 if ((sc->lcr & LCR_DLAB) != 0) {
501 if (offset == REG_DLL) {
506 if (offset == REG_DLH) {
514 reg = rxfifo_getchar(sc);
520 iir = (sc->fcr & FCR_ENABLE) ? IIR_FIFO_MASK : 0;
522 intr_reason = uart_intr_reason(sc);
525 * Deal with side effects of reading the IIR register
527 if (intr_reason == IIR_TXRDY)
528 sc->thre_int_pending = false;
541 /* Transmitter is always ready for more data */
542 sc->lsr |= LSR_TEMT | LSR_THRE;
544 /* Check for new receive data */
545 if (rxfifo_numchars(sc) > 0)
546 sc->lsr |= LSR_RXRDY;
548 sc->lsr &= ~LSR_RXRDY;
552 /* The LSR_OE bit is cleared on LSR read */
557 * MSR delta bits are cleared on read
560 sc->msr &= ~MSR_DELTA_MASK;
571 uart_toggle_intr(sc);
572 pthread_mutex_unlock(&sc->mtx);
578 uart_legacy_alloc(int which, int *baseaddr, int *irq)
581 if (which < 0 || which >= UART_NLDEVS || uart_lres[which].inuse)
584 uart_lres[which].inuse = true;
585 *baseaddr = uart_lres[which].baseaddr;
586 *irq = uart_lres[which].irq;
592 uart_init(uart_intr_func_t intr_assert, uart_intr_func_t intr_deassert,
595 struct uart_softc *sc;
597 sc = calloc(1, sizeof(struct uart_softc));
600 sc->intr_assert = intr_assert;
601 sc->intr_deassert = intr_deassert;
603 pthread_mutex_init(&sc->mtx, NULL);
611 uart_tty_backend(struct uart_softc *sc, const char *opts)
618 fd = open(opts, O_RDWR | O_NONBLOCK);
619 if (fd > 0 && isatty(fd)) {
621 sc->tty.opened = true;
629 uart_set_backend(struct uart_softc *sc, const char *opts)
638 if (strcmp("stdio", opts) == 0) {
640 sc->tty.fd = STDIN_FILENO;
641 sc->tty.opened = true;
645 } else if (uart_tty_backend(sc, opts) == 0) {
649 /* Make the backend file descriptor non-blocking */
651 retval = fcntl(sc->tty.fd, F_SETFL, O_NONBLOCK);