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29 # Sample NANDsim configuration file.
32 #############################################################################
34 # [sim] General (common) simulator configuration section.
40 # log_output=[none, console, ram, file]
42 # When log_output=file is specified, each [ctrl] section must have a
43 # corresponding 'log_filename' field provided, which specifies log file name
47 #############################################################################
49 # [ctrl] Controller configuration section.
51 # There can be a number of controllers defined for simulation, each has a
52 # dedicated [ctrl] section. With a given controller there are associated
53 # subordinate NAND chips, which are tied to chip select lines.
56 # The number of this controller.
60 # The number of chip selects available at this controller.
68 # ECC layout. This is the list of byte offsets within OOB area, which comprise
69 # the ECC contents set.
71 # ecc_layout=[byte1, byte2-byte3, ..byten]
74 # Absolute path to the log file for this controller.
75 #log_filename=/var/log/nandsim-ctl0.log
78 #############################################################################
80 # [chip] Chip configuration section.
82 # There can be a number of individual NAND chip devices defined for
83 # simulation, and each has a dedicated [chip] section.
85 # A particular chip needs to be associated with its parent NAND controller by
86 # specifying the following fields: controller number (chip_ctrl) and the chip
87 # select line it is connected to (chip_cs). The chip can be connected to only
88 # a single (and unique) controller:cs pair.
91 # The number of parent controller. This has to fit one of the controller
92 # instance number (ctrl_num from [ctrl] section).
100 # ONFI device identifier.
101 # device_id=0x00..0xff
104 # ONFI manufacturer identifier.
105 # manufacturer_id=0x00..0xff
108 # Textual description of the chip.
110 model="k9xxg08uxM:1GiB 3,3V 8-bit"
112 # Textual name of the chip manufacturer.
113 # manufacturer="manufacturer name"
114 manufacturer="SAMSUNG"
116 # page_size=[must be power of 2 and >= 512] (in bytes)
120 # pages_per_block=n*32
122 # blocks_per_lun=[>0]
126 # column_addr_cycle=[1,2]
128 # row_addr_cycle=[1,2,3]
131 # program_time= (in us)
133 # erase_time= (in us)
140 # Simulate write-protect on the chip.
141 # write_protect=[yes|no]
144 # Blocks wear-out threshold. Each block has a counter of program-erase cycles;
145 # when this counter reaches 'wear_out' value a given block is treated as a bad
146 # block (access will report error).
148 # Setting wear_out to 0 means that blocks will never wear out.
153 # Errors per million read/write bytes. This simulates an accidental read/write
154 # block error, which can happen in real devices with certain probability. Note
155 # this isn't a bad block condition i.e. the block at which the read/write
156 # operation is simulated to fail here remains usable, only the operation has
157 # not succeeded (this is where ECC comes into play and is supposed to correct
160 # error_ratio=0..1000000
163 # Chip data bus width. All chips connected to the same controller must have
164 # the same bus width.
169 # Bad block map. NANDsim emulates bad block behavior upon accessing a block
170 # with number from the specified list.
172 # bad_block_map=[bad_block1, bad_block2-bad_block3, ..bad_blockn]
173 bad_block_map=[100-200]