MFC r200854,200856,200865,200873,200875,200877,200884

MFC r200854,200856,200865,200873,200875,200877,200884

r200854:
  Add minimal dealy while ste(4) is waiting for the end of active DMA
  cycle.

r200856:
  Introduce sc_flags member variable and use it to keep track of
  link state and PHY related information.
  Remove ste_link and ste_one_phy variable of softc as it's not used
  anymore.
  While I'm here add IFF_DRV_RUNNING check in ste_start_locked().

r200865:
  Reimplement miibus_statchg method. Don't rely on link state change
  interrupt. If we want to use link state change interrupt ste(4)
  should also implement auto-negotiation complete handler as well as
  various PHY access handling. Now link state change is handled by
  mii(4) polling so it will automatically update link state UP/DOWN
  events which in turn make ste(4) usable with lagg(4).

  r199559 added a private timer to drive watchdog and the timer also
  used to drive MAC statistics update. Because the MAC statistics
  update is called whenever statistics counter reaches near-full, it
  drove watchdog timer too fast such that it caused false watchdog
  timeouts under heavy TX traffic conditions.
  Fix the regression by separating ste_stats_update() from driving
  watchdog timer and introduce a new function ste_tick() that handles
  periodic job such as driving watchdog, MAC statistics update and
  link state check etc.
  While I'm here clear armed watchdog timer in ste_stop().

r200873:
  Instead of relying on hard resetting of controller to stop
  receiving incoming traffics, try harder to gracefully stop active
  DMA cycles and then stop MACs. This is the way what datasheet
  recommends and seems to work reliably. Resetting controller while
  active DMAs are in progress is bad thing as we can't predict how
  DMAs touche allocated TX/RX buffers. This change ensures controller
  stop state before attempting to release allocated TX/RX buffers.
  Also update MAC statistics which could have been updated during the
  wait time of MAC stop.

  While I'm here remove unnecessary controller resets in various
  location. ste(4) no longer relies on hard controller reset to stop
  controller and resetting controller also clears all configured
  settings which makes it hard to implement WOL in near future.
  Now resetting a controller is performed in ste_init_locked().

r200875:
  Prefer memory space register mapping over io space. If memory space
  mapping fails fall back to old io space mapping.
  While I'm here use PCIR_BAR macro.

r200877:
  Prefer bus_write_{1,2,4}/bus_read_{1,2,4} to
  bus_space_write_{1,2,4}/bus_space_read_{1,2,4}.
  Remove unused ste_bhandle and ste_btag in softc.

r200884:
  Reimplement Tx status error handler as recommended by datasheet.
  If ste(4) encounter TX underrun or excessive collisions the TX MAC
  of controller is stalled so driver should wake it up again. TX
  underrun requires increasing TX threshold value to minimize
  further TX underruns. Previously ste(4) used to reset controller
  to recover from TX underrun, excessive collision and reclaiming
  error. However datasheet says only TX underrun requires resetting
  entire controller. So implement ste_restart_tx() that restarts TX
  MAC and do not perform full reset except TX underrun case.
  Now ste(4) uses CSR_READ_2 instead of CSR_READ_1 to read
  STE_TX_STATUS register. This way ste(4) will also read frame id
  value and we can write the same value back to STE_TX_FRAMEID
  register instead of overwriting it to 0. The datasheet was wrong
  in write back of STE_TX_STATUS so add some comments why we do so.
  Also always invoke ste_txeoc() after ste_txeof() in ste_poll as
  without reading TX status register can stall TX MAC.

git-svn-id: svn://svn.freebsd.org/base/stable/8@202311 ccf9f872-aa2e-dd11-9fc8-001c23d0bc1f