MFC r205091,216860:

MFC r205091,216860:
r205091:
  Implement Rx checksum offloading for Yukon EC, Yukon Ultra,
  Yukon FE and Yukon Ultra2. These controllers provide very simple
  checksum computation mechanism and it requires additional pseudo
  header checksum computation in upper stack. Even though I couldn't
  see much performance difference with/without Rx checksum offloading
  it may help notebook based controllers.

  Actually controller can compute two checksum value by giving
  different starting position of checksum computation on received
  frame. However, for long time, Marvell's checksum offloading engine
  have been known to have several silicon bugs so don't blindly trust
  computed partial checksum value. Instead, compute partial checksum
  twice by giving the same checksum computation position and compare
  the result. If the value is different it's clear indication of
  hardware bug. This configuration lose IP checksum offloading
  capability but I think it's better to take safe route.
  Note, Rx checksum offloading for Yukon XL was still disabled due to
  known silicon bug.

r216860:
  Fix endianness bug introduced in r205091.
  After controller updates control word in a RX LE, driver converts
  it to host byte order. The checksum value in the control word is
  stored in big endian form by controller. r205091 didn't account for
  the host byte order conversion such that the checksum value was
  incorrectly interpreted on big endian architectures which in turn
  made all TCP/UDP frames dropped. Make RX checksum offload work
  on any architectures by swapping the checksum value.

  Reported by:	Sreekanth M. ( kanthms <> netlogicmicro dot com )
  Tested by:	Sreekanth M. ( kanthms <> netlogicmicro dot com )

git-svn-id: svn://svn.freebsd.org/base/stable/8@223394 ccf9f872-aa2e-dd11-9fc8-001c23d0bc1f