MFC 265440, 265441, 265444, 265445, 265446, 265447:
Move the pl310.enabled tunable to hw.pl310.enabled. Clean up a few minor
style(9) nits. Use DEVMETHOD_END.
Break out the code that figures out the L2 cache geometry to its own
routine, so that it can be called from multiple places in upcoming changes.
Call platform_pl310_init() before enabling the controller, and handle the
case where the controller is already enabled.
Add defines for the bits in the PL310 debug control register.
Add a public routine to set the L2 cache ram latencies. This can be
called by platform init routines to fine-tune cache performance.
Enable PL310 power-saving modes and tune the cache ram latencies for imx6.
git-svn-id: svn://svn.freebsd.org/base/stable/10@266384
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