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MFC 276724:
authorjhb <jhb@ccf9f872-aa2e-dd11-9fc8-001c23d0bc1f>
Thu, 2 Apr 2015 01:02:42 +0000 (01:02 +0000)
committerjhb <jhb@ccf9f872-aa2e-dd11-9fc8-001c23d0bc1f>
Thu, 2 Apr 2015 01:02:42 +0000 (01:02 +0000)
commit5f6dfe79d3679a498bcb7afd52b6dc9cc909b353
tree7694f537b30d0bb29bc4821549a8b28e4d2fb4b4tree | snapshot
parent8dcaaa472d7035890279dc3151769670273f3653commit | diff
MFC 276724:
On some Intel CPUs with a P-state but not C-state invariant TSC the TSC
may also halt in C2 and not just C3 (it seems that in some cases the BIOS
advertises its C3 state as a C2 state in _CST).  Just play it safe and
disable both C2 and C3 states if a user forces the use of the TSC as the
timecounter on such CPUs.

PR: 192316

git-svn-id: svn://svn.freebsd.org/base/stable/10@280973 ccf9f872-aa2e-dd11-9fc8-001c23d0bc1f
sys/amd64/amd64/machdep.c diff | blob | history
sys/dev/acpica/acpi_cpu.c diff | blob | history
sys/i386/i386/machdep.c diff | blob | history
sys/kern/kern_clocksource.c diff | blob | history
sys/kern/kern_tc.c diff | blob | history
sys/sys/systm.h diff | blob | history
sys/sys/timetc.h diff | blob | history
sys/x86/x86/tsc.c diff | blob | history
10-STABLE