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(parent: dd908f4) | patch
MFC: r320577, r320620
authormarius <marius@ccf9f872-aa2e-dd11-9fc8-001c23d0bc1f>
Tue, 11 Jul 2017 21:52:11 +0000 (21:52 +0000)
committermarius <marius@ccf9f872-aa2e-dd11-9fc8-001c23d0bc1f>
Tue, 11 Jul 2017 21:52:11 +0000 (21:52 +0000)
commitef4ece697e6b52e865168760d5d8ccd34984ec41
tree92e322b9b7c933fc0969e3329ed7b92fe13b8233tree | snapshot
parentdd908f449b9f6482b3f24392c89fe0c25758ed8bcommit | diff
MFC: r320577, r320620

Retry up to 2 ms to enable bus power as at least with some Intel
SDHCI/eMMC controllers the first attempt after a D3 to D0 transition,
i. e. when the firmware has put the devices into D3 state before,
can fail.

git-svn-id: svn://svn.freebsd.org/base/stable/10@320899 ccf9f872-aa2e-dd11-9fc8-001c23d0bc1f
sys/dev/sdhci/sdhci.c diff | blob | history
10-STABLE