1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "integrate.h"
50 #include "target-def.h"
52 #include "langhooks.h"
53 #include <splay-tree.h>
54 #include "cfglayout.h"
56 /* Specify which cpu to schedule for. */
58 enum processor_type alpha_cpu;
59 static const char * const alpha_cpu_name[] =
64 /* Specify how accurate floating-point traps need to be. */
66 enum alpha_trap_precision alpha_tp;
68 /* Specify the floating-point rounding mode. */
70 enum alpha_fp_rounding_mode alpha_fprm;
72 /* Specify which things cause traps. */
74 enum alpha_fp_trap_mode alpha_fptm;
76 /* Specify bit size of immediate TLS offsets. */
78 int alpha_tls_size = 32;
80 /* Strings decoded into the above options. */
82 const char *alpha_cpu_string; /* -mcpu= */
83 const char *alpha_tune_string; /* -mtune= */
84 const char *alpha_tp_string; /* -mtrap-precision=[p|s|i] */
85 const char *alpha_fprm_string; /* -mfp-rounding-mode=[n|m|c|d] */
86 const char *alpha_fptm_string; /* -mfp-trap-mode=[n|u|su|sui] */
87 const char *alpha_mlat_string; /* -mmemory-latency= */
88 const char *alpha_tls_size_string; /* -mtls-size=[16|32|64] */
90 /* Save information from a "cmpxx" operation until the branch or scc is
93 struct alpha_compare alpha_compare;
95 /* Nonzero if inside of a function, because the Alpha asm can't
96 handle .files inside of functions. */
98 static int inside_function = FALSE;
100 /* The number of cycles of latency we should assume on memory reads. */
102 int alpha_memory_latency = 3;
104 /* Whether the function needs the GP. */
106 static int alpha_function_needs_gp;
108 /* The alias set for prologue/epilogue register save/restore. */
110 static GTY(()) int alpha_sr_alias_set;
112 /* The assembler name of the current function. */
114 static const char *alpha_fnname;
116 /* The next explicit relocation sequence number. */
117 extern GTY(()) int alpha_next_sequence_number;
118 int alpha_next_sequence_number = 1;
120 /* The literal and gpdisp sequence numbers for this insn, as printed
121 by %# and %* respectively. */
122 extern GTY(()) int alpha_this_literal_sequence_number;
123 extern GTY(()) int alpha_this_gpdisp_sequence_number;
124 int alpha_this_literal_sequence_number;
125 int alpha_this_gpdisp_sequence_number;
127 /* Costs of various operations on the different architectures. */
129 struct alpha_rtx_cost_data
131 unsigned char fp_add;
132 unsigned char fp_mult;
133 unsigned char fp_div_sf;
134 unsigned char fp_div_df;
135 unsigned char int_mult_si;
136 unsigned char int_mult_di;
137 unsigned char int_shift;
138 unsigned char int_cmov;
141 static struct alpha_rtx_cost_data const alpha_rtx_cost_data[PROCESSOR_MAX] =
144 COSTS_N_INSNS (6), /* fp_add */
145 COSTS_N_INSNS (6), /* fp_mult */
146 COSTS_N_INSNS (34), /* fp_div_sf */
147 COSTS_N_INSNS (63), /* fp_div_df */
148 COSTS_N_INSNS (23), /* int_mult_si */
149 COSTS_N_INSNS (23), /* int_mult_di */
150 COSTS_N_INSNS (2), /* int_shift */
151 COSTS_N_INSNS (2), /* int_cmov */
154 COSTS_N_INSNS (4), /* fp_add */
155 COSTS_N_INSNS (4), /* fp_mult */
156 COSTS_N_INSNS (15), /* fp_div_sf */
157 COSTS_N_INSNS (22), /* fp_div_df */
158 COSTS_N_INSNS (8), /* int_mult_si */
159 COSTS_N_INSNS (12), /* int_mult_di */
160 COSTS_N_INSNS (1) + 1, /* int_shift */
161 COSTS_N_INSNS (1), /* int_cmov */
164 COSTS_N_INSNS (4), /* fp_add */
165 COSTS_N_INSNS (4), /* fp_mult */
166 COSTS_N_INSNS (12), /* fp_div_sf */
167 COSTS_N_INSNS (15), /* fp_div_df */
168 COSTS_N_INSNS (7), /* int_mult_si */
169 COSTS_N_INSNS (7), /* int_mult_di */
170 COSTS_N_INSNS (1), /* int_shift */
171 COSTS_N_INSNS (2), /* int_cmov */
175 /* Get the number of args of a function in one of two ways. */
176 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
177 #define NUM_ARGS current_function_args_info.num_args
179 #define NUM_ARGS current_function_args_info
185 /* Declarations of static functions. */
186 static struct machine_function *alpha_init_machine_status (void);
187 static rtx alpha_emit_xfloating_compare (enum rtx_code, rtx, rtx);
189 #if TARGET_ABI_OPEN_VMS
190 static void alpha_write_linkage (FILE *, const char *, tree);
193 static void unicosmk_output_deferred_case_vectors (FILE *);
194 static void unicosmk_gen_dsib (unsigned long *);
195 static void unicosmk_output_ssib (FILE *, const char *);
196 static int unicosmk_need_dex (rtx);
198 /* Parse target option strings. */
201 override_options (void)
204 static const struct cpu_table {
205 const char *const name;
206 const enum processor_type processor;
209 #define EV5_MASK (MASK_CPU_EV5)
210 #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
211 { "ev4", PROCESSOR_EV4, 0 },
212 { "ev45", PROCESSOR_EV4, 0 },
213 { "21064", PROCESSOR_EV4, 0 },
214 { "ev5", PROCESSOR_EV5, EV5_MASK },
215 { "21164", PROCESSOR_EV5, EV5_MASK },
216 { "ev56", PROCESSOR_EV5, EV5_MASK|MASK_BWX },
217 { "21164a", PROCESSOR_EV5, EV5_MASK|MASK_BWX },
218 { "pca56", PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX },
219 { "21164PC",PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX },
220 { "21164pc",PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX },
221 { "ev6", PROCESSOR_EV6, EV6_MASK },
222 { "21264", PROCESSOR_EV6, EV6_MASK },
223 { "ev67", PROCESSOR_EV6, EV6_MASK|MASK_CIX },
224 { "21264a", PROCESSOR_EV6, EV6_MASK|MASK_CIX },
228 /* Unicos/Mk doesn't have shared libraries. */
229 if (TARGET_ABI_UNICOSMK && flag_pic)
231 warning ("-f%s ignored for Unicos/Mk (not supported)",
232 (flag_pic > 1) ? "PIC" : "pic");
236 /* On Unicos/Mk, the native compiler consistently generates /d suffices for
237 floating-point instructions. Make that the default for this target. */
238 if (TARGET_ABI_UNICOSMK)
239 alpha_fprm = ALPHA_FPRM_DYN;
241 alpha_fprm = ALPHA_FPRM_NORM;
243 alpha_tp = ALPHA_TP_PROG;
244 alpha_fptm = ALPHA_FPTM_N;
246 /* We cannot use su and sui qualifiers for conversion instructions on
247 Unicos/Mk. I'm not sure if this is due to assembler or hardware
248 limitations. Right now, we issue a warning if -mieee is specified
249 and then ignore it; eventually, we should either get it right or
250 disable the option altogether. */
254 if (TARGET_ABI_UNICOSMK)
255 warning ("-mieee not supported on Unicos/Mk");
258 alpha_tp = ALPHA_TP_INSN;
259 alpha_fptm = ALPHA_FPTM_SU;
263 if (TARGET_IEEE_WITH_INEXACT)
265 if (TARGET_ABI_UNICOSMK)
266 warning ("-mieee-with-inexact not supported on Unicos/Mk");
269 alpha_tp = ALPHA_TP_INSN;
270 alpha_fptm = ALPHA_FPTM_SUI;
276 if (! strcmp (alpha_tp_string, "p"))
277 alpha_tp = ALPHA_TP_PROG;
278 else if (! strcmp (alpha_tp_string, "f"))
279 alpha_tp = ALPHA_TP_FUNC;
280 else if (! strcmp (alpha_tp_string, "i"))
281 alpha_tp = ALPHA_TP_INSN;
283 error ("bad value `%s' for -mtrap-precision switch", alpha_tp_string);
286 if (alpha_fprm_string)
288 if (! strcmp (alpha_fprm_string, "n"))
289 alpha_fprm = ALPHA_FPRM_NORM;
290 else if (! strcmp (alpha_fprm_string, "m"))
291 alpha_fprm = ALPHA_FPRM_MINF;
292 else if (! strcmp (alpha_fprm_string, "c"))
293 alpha_fprm = ALPHA_FPRM_CHOP;
294 else if (! strcmp (alpha_fprm_string,"d"))
295 alpha_fprm = ALPHA_FPRM_DYN;
297 error ("bad value `%s' for -mfp-rounding-mode switch",
301 if (alpha_fptm_string)
303 if (strcmp (alpha_fptm_string, "n") == 0)
304 alpha_fptm = ALPHA_FPTM_N;
305 else if (strcmp (alpha_fptm_string, "u") == 0)
306 alpha_fptm = ALPHA_FPTM_U;
307 else if (strcmp (alpha_fptm_string, "su") == 0)
308 alpha_fptm = ALPHA_FPTM_SU;
309 else if (strcmp (alpha_fptm_string, "sui") == 0)
310 alpha_fptm = ALPHA_FPTM_SUI;
312 error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string);
315 if (alpha_tls_size_string)
317 if (strcmp (alpha_tls_size_string, "16") == 0)
319 else if (strcmp (alpha_tls_size_string, "32") == 0)
321 else if (strcmp (alpha_tls_size_string, "64") == 0)
324 error ("bad value `%s' for -mtls-size switch", alpha_tls_size_string);
328 = TARGET_CPU_DEFAULT & MASK_CPU_EV6 ? PROCESSOR_EV6
329 : (TARGET_CPU_DEFAULT & MASK_CPU_EV5 ? PROCESSOR_EV5 : PROCESSOR_EV4);
331 if (alpha_cpu_string)
333 for (i = 0; cpu_table [i].name; i++)
334 if (! strcmp (alpha_cpu_string, cpu_table [i].name))
336 alpha_cpu = cpu_table [i].processor;
337 target_flags &= ~ (MASK_BWX | MASK_MAX | MASK_FIX | MASK_CIX
338 | MASK_CPU_EV5 | MASK_CPU_EV6);
339 target_flags |= cpu_table [i].flags;
342 if (! cpu_table [i].name)
343 error ("bad value `%s' for -mcpu switch", alpha_cpu_string);
346 if (alpha_tune_string)
348 for (i = 0; cpu_table [i].name; i++)
349 if (! strcmp (alpha_tune_string, cpu_table [i].name))
351 alpha_cpu = cpu_table [i].processor;
354 if (! cpu_table [i].name)
355 error ("bad value `%s' for -mcpu switch", alpha_tune_string);
358 /* Do some sanity checks on the above options. */
360 if (TARGET_ABI_UNICOSMK && alpha_fptm != ALPHA_FPTM_N)
362 warning ("trap mode not supported on Unicos/Mk");
363 alpha_fptm = ALPHA_FPTM_N;
366 if ((alpha_fptm == ALPHA_FPTM_SU || alpha_fptm == ALPHA_FPTM_SUI)
367 && alpha_tp != ALPHA_TP_INSN && ! TARGET_CPU_EV6)
369 warning ("fp software completion requires -mtrap-precision=i");
370 alpha_tp = ALPHA_TP_INSN;
375 /* Except for EV6 pass 1 (not released), we always have precise
376 arithmetic traps. Which means we can do software completion
377 without minding trap shadows. */
378 alpha_tp = ALPHA_TP_PROG;
381 if (TARGET_FLOAT_VAX)
383 if (alpha_fprm == ALPHA_FPRM_MINF || alpha_fprm == ALPHA_FPRM_DYN)
385 warning ("rounding mode not supported for VAX floats");
386 alpha_fprm = ALPHA_FPRM_NORM;
388 if (alpha_fptm == ALPHA_FPTM_SUI)
390 warning ("trap mode not supported for VAX floats");
391 alpha_fptm = ALPHA_FPTM_SU;
393 if (target_flags_explicit & MASK_LONG_DOUBLE_128)
394 warning ("128-bit long double not supported for VAX floats");
395 target_flags &= ~MASK_LONG_DOUBLE_128;
402 if (!alpha_mlat_string)
403 alpha_mlat_string = "L1";
405 if (ISDIGIT ((unsigned char)alpha_mlat_string[0])
406 && (lat = strtol (alpha_mlat_string, &end, 10), *end == '\0'))
408 else if ((alpha_mlat_string[0] == 'L' || alpha_mlat_string[0] == 'l')
409 && ISDIGIT ((unsigned char)alpha_mlat_string[1])
410 && alpha_mlat_string[2] == '\0')
412 static int const cache_latency[][4] =
414 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
415 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
416 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
419 lat = alpha_mlat_string[1] - '0';
420 if (lat <= 0 || lat > 3 || cache_latency[alpha_cpu][lat-1] == -1)
422 warning ("L%d cache latency unknown for %s",
423 lat, alpha_cpu_name[alpha_cpu]);
427 lat = cache_latency[alpha_cpu][lat-1];
429 else if (! strcmp (alpha_mlat_string, "main"))
431 /* Most current memories have about 370ns latency. This is
432 a reasonable guess for a fast cpu. */
437 warning ("bad value `%s' for -mmemory-latency", alpha_mlat_string);
441 alpha_memory_latency = lat;
444 /* Default the definition of "small data" to 8 bytes. */
448 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
450 target_flags |= MASK_SMALL_DATA;
451 else if (flag_pic == 2)
452 target_flags &= ~MASK_SMALL_DATA;
454 /* Align labels and loops for optimal branching. */
455 /* ??? Kludge these by not doing anything if we don't optimize and also if
456 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
457 if (optimize > 0 && write_symbols != SDB_DEBUG)
459 if (align_loops <= 0)
461 if (align_jumps <= 0)
464 if (align_functions <= 0)
465 align_functions = 16;
467 /* Acquire a unique set number for our register saves and restores. */
468 alpha_sr_alias_set = new_alias_set ();
470 /* Register variables and functions with the garbage collector. */
472 /* Set up function hooks. */
473 init_machine_status = alpha_init_machine_status;
475 /* Tell the compiler when we're using VAX floating point. */
476 if (TARGET_FLOAT_VAX)
478 REAL_MODE_FORMAT (SFmode) = &vax_f_format;
479 REAL_MODE_FORMAT (DFmode) = &vax_g_format;
480 REAL_MODE_FORMAT (TFmode) = NULL;
484 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
487 zap_mask (HOST_WIDE_INT value)
491 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
493 if ((value & 0xff) != 0 && (value & 0xff) != 0xff)
499 /* Returns 1 if OP is either the constant zero or a register. If a
500 register, it must be in the proper mode unless MODE is VOIDmode. */
503 reg_or_0_operand (rtx op, enum machine_mode mode)
505 return op == CONST0_RTX (mode) || register_operand (op, mode);
508 /* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
512 reg_or_6bit_operand (rtx op, enum machine_mode mode)
514 return ((GET_CODE (op) == CONST_INT
515 && (unsigned HOST_WIDE_INT) INTVAL (op) < 64)
516 || register_operand (op, mode));
520 /* Return 1 if OP is an 8-bit constant or any register. */
523 reg_or_8bit_operand (rtx op, enum machine_mode mode)
525 return ((GET_CODE (op) == CONST_INT
526 && (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100)
527 || register_operand (op, mode));
530 /* Return 1 if OP is a constant or any register. */
533 reg_or_const_int_operand (rtx op, enum machine_mode mode)
535 return GET_CODE (op) == CONST_INT || register_operand (op, mode);
538 /* Return 1 if OP is an 8-bit constant. */
541 cint8_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
543 return ((GET_CODE (op) == CONST_INT
544 && (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100));
547 /* Return 1 if the operand is a valid second operand to an add insn. */
550 add_operand (rtx op, enum machine_mode mode)
552 if (GET_CODE (op) == CONST_INT)
553 /* Constraints I, J, O and P are covered by K. */
554 return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')
555 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
557 return register_operand (op, mode);
560 /* Return 1 if the operand is a valid second operand to a sign-extending
564 sext_add_operand (rtx op, enum machine_mode mode)
566 if (GET_CODE (op) == CONST_INT)
567 return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
568 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'O'));
570 return reg_not_elim_operand (op, mode);
573 /* Return 1 if OP is the constant 4 or 8. */
576 const48_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
578 return (GET_CODE (op) == CONST_INT
579 && (INTVAL (op) == 4 || INTVAL (op) == 8));
582 /* Return 1 if OP is a valid first operand to an AND insn. */
585 and_operand (rtx op, enum machine_mode mode)
587 if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == VOIDmode)
588 return (zap_mask (CONST_DOUBLE_LOW (op))
589 && zap_mask (CONST_DOUBLE_HIGH (op)));
591 if (GET_CODE (op) == CONST_INT)
592 return ((unsigned HOST_WIDE_INT) INTVAL (op) < 0x100
593 || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100
594 || zap_mask (INTVAL (op)));
596 return register_operand (op, mode);
599 /* Return 1 if OP is a valid first operand to an IOR or XOR insn. */
602 or_operand (rtx op, enum machine_mode mode)
604 if (GET_CODE (op) == CONST_INT)
605 return ((unsigned HOST_WIDE_INT) INTVAL (op) < 0x100
606 || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100);
608 return register_operand (op, mode);
611 /* Return 1 if OP is a constant that is the width, in bits, of an integral
612 mode smaller than DImode. */
615 mode_width_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
617 return (GET_CODE (op) == CONST_INT
618 && (INTVAL (op) == 8 || INTVAL (op) == 16
619 || INTVAL (op) == 32 || INTVAL (op) == 64));
622 /* Return 1 if OP is a constant that is the width of an integral machine mode
623 smaller than an integer. */
626 mode_mask_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
628 if (GET_CODE (op) == CONST_INT)
630 HOST_WIDE_INT value = INTVAL (op);
636 if (value == 0xffffffff)
641 else if (HOST_BITS_PER_WIDE_INT == 32 && GET_CODE (op) == CONST_DOUBLE)
643 if (CONST_DOUBLE_LOW (op) == 0xffffffff && CONST_DOUBLE_HIGH (op) == 0)
650 /* Return 1 if OP is a multiple of 8 less than 64. */
653 mul8_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
655 return (GET_CODE (op) == CONST_INT
656 && (unsigned HOST_WIDE_INT) INTVAL (op) < 64
657 && (INTVAL (op) & 7) == 0);
660 /* Return 1 if OP is the zero constant for MODE. */
663 const0_operand (rtx op, enum machine_mode mode)
665 return op == CONST0_RTX (mode);
668 /* Return 1 if OP is a hard floating-point register. */
671 hard_fp_register_operand (rtx op, enum machine_mode mode)
673 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
676 if (GET_CODE (op) == SUBREG)
677 op = SUBREG_REG (op);
678 return GET_CODE (op) == REG && REGNO_REG_CLASS (REGNO (op)) == FLOAT_REGS;
681 /* Return 1 if OP is a hard general register. */
684 hard_int_register_operand (rtx op, enum machine_mode mode)
686 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
689 if (GET_CODE (op) == SUBREG)
690 op = SUBREG_REG (op);
691 return GET_CODE (op) == REG && REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS;
694 /* Return 1 if OP is a register or a constant integer. */
698 reg_or_cint_operand (rtx op, enum machine_mode mode)
700 return (GET_CODE (op) == CONST_INT
701 || register_operand (op, mode));
704 /* Return 1 if OP is something that can be reloaded into a register;
705 if it is a MEM, it need not be valid. */
708 some_operand (rtx op, enum machine_mode mode)
710 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
713 switch (GET_CODE (op))
727 return some_operand (SUBREG_REG (op), VOIDmode);
736 /* Likewise, but don't accept constants. */
739 some_ni_operand (rtx op, enum machine_mode mode)
741 if (GET_MODE (op) != mode && mode != VOIDmode)
744 if (GET_CODE (op) == SUBREG)
745 op = SUBREG_REG (op);
747 return (GET_CODE (op) == REG || GET_CODE (op) == MEM);
750 /* Return 1 if OP is a valid operand for the source of a move insn. */
753 input_operand (rtx op, enum machine_mode mode)
755 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
758 if (GET_MODE_CLASS (mode) == MODE_FLOAT && GET_MODE (op) != mode)
761 switch (GET_CODE (op))
766 if (TARGET_EXPLICIT_RELOCS)
768 /* We don't split symbolic operands into something unintelligable
769 until after reload, but we do not wish non-small, non-global
770 symbolic operands to be reconstructed from their high/lo_sum
772 return (small_symbolic_operand (op, mode)
773 || global_symbolic_operand (op, mode)
774 || gotdtp_symbolic_operand (op, mode)
775 || gottp_symbolic_operand (op, mode));
778 /* This handles both the Windows/NT and OSF cases. */
779 return mode == ptr_mode || mode == DImode;
782 return (TARGET_EXPLICIT_RELOCS
783 && local_symbolic_operand (XEXP (op, 0), mode));
790 if (register_operand (op, mode))
792 /* ... fall through ... */
794 return ((TARGET_BWX || (mode != HImode && mode != QImode))
795 && general_operand (op, mode));
799 return op == CONST0_RTX (mode);
802 return mode == QImode || mode == HImode || add_operand (op, mode);
814 /* Return 1 if OP is a SYMBOL_REF for a function known to be in this
815 file, and in the same section as the current function. */
818 samegp_function_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
820 if (GET_CODE (op) != SYMBOL_REF)
823 /* Easy test for recursion. */
824 if (op == XEXP (DECL_RTL (current_function_decl), 0))
827 /* Functions that are not local can be overridden, and thus may
828 not share the same gp. */
829 if (! SYMBOL_REF_LOCAL_P (op))
832 /* If -msmall-data is in effect, assume that there is only one GP
833 for the module, and so any local symbol has this property. We
834 need explicit relocations to be able to enforce this for symbols
835 not defined in this unit of translation, however. */
836 if (TARGET_EXPLICIT_RELOCS && TARGET_SMALL_DATA)
839 /* Functions that are not external are defined in this UoT,
840 and thus must share the same gp. */
841 return ! SYMBOL_REF_EXTERNAL_P (op);
844 /* Return 1 if OP is a SYMBOL_REF for which we can make a call via bsr. */
847 direct_call_operand (rtx op, enum machine_mode mode)
849 tree op_decl, cfun_sec, op_sec;
851 /* Must share the same GP. */
852 if (!samegp_function_operand (op, mode))
855 /* If profiling is implemented via linker tricks, we can't jump
856 to the nogp alternate entry point. Note that current_function_profile
857 would not be correct, since that doesn't indicate if the target
858 function uses profiling. */
859 /* ??? TARGET_PROFILING_NEEDS_GP isn't really the right test,
860 but is approximately correct for the OSF ABIs. Don't know
861 what to do for VMS, NT, or UMK. */
862 if (!TARGET_PROFILING_NEEDS_GP && profile_flag)
865 /* Must be a function. In some cases folks create thunks in static
866 data structures and then make calls to them. If we allow the
867 direct call, we'll get an error from the linker about !samegp reloc
868 against a symbol without a .prologue directive. */
869 if (!SYMBOL_REF_FUNCTION_P (op))
872 /* Must be "near" so that the branch is assumed to reach. With
873 -msmall-text, this is assumed true of all local symbols. Since
874 we've already checked samegp, locality is already assured. */
875 if (TARGET_SMALL_TEXT)
878 /* Otherwise, a decl is "near" if it is defined in the same section. */
879 if (flag_function_sections)
882 op_decl = SYMBOL_REF_DECL (op);
883 if (DECL_ONE_ONLY (current_function_decl)
884 || (op_decl && DECL_ONE_ONLY (op_decl)))
887 cfun_sec = DECL_SECTION_NAME (current_function_decl);
888 op_sec = op_decl ? DECL_SECTION_NAME (op_decl) : NULL;
889 return ((!cfun_sec && !op_sec)
890 || (cfun_sec && op_sec
891 && strcmp (TREE_STRING_POINTER (cfun_sec),
892 TREE_STRING_POINTER (op_sec)) == 0));
895 /* Return true if OP is a LABEL_REF, or SYMBOL_REF or CONST referencing
896 a (non-tls) variable known to be defined in this file. */
899 local_symbolic_operand (rtx op, enum machine_mode mode)
901 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
904 if (GET_CODE (op) == LABEL_REF)
907 if (GET_CODE (op) == CONST
908 && GET_CODE (XEXP (op, 0)) == PLUS
909 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
910 op = XEXP (XEXP (op, 0), 0);
912 if (GET_CODE (op) != SYMBOL_REF)
915 return SYMBOL_REF_LOCAL_P (op) && !SYMBOL_REF_TLS_MODEL (op);
918 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
919 known to be defined in this file in the small data area. */
922 small_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
924 if (! TARGET_SMALL_DATA)
927 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
930 if (GET_CODE (op) == CONST
931 && GET_CODE (XEXP (op, 0)) == PLUS
932 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
933 op = XEXP (XEXP (op, 0), 0);
935 if (GET_CODE (op) != SYMBOL_REF)
938 /* ??? There's no encode_section_info equivalent for the rtl
939 constant pool, so SYMBOL_FLAG_SMALL never gets set. */
940 if (CONSTANT_POOL_ADDRESS_P (op))
941 return GET_MODE_SIZE (get_pool_mode (op)) <= g_switch_value;
943 return (SYMBOL_REF_LOCAL_P (op)
944 && SYMBOL_REF_SMALL_P (op)
945 && SYMBOL_REF_TLS_MODEL (op) == 0);
948 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
949 not known (or known not) to be defined in this file. */
952 global_symbolic_operand (rtx op, enum machine_mode mode)
954 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
957 if (GET_CODE (op) == CONST
958 && GET_CODE (XEXP (op, 0)) == PLUS
959 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
960 op = XEXP (XEXP (op, 0), 0);
962 if (GET_CODE (op) != SYMBOL_REF)
965 return !SYMBOL_REF_LOCAL_P (op) && !SYMBOL_REF_TLS_MODEL (op);
968 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
971 call_operand (rtx op, enum machine_mode mode)
976 if (GET_CODE (op) == REG)
980 /* Disallow virtual registers to cope with pathological test cases
981 such as compile/930117-1.c in which the virtual reg decomposes
982 to the frame pointer. Which is a hard reg that is not $27. */
983 return (REGNO (op) == 27 || REGNO (op) > LAST_VIRTUAL_REGISTER);
988 if (TARGET_ABI_UNICOSMK)
990 if (GET_CODE (op) == SYMBOL_REF)
996 /* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
997 possibly with an offset. */
1000 symbolic_operand (rtx op, enum machine_mode mode)
1002 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1004 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
1006 if (GET_CODE (op) == CONST
1007 && GET_CODE (XEXP (op,0)) == PLUS
1008 && GET_CODE (XEXP (XEXP (op,0), 0)) == SYMBOL_REF
1009 && GET_CODE (XEXP (XEXP (op,0), 1)) == CONST_INT)
1014 /* Return true if OP is valid for a particular TLS relocation. */
1017 tls_symbolic_operand_1 (rtx op, enum machine_mode mode, int size, int unspec)
1019 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1022 if (GET_CODE (op) != CONST)
1026 if (GET_CODE (op) != UNSPEC || XINT (op, 1) != unspec)
1028 op = XVECEXP (op, 0, 0);
1030 if (GET_CODE (op) != SYMBOL_REF)
1033 if (SYMBOL_REF_LOCAL_P (op))
1035 if (alpha_tls_size > size)
1044 switch (SYMBOL_REF_TLS_MODEL (op))
1046 case TLS_MODEL_LOCAL_DYNAMIC:
1047 return unspec == UNSPEC_DTPREL;
1048 case TLS_MODEL_INITIAL_EXEC:
1049 return unspec == UNSPEC_TPREL && size == 64;
1050 case TLS_MODEL_LOCAL_EXEC:
1051 return unspec == UNSPEC_TPREL;
1057 /* Return true if OP is valid for 16-bit DTP relative relocations. */
1060 dtp16_symbolic_operand (rtx op, enum machine_mode mode)
1062 return tls_symbolic_operand_1 (op, mode, 16, UNSPEC_DTPREL);
1065 /* Return true if OP is valid for 32-bit DTP relative relocations. */
1068 dtp32_symbolic_operand (rtx op, enum machine_mode mode)
1070 return tls_symbolic_operand_1 (op, mode, 32, UNSPEC_DTPREL);
1073 /* Return true if OP is valid for 64-bit DTP relative relocations. */
1076 gotdtp_symbolic_operand (rtx op, enum machine_mode mode)
1078 return tls_symbolic_operand_1 (op, mode, 64, UNSPEC_DTPREL);
1081 /* Return true if OP is valid for 16-bit TP relative relocations. */
1084 tp16_symbolic_operand (rtx op, enum machine_mode mode)
1086 return tls_symbolic_operand_1 (op, mode, 16, UNSPEC_TPREL);
1089 /* Return true if OP is valid for 32-bit TP relative relocations. */
1092 tp32_symbolic_operand (rtx op, enum machine_mode mode)
1094 return tls_symbolic_operand_1 (op, mode, 32, UNSPEC_TPREL);
1097 /* Return true if OP is valid for 64-bit TP relative relocations. */
1100 gottp_symbolic_operand (rtx op, enum machine_mode mode)
1102 return tls_symbolic_operand_1 (op, mode, 64, UNSPEC_TPREL);
1105 /* Return 1 if OP is a valid Alpha comparison operator. Here we know which
1106 comparisons are valid in which insn. */
1109 alpha_comparison_operator (rtx op, enum machine_mode mode)
1111 enum rtx_code code = GET_CODE (op);
1113 if (mode != GET_MODE (op) && mode != VOIDmode)
1116 return (code == EQ || code == LE || code == LT
1117 || code == LEU || code == LTU);
1120 /* Return 1 if OP is a valid Alpha comparison operator against zero.
1121 Here we know which comparisons are valid in which insn. */
1124 alpha_zero_comparison_operator (rtx op, enum machine_mode mode)
1126 enum rtx_code code = GET_CODE (op);
1128 if (mode != GET_MODE (op) && mode != VOIDmode)
1131 return (code == EQ || code == NE || code == LE || code == LT
1132 || code == LEU || code == LTU);
1135 /* Return 1 if OP is a valid Alpha swapped comparison operator. */
1138 alpha_swapped_comparison_operator (rtx op, enum machine_mode mode)
1140 enum rtx_code code = GET_CODE (op);
1142 if ((mode != GET_MODE (op) && mode != VOIDmode)
1143 || GET_RTX_CLASS (code) != '<')
1146 code = swap_condition (code);
1147 return (code == EQ || code == LE || code == LT
1148 || code == LEU || code == LTU);
1151 /* Return 1 if OP is a signed comparison operation. */
1154 signed_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1156 enum rtx_code code = GET_CODE (op);
1158 if (mode != GET_MODE (op) && mode != VOIDmode)
1161 return (code == EQ || code == NE
1162 || code == LE || code == LT
1163 || code == GE || code == GT);
1166 /* Return 1 if OP is a valid Alpha floating point comparison operator.
1167 Here we know which comparisons are valid in which insn. */
1170 alpha_fp_comparison_operator (rtx op, enum machine_mode mode)
1172 enum rtx_code code = GET_CODE (op);
1174 if (mode != GET_MODE (op) && mode != VOIDmode)
1177 return (code == EQ || code == LE || code == LT || code == UNORDERED);
1180 /* Return 1 if this is a divide or modulus operator. */
1183 divmod_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1185 enum rtx_code code = GET_CODE (op);
1187 return (code == DIV || code == MOD || code == UDIV || code == UMOD);
1190 /* Return 1 if this is a float->int conversion operator. */
1193 fix_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1195 enum rtx_code code = GET_CODE (op);
1197 return (code == FIX || code == UNSIGNED_FIX);
1200 /* Return 1 if this memory address is a known aligned register plus
1201 a constant. It must be a valid address. This means that we can do
1202 this as an aligned reference plus some offset.
1204 Take into account what reload will do. */
1207 aligned_memory_operand (rtx op, enum machine_mode mode)
1211 if (reload_in_progress)
1214 if (GET_CODE (tmp) == SUBREG)
1215 tmp = SUBREG_REG (tmp);
1216 if (GET_CODE (tmp) == REG
1217 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
1219 op = reg_equiv_memory_loc[REGNO (tmp)];
1225 if (GET_CODE (op) != MEM)
1227 if (MEM_ALIGN (op) >= 32)
1231 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1232 sorts of constructs. Dig for the real base register. */
1233 if (reload_in_progress
1234 && GET_CODE (op) == PLUS
1235 && GET_CODE (XEXP (op, 0)) == PLUS)
1236 base = XEXP (XEXP (op, 0), 0);
1239 if (! memory_address_p (mode, op))
1241 base = (GET_CODE (op) == PLUS ? XEXP (op, 0) : op);
1244 return (GET_CODE (base) == REG && REGNO_POINTER_ALIGN (REGNO (base)) >= 32);
1247 /* Similar, but return 1 if OP is a MEM which is not alignable. */
1250 unaligned_memory_operand (rtx op, enum machine_mode mode)
1254 if (reload_in_progress)
1257 if (GET_CODE (tmp) == SUBREG)
1258 tmp = SUBREG_REG (tmp);
1259 if (GET_CODE (tmp) == REG
1260 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
1262 op = reg_equiv_memory_loc[REGNO (tmp)];
1268 if (GET_CODE (op) != MEM)
1270 if (MEM_ALIGN (op) >= 32)
1274 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1275 sorts of constructs. Dig for the real base register. */
1276 if (reload_in_progress
1277 && GET_CODE (op) == PLUS
1278 && GET_CODE (XEXP (op, 0)) == PLUS)
1279 base = XEXP (XEXP (op, 0), 0);
1282 if (! memory_address_p (mode, op))
1284 base = (GET_CODE (op) == PLUS ? XEXP (op, 0) : op);
1287 return (GET_CODE (base) == REG && REGNO_POINTER_ALIGN (REGNO (base)) < 32);
1290 /* Return 1 if OP is either a register or an unaligned memory location. */
1293 reg_or_unaligned_mem_operand (rtx op, enum machine_mode mode)
1295 return register_operand (op, mode) || unaligned_memory_operand (op, mode);
1298 /* Return 1 if OP is any memory location. During reload a pseudo matches. */
1301 any_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1303 return (GET_CODE (op) == MEM
1304 || (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
1305 || (reload_in_progress && GET_CODE (op) == REG
1306 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1307 || (reload_in_progress && GET_CODE (op) == SUBREG
1308 && GET_CODE (SUBREG_REG (op)) == REG
1309 && REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER));
1312 /* Returns 1 if OP is not an eliminable register.
1314 This exists to cure a pathological abort in the s8addq (et al) patterns,
1316 long foo () { long t; bar(); return (long) &t * 26107; }
1318 which run afoul of a hack in reload to cure a (presumably) similar
1319 problem with lea-type instructions on other targets. But there is
1320 one of us and many of them, so work around the problem by selectively
1321 preventing combine from making the optimization. */
1324 reg_not_elim_operand (rtx op, enum machine_mode mode)
1327 if (GET_CODE (op) == SUBREG)
1328 inner = SUBREG_REG (op);
1329 if (inner == frame_pointer_rtx || inner == arg_pointer_rtx)
1332 return register_operand (op, mode);
1335 /* Return 1 is OP is a memory location that is not a reference (using
1336 an AND) to an unaligned location. Take into account what reload
1340 normal_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1342 if (reload_in_progress)
1345 if (GET_CODE (tmp) == SUBREG)
1346 tmp = SUBREG_REG (tmp);
1347 if (GET_CODE (tmp) == REG
1348 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
1350 op = reg_equiv_memory_loc[REGNO (tmp)];
1352 /* This may not have been assigned an equivalent address if it will
1353 be eliminated. In that case, it doesn't matter what we do. */
1359 return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) != AND;
1362 /* Accept a register, but not a subreg of any kind. This allows us to
1363 avoid pathological cases in reload wrt data movement common in
1364 int->fp conversion. */
1367 reg_no_subreg_operand (rtx op, enum machine_mode mode)
1369 if (GET_CODE (op) != REG)
1371 return register_operand (op, mode);
1374 /* Recognize an addition operation that includes a constant. Used to
1375 convince reload to canonize (plus (plus reg c1) c2) during register
1379 addition_operation (rtx op, enum machine_mode mode)
1381 if (GET_MODE (op) != mode && mode != VOIDmode)
1383 if (GET_CODE (op) == PLUS
1384 && register_operand (XEXP (op, 0), mode)
1385 && GET_CODE (XEXP (op, 1)) == CONST_INT
1386 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op, 1)), 'K'))
1391 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
1392 the range defined for C in [I-P]. */
1395 alpha_const_ok_for_letter_p (HOST_WIDE_INT value, int c)
1400 /* An unsigned 8 bit constant. */
1401 return (unsigned HOST_WIDE_INT) value < 0x100;
1403 /* The constant zero. */
1406 /* A signed 16 bit constant. */
1407 return (unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000;
1409 /* A shifted signed 16 bit constant appropriate for LDAH. */
1410 return ((value & 0xffff) == 0
1411 && ((value) >> 31 == -1 || value >> 31 == 0));
1413 /* A constant that can be AND'ed with using a ZAP insn. */
1414 return zap_mask (value);
1416 /* A complemented unsigned 8 bit constant. */
1417 return (unsigned HOST_WIDE_INT) (~ value) < 0x100;
1419 /* A negated unsigned 8 bit constant. */
1420 return (unsigned HOST_WIDE_INT) (- value) < 0x100;
1422 /* The constant 1, 2 or 3. */
1423 return value == 1 || value == 2 || value == 3;
1430 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1431 matches for C in [GH]. */
1434 alpha_const_double_ok_for_letter_p (rtx value, int c)
1439 /* The floating point zero constant. */
1440 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
1441 && value == CONST0_RTX (GET_MODE (value)));
1444 /* A valid operand of a ZAP insn. */
1445 return (GET_MODE (value) == VOIDmode
1446 && zap_mask (CONST_DOUBLE_LOW (value))
1447 && zap_mask (CONST_DOUBLE_HIGH (value)));
1454 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1458 alpha_extra_constraint (rtx value, int c)
1463 return normal_memory_operand (value, VOIDmode);
1465 return direct_call_operand (value, Pmode);
1467 return (GET_CODE (value) == CONST_INT
1468 && (unsigned HOST_WIDE_INT) INTVAL (value) < 64);
1470 return GET_CODE (value) == HIGH;
1472 return TARGET_ABI_UNICOSMK && symbolic_operand (value, VOIDmode);
1474 return (GET_CODE (value) == CONST_VECTOR
1475 && value == CONST0_RTX (GET_MODE (value)));
1481 /* Return 1 if this function can directly return via $26. */
1484 direct_return (void)
1486 return (! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK
1488 && alpha_sa_size () == 0
1489 && get_frame_size () == 0
1490 && current_function_outgoing_args_size == 0
1491 && current_function_pretend_args_size == 0);
1494 /* Return the ADDR_VEC associated with a tablejump insn. */
1497 alpha_tablejump_addr_vec (rtx insn)
1501 tmp = JUMP_LABEL (insn);
1504 tmp = NEXT_INSN (tmp);
1507 if (GET_CODE (tmp) == JUMP_INSN
1508 && GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC)
1509 return PATTERN (tmp);
1513 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
1516 alpha_tablejump_best_label (rtx insn)
1518 rtx jump_table = alpha_tablejump_addr_vec (insn);
1519 rtx best_label = NULL_RTX;
1521 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
1522 there for edge frequency counts from profile data. */
1526 int n_labels = XVECLEN (jump_table, 1);
1527 int best_count = -1;
1530 for (i = 0; i < n_labels; i++)
1534 for (j = i + 1; j < n_labels; j++)
1535 if (XEXP (XVECEXP (jump_table, 1, i), 0)
1536 == XEXP (XVECEXP (jump_table, 1, j), 0))
1539 if (count > best_count)
1540 best_count = count, best_label = XVECEXP (jump_table, 1, i);
1544 return best_label ? best_label : const0_rtx;
1547 /* Return the TLS model to use for SYMBOL. */
1549 static enum tls_model
1550 tls_symbolic_operand_type (rtx symbol)
1552 enum tls_model model;
1554 if (GET_CODE (symbol) != SYMBOL_REF)
1556 model = SYMBOL_REF_TLS_MODEL (symbol);
1558 /* Local-exec with a 64-bit size is the same code as initial-exec. */
1559 if (model == TLS_MODEL_LOCAL_EXEC && alpha_tls_size == 64)
1560 model = TLS_MODEL_INITIAL_EXEC;
1565 /* Return true if the function DECL will share the same GP as any
1566 function in the current unit of translation. */
1569 decl_has_samegp (tree decl)
1571 /* Functions that are not local can be overridden, and thus may
1572 not share the same gp. */
1573 if (!(*targetm.binds_local_p) (decl))
1576 /* If -msmall-data is in effect, assume that there is only one GP
1577 for the module, and so any local symbol has this property. We
1578 need explicit relocations to be able to enforce this for symbols
1579 not defined in this unit of translation, however. */
1580 if (TARGET_EXPLICIT_RELOCS && TARGET_SMALL_DATA)
1583 /* Functions that are not external are defined in this UoT. */
1584 /* ??? Irritatingly, static functions not yet emitted are still
1585 marked "external". Apply this to non-static functions only. */
1586 return !TREE_PUBLIC (decl) || !DECL_EXTERNAL (decl);
1589 /* Return true if EXP should be placed in the small data section. */
1592 alpha_in_small_data_p (tree exp)
1594 /* We want to merge strings, so we never consider them small data. */
1595 if (TREE_CODE (exp) == STRING_CST)
1598 /* Functions are never in the small data area. Duh. */
1599 if (TREE_CODE (exp) == FUNCTION_DECL)
1602 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
1604 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
1605 if (strcmp (section, ".sdata") == 0
1606 || strcmp (section, ".sbss") == 0)
1611 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
1613 /* If this is an incomplete type with size 0, then we can't put it
1614 in sdata because it might be too big when completed. */
1615 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
1622 #if TARGET_ABI_OPEN_VMS
1624 alpha_linkage_symbol_p (const char *symname)
1626 int symlen = strlen (symname);
1629 return strcmp (&symname [symlen - 4], "..lk") == 0;
1634 #define LINKAGE_SYMBOL_REF_P(X) \
1635 ((GET_CODE (X) == SYMBOL_REF \
1636 && alpha_linkage_symbol_p (XSTR (X, 0))) \
1637 || (GET_CODE (X) == CONST \
1638 && GET_CODE (XEXP (X, 0)) == PLUS \
1639 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
1640 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
1643 /* legitimate_address_p recognizes an RTL expression that is a valid
1644 memory address for an instruction. The MODE argument is the
1645 machine mode for the MEM expression that wants to use this address.
1647 For Alpha, we have either a constant address or the sum of a
1648 register and a constant address, or just a register. For DImode,
1649 any of those forms can be surrounded with an AND that clear the
1650 low-order three bits; this is an "unaligned" access. */
1653 alpha_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1655 /* If this is an ldq_u type address, discard the outer AND. */
1657 && GET_CODE (x) == AND
1658 && GET_CODE (XEXP (x, 1)) == CONST_INT
1659 && INTVAL (XEXP (x, 1)) == -8)
1662 /* Discard non-paradoxical subregs. */
1663 if (GET_CODE (x) == SUBREG
1664 && (GET_MODE_SIZE (GET_MODE (x))
1665 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
1668 /* Unadorned general registers are valid. */
1671 ? STRICT_REG_OK_FOR_BASE_P (x)
1672 : NONSTRICT_REG_OK_FOR_BASE_P (x)))
1675 /* Constant addresses (i.e. +/- 32k) are valid. */
1676 if (CONSTANT_ADDRESS_P (x))
1679 #if TARGET_ABI_OPEN_VMS
1680 if (LINKAGE_SYMBOL_REF_P (x))
1684 /* Register plus a small constant offset is valid. */
1685 if (GET_CODE (x) == PLUS)
1687 rtx ofs = XEXP (x, 1);
1690 /* Discard non-paradoxical subregs. */
1691 if (GET_CODE (x) == SUBREG
1692 && (GET_MODE_SIZE (GET_MODE (x))
1693 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
1699 && NONSTRICT_REG_OK_FP_BASE_P (x)
1700 && GET_CODE (ofs) == CONST_INT)
1703 ? STRICT_REG_OK_FOR_BASE_P (x)
1704 : NONSTRICT_REG_OK_FOR_BASE_P (x))
1705 && CONSTANT_ADDRESS_P (ofs))
1708 else if (GET_CODE (x) == ADDRESSOF
1709 && GET_CODE (ofs) == CONST_INT)
1713 /* If we're managing explicit relocations, LO_SUM is valid, as
1714 are small data symbols. */
1715 else if (TARGET_EXPLICIT_RELOCS)
1717 if (small_symbolic_operand (x, Pmode))
1720 if (GET_CODE (x) == LO_SUM)
1722 rtx ofs = XEXP (x, 1);
1725 /* Discard non-paradoxical subregs. */
1726 if (GET_CODE (x) == SUBREG
1727 && (GET_MODE_SIZE (GET_MODE (x))
1728 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
1731 /* Must have a valid base register. */
1734 ? STRICT_REG_OK_FOR_BASE_P (x)
1735 : NONSTRICT_REG_OK_FOR_BASE_P (x))))
1738 /* The symbol must be local. */
1739 if (local_symbolic_operand (ofs, Pmode)
1740 || dtp32_symbolic_operand (ofs, Pmode)
1741 || tp32_symbolic_operand (ofs, Pmode))
1749 /* Build the SYMBOL_REF for __tls_get_addr. */
1751 static GTY(()) rtx tls_get_addr_libfunc;
1754 get_tls_get_addr (void)
1756 if (!tls_get_addr_libfunc)
1757 tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr");
1758 return tls_get_addr_libfunc;
1761 /* Try machine-dependent ways of modifying an illegitimate address
1762 to be legitimate. If we find one, return the new, valid address. */
1765 alpha_legitimize_address (rtx x, rtx scratch,
1766 enum machine_mode mode ATTRIBUTE_UNUSED)
1768 HOST_WIDE_INT addend;
1770 /* If the address is (plus reg const_int) and the CONST_INT is not a
1771 valid offset, compute the high part of the constant and add it to
1772 the register. Then our address is (plus temp low-part-const). */
1773 if (GET_CODE (x) == PLUS
1774 && GET_CODE (XEXP (x, 0)) == REG
1775 && GET_CODE (XEXP (x, 1)) == CONST_INT
1776 && ! CONSTANT_ADDRESS_P (XEXP (x, 1)))
1778 addend = INTVAL (XEXP (x, 1));
1783 /* If the address is (const (plus FOO const_int)), find the low-order
1784 part of the CONST_INT. Then load FOO plus any high-order part of the
1785 CONST_INT into a register. Our address is (plus reg low-part-const).
1786 This is done to reduce the number of GOT entries. */
1788 && GET_CODE (x) == CONST
1789 && GET_CODE (XEXP (x, 0)) == PLUS
1790 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
1792 addend = INTVAL (XEXP (XEXP (x, 0), 1));
1793 x = force_reg (Pmode, XEXP (XEXP (x, 0), 0));
1797 /* If we have a (plus reg const), emit the load as in (2), then add
1798 the two registers, and finally generate (plus reg low-part-const) as
1801 && GET_CODE (x) == PLUS
1802 && GET_CODE (XEXP (x, 0)) == REG
1803 && GET_CODE (XEXP (x, 1)) == CONST
1804 && GET_CODE (XEXP (XEXP (x, 1), 0)) == PLUS
1805 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == CONST_INT)
1807 addend = INTVAL (XEXP (XEXP (XEXP (x, 1), 0), 1));
1808 x = expand_simple_binop (Pmode, PLUS, XEXP (x, 0),
1809 XEXP (XEXP (XEXP (x, 1), 0), 0),
1810 NULL_RTX, 1, OPTAB_LIB_WIDEN);
1814 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
1815 if (TARGET_EXPLICIT_RELOCS && symbolic_operand (x, Pmode))
1817 rtx r0, r16, eqv, tga, tp, insn, dest, seq;
1819 switch (tls_symbolic_operand_type (x))
1821 case TLS_MODEL_GLOBAL_DYNAMIC:
1824 r0 = gen_rtx_REG (Pmode, 0);
1825 r16 = gen_rtx_REG (Pmode, 16);
1826 tga = get_tls_get_addr ();
1827 dest = gen_reg_rtx (Pmode);
1828 seq = GEN_INT (alpha_next_sequence_number++);
1830 emit_insn (gen_movdi_er_tlsgd (r16, pic_offset_table_rtx, x, seq));
1831 insn = gen_call_value_osf_tlsgd (r0, tga, seq);
1832 insn = emit_call_insn (insn);
1833 CONST_OR_PURE_CALL_P (insn) = 1;
1834 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r16);
1836 insn = get_insns ();
1839 emit_libcall_block (insn, dest, r0, x);
1842 case TLS_MODEL_LOCAL_DYNAMIC:
1845 r0 = gen_rtx_REG (Pmode, 0);
1846 r16 = gen_rtx_REG (Pmode, 16);
1847 tga = get_tls_get_addr ();
1848 scratch = gen_reg_rtx (Pmode);
1849 seq = GEN_INT (alpha_next_sequence_number++);
1851 emit_insn (gen_movdi_er_tlsldm (r16, pic_offset_table_rtx, seq));
1852 insn = gen_call_value_osf_tlsldm (r0, tga, seq);
1853 insn = emit_call_insn (insn);
1854 CONST_OR_PURE_CALL_P (insn) = 1;
1855 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r16);
1857 insn = get_insns ();
1860 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
1861 UNSPEC_TLSLDM_CALL);
1862 emit_libcall_block (insn, scratch, r0, eqv);
1864 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPREL);
1865 eqv = gen_rtx_CONST (Pmode, eqv);
1867 if (alpha_tls_size == 64)
1869 dest = gen_reg_rtx (Pmode);
1870 emit_insn (gen_rtx_SET (VOIDmode, dest, eqv));
1871 emit_insn (gen_adddi3 (dest, dest, scratch));
1874 if (alpha_tls_size == 32)
1876 insn = gen_rtx_HIGH (Pmode, eqv);
1877 insn = gen_rtx_PLUS (Pmode, scratch, insn);
1878 scratch = gen_reg_rtx (Pmode);
1879 emit_insn (gen_rtx_SET (VOIDmode, scratch, insn));
1881 return gen_rtx_LO_SUM (Pmode, scratch, eqv);
1883 case TLS_MODEL_INITIAL_EXEC:
1884 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_TPREL);
1885 eqv = gen_rtx_CONST (Pmode, eqv);
1886 tp = gen_reg_rtx (Pmode);
1887 scratch = gen_reg_rtx (Pmode);
1888 dest = gen_reg_rtx (Pmode);
1890 emit_insn (gen_load_tp (tp));
1891 emit_insn (gen_rtx_SET (VOIDmode, scratch, eqv));
1892 emit_insn (gen_adddi3 (dest, tp, scratch));
1895 case TLS_MODEL_LOCAL_EXEC:
1896 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_TPREL);
1897 eqv = gen_rtx_CONST (Pmode, eqv);
1898 tp = gen_reg_rtx (Pmode);
1900 emit_insn (gen_load_tp (tp));
1901 if (alpha_tls_size == 32)
1903 insn = gen_rtx_HIGH (Pmode, eqv);
1904 insn = gen_rtx_PLUS (Pmode, tp, insn);
1905 tp = gen_reg_rtx (Pmode);
1906 emit_insn (gen_rtx_SET (VOIDmode, tp, insn));
1908 return gen_rtx_LO_SUM (Pmode, tp, eqv);
1911 if (local_symbolic_operand (x, Pmode))
1913 if (small_symbolic_operand (x, Pmode))
1917 if (!no_new_pseudos)
1918 scratch = gen_reg_rtx (Pmode);
1919 emit_insn (gen_rtx_SET (VOIDmode, scratch,
1920 gen_rtx_HIGH (Pmode, x)));
1921 return gen_rtx_LO_SUM (Pmode, scratch, x);
1930 HOST_WIDE_INT low, high;
1932 low = ((addend & 0xffff) ^ 0x8000) - 0x8000;
1934 high = ((addend & 0xffffffff) ^ 0x80000000) - 0x80000000;
1938 x = expand_simple_binop (Pmode, PLUS, x, GEN_INT (addend),
1939 (no_new_pseudos ? scratch : NULL_RTX),
1940 1, OPTAB_LIB_WIDEN);
1942 x = expand_simple_binop (Pmode, PLUS, x, GEN_INT (high),
1943 (no_new_pseudos ? scratch : NULL_RTX),
1944 1, OPTAB_LIB_WIDEN);
1946 return plus_constant (x, low);
1950 /* Primarily this is required for TLS symbols, but given that our move
1951 patterns *ought* to be able to handle any symbol at any time, we
1952 should never be spilling symbolic operands to the constant pool, ever. */
1955 alpha_cannot_force_const_mem (rtx x)
1957 enum rtx_code code = GET_CODE (x);
1958 return code == SYMBOL_REF || code == LABEL_REF || code == CONST;
1961 /* We do not allow indirect calls to be optimized into sibling calls, nor
1962 can we allow a call to a function with a different GP to be optimized
1966 alpha_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
1968 /* Can't do indirect tail calls, since we don't know if the target
1969 uses the same GP. */
1973 /* Otherwise, we can make a tail call if the target function shares
1975 return decl_has_samegp (decl);
1978 /* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a
1979 small symbolic operand until after reload. At which point we need
1980 to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref))
1981 so that sched2 has the proper dependency information. */
1984 some_small_symbolic_operand_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
1988 /* Don't re-split. */
1989 if (GET_CODE (x) == LO_SUM)
1992 return small_symbolic_operand (x, Pmode) != 0;
1996 some_small_symbolic_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1998 return for_each_rtx (&x, some_small_symbolic_operand_1, NULL);
2002 split_small_symbolic_operand_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
2006 /* Don't re-split. */
2007 if (GET_CODE (x) == LO_SUM)
2010 if (small_symbolic_operand (x, Pmode))
2012 x = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, x);
2021 split_small_symbolic_operand (rtx x)
2024 for_each_rtx (&x, split_small_symbolic_operand_1, NULL);
2028 /* Indicate that INSN cannot be duplicated. This is true for any insn
2029 that we've marked with gpdisp relocs, since those have to stay in
2030 1-1 correspondence with one another.
2032 Technically we could copy them if we could set up a mapping from one
2033 sequence number to another, across the set of insns to be duplicated.
2034 This seems overly complicated and error-prone since interblock motion
2035 from sched-ebb could move one of the pair of insns to a different block.
2037 Also cannot allow jsr insns to be duplicated. If they throw exceptions,
2038 then they'll be in a different block from their ldgp. Which could lead
2039 the bb reorder code to think that it would be ok to copy just the block
2040 containing the call and branch to the block containing the ldgp. */
2043 alpha_cannot_copy_insn_p (rtx insn)
2045 if (!reload_completed || !TARGET_EXPLICIT_RELOCS)
2047 if (recog_memoized (insn) >= 0)
2048 return get_attr_cannot_copy (insn);
2054 /* Try a machine-dependent way of reloading an illegitimate address
2055 operand. If we find one, push the reload and return the new rtx. */
2058 alpha_legitimize_reload_address (rtx x,
2059 enum machine_mode mode ATTRIBUTE_UNUSED,
2060 int opnum, int type,
2061 int ind_levels ATTRIBUTE_UNUSED)
2063 /* We must recognize output that we have already generated ourselves. */
2064 if (GET_CODE (x) == PLUS
2065 && GET_CODE (XEXP (x, 0)) == PLUS
2066 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
2067 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2068 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2070 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2071 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
2076 /* We wish to handle large displacements off a base register by
2077 splitting the addend across an ldah and the mem insn. This
2078 cuts number of extra insns needed from 3 to 1. */
2079 if (GET_CODE (x) == PLUS
2080 && GET_CODE (XEXP (x, 0)) == REG
2081 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2082 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x, 0)))
2083 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2085 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
2086 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
2088 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
2090 /* Check for 32-bit overflow. */
2091 if (high + low != val)
2094 /* Reload the high part into a base reg; leave the low part
2095 in the mem directly. */
2096 x = gen_rtx_PLUS (GET_MODE (x),
2097 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
2101 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2102 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
2110 /* Compute a (partial) cost for rtx X. Return true if the complete
2111 cost has been computed, and false if subexpressions should be
2112 scanned. In either case, *TOTAL contains the cost result. */
2115 alpha_rtx_costs (rtx x, int code, int outer_code, int *total)
2117 enum machine_mode mode = GET_MODE (x);
2118 bool float_mode_p = FLOAT_MODE_P (mode);
2122 /* If this is an 8-bit constant, return zero since it can be used
2123 nearly anywhere with no cost. If it is a valid operand for an
2124 ADD or AND, likewise return 0 if we know it will be used in that
2125 context. Otherwise, return 2 since it might be used there later.
2126 All other constants take at least two insns. */
2128 if (INTVAL (x) >= 0 && INTVAL (x) < 256)
2136 if (x == CONST0_RTX (mode))
2138 else if ((outer_code == PLUS && add_operand (x, VOIDmode))
2139 || (outer_code == AND && and_operand (x, VOIDmode)))
2141 else if (add_operand (x, VOIDmode) || and_operand (x, VOIDmode))
2144 *total = COSTS_N_INSNS (2);
2150 if (TARGET_EXPLICIT_RELOCS && small_symbolic_operand (x, VOIDmode))
2151 *total = COSTS_N_INSNS (outer_code != MEM);
2152 else if (TARGET_EXPLICIT_RELOCS && local_symbolic_operand (x, VOIDmode))
2153 *total = COSTS_N_INSNS (1 + (outer_code != MEM));
2154 else if (tls_symbolic_operand_type (x))
2155 /* Estimate of cost for call_pal rduniq. */
2156 *total = COSTS_N_INSNS (15);
2158 /* Otherwise we do a load from the GOT. */
2159 *total = COSTS_N_INSNS (alpha_memory_latency);
2165 *total = alpha_rtx_cost_data[alpha_cpu].fp_add;
2166 else if (GET_CODE (XEXP (x, 0)) == MULT
2167 && const48_operand (XEXP (XEXP (x, 0), 1), VOIDmode))
2169 *total = (rtx_cost (XEXP (XEXP (x, 0), 0), outer_code)
2170 + rtx_cost (XEXP (x, 1), outer_code) + 2);
2177 *total = alpha_rtx_cost_data[alpha_cpu].fp_mult;
2178 else if (mode == DImode)
2179 *total = alpha_rtx_cost_data[alpha_cpu].int_mult_di;
2181 *total = alpha_rtx_cost_data[alpha_cpu].int_mult_si;
2185 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2186 && INTVAL (XEXP (x, 1)) <= 3)
2188 *total = COSTS_N_INSNS (1);
2195 *total = alpha_rtx_cost_data[alpha_cpu].int_shift;
2200 *total = alpha_rtx_cost_data[alpha_cpu].fp_add;
2202 *total = alpha_rtx_cost_data[alpha_cpu].int_cmov;
2210 *total = COSTS_N_INSNS (70); /* ??? */
2211 else if (mode == SFmode)
2212 *total = alpha_rtx_cost_data[alpha_cpu].fp_div_sf;
2214 *total = alpha_rtx_cost_data[alpha_cpu].fp_div_df;
2218 *total = COSTS_N_INSNS (alpha_memory_latency);
2224 *total = COSTS_N_INSNS (1);
2232 *total = COSTS_N_INSNS (1) + alpha_rtx_cost_data[alpha_cpu].int_cmov;
2238 case UNSIGNED_FLOAT:
2242 case FLOAT_TRUNCATE:
2243 *total = alpha_rtx_cost_data[alpha_cpu].fp_add;
2251 /* REF is an alignable memory location. Place an aligned SImode
2252 reference into *PALIGNED_MEM and the number of bits to shift into
2253 *PBITNUM. SCRATCH is a free register for use in reloading out
2254 of range stack slots. */
2257 get_aligned_mem (rtx ref, rtx *paligned_mem, rtx *pbitnum)
2260 HOST_WIDE_INT offset = 0;
2262 if (GET_CODE (ref) != MEM)
2265 if (reload_in_progress
2266 && ! memory_address_p (GET_MODE (ref), XEXP (ref, 0)))
2268 base = find_replacement (&XEXP (ref, 0));
2270 if (! memory_address_p (GET_MODE (ref), base))
2275 base = XEXP (ref, 0);
2278 if (GET_CODE (base) == PLUS)
2279 offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
2282 = widen_memory_access (ref, SImode, (offset & ~3) - offset);
2284 if (WORDS_BIG_ENDIAN)
2285 *pbitnum = GEN_INT (32 - (GET_MODE_BITSIZE (GET_MODE (ref))
2286 + (offset & 3) * 8));
2288 *pbitnum = GEN_INT ((offset & 3) * 8);
2291 /* Similar, but just get the address. Handle the two reload cases.
2292 Add EXTRA_OFFSET to the address we return. */
2295 get_unaligned_address (rtx ref, int extra_offset)
2298 HOST_WIDE_INT offset = 0;
2300 if (GET_CODE (ref) != MEM)
2303 if (reload_in_progress
2304 && ! memory_address_p (GET_MODE (ref), XEXP (ref, 0)))
2306 base = find_replacement (&XEXP (ref, 0));
2308 if (! memory_address_p (GET_MODE (ref), base))
2313 base = XEXP (ref, 0);
2316 if (GET_CODE (base) == PLUS)
2317 offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
2319 return plus_constant (base, offset + extra_offset);
2322 /* On the Alpha, all (non-symbolic) constants except zero go into
2323 a floating-point register via memory. Note that we cannot
2324 return anything that is not a subset of CLASS, and that some
2325 symbolic constants cannot be dropped to memory. */
2328 alpha_preferred_reload_class(rtx x, enum reg_class class)
2330 /* Zero is present in any register class. */
2331 if (x == CONST0_RTX (GET_MODE (x)))
2334 /* These sorts of constants we can easily drop to memory. */
2335 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
2337 if (class == FLOAT_REGS)
2339 if (class == ALL_REGS)
2340 return GENERAL_REGS;
2344 /* All other kinds of constants should not (and in the case of HIGH
2345 cannot) be dropped to memory -- instead we use a GENERAL_REGS
2346 secondary reload. */
2348 return (class == ALL_REGS ? GENERAL_REGS : class);
2353 /* Loading and storing HImode or QImode values to and from memory
2354 usually requires a scratch register. The exceptions are loading
2355 QImode and HImode from an aligned address to a general register
2356 unless byte instructions are permitted.
2358 We also cannot load an unaligned address or a paradoxical SUBREG
2359 into an FP register.
2361 We also cannot do integral arithmetic into FP regs, as might result
2362 from register elimination into a DImode fp register. */
2365 secondary_reload_class (enum reg_class class, enum machine_mode mode,
2368 if ((mode == QImode || mode == HImode) && ! TARGET_BWX)
2370 if (GET_CODE (x) == MEM
2371 || (GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER)
2372 || (GET_CODE (x) == SUBREG
2373 && (GET_CODE (SUBREG_REG (x)) == MEM
2374 || (GET_CODE (SUBREG_REG (x)) == REG
2375 && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER))))
2377 if (!in || !aligned_memory_operand(x, mode))
2378 return GENERAL_REGS;
2382 if (class == FLOAT_REGS)
2384 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == AND)
2385 return GENERAL_REGS;
2387 if (GET_CODE (x) == SUBREG
2388 && (GET_MODE_SIZE (GET_MODE (x))
2389 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
2390 return GENERAL_REGS;
2392 if (in && INTEGRAL_MODE_P (mode)
2393 && ! (memory_operand (x, mode) || x == const0_rtx))
2394 return GENERAL_REGS;
2400 /* Subfunction of the following function. Update the flags of any MEM
2401 found in part of X. */
2404 alpha_set_memflags_1 (rtx x, int in_struct_p, int volatile_p, int unchanging_p)
2408 switch (GET_CODE (x))
2414 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
2415 alpha_set_memflags_1 (XVECEXP (x, 0, i), in_struct_p, volatile_p,
2420 alpha_set_memflags_1 (PATTERN (x), in_struct_p, volatile_p,
2425 alpha_set_memflags_1 (SET_DEST (x), in_struct_p, volatile_p,
2427 alpha_set_memflags_1 (SET_SRC (x), in_struct_p, volatile_p,
2432 MEM_IN_STRUCT_P (x) = in_struct_p;
2433 MEM_VOLATILE_P (x) = volatile_p;
2434 RTX_UNCHANGING_P (x) = unchanging_p;
2435 /* Sadly, we cannot use alias sets because the extra aliasing
2436 produced by the AND interferes. Given that two-byte quantities
2437 are the only thing we would be able to differentiate anyway,
2438 there does not seem to be any point in convoluting the early
2439 out of the alias check. */
2447 /* Given INSN, which is an INSN list or the PATTERN of a single insn
2448 generated to perform a memory operation, look for any MEMs in either
2449 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
2450 volatile flags from REF into each of the MEMs found. If REF is not
2451 a MEM, don't do anything. */
2454 alpha_set_memflags (rtx insn, rtx ref)
2456 int in_struct_p, volatile_p, unchanging_p;
2458 if (GET_CODE (ref) != MEM)
2461 in_struct_p = MEM_IN_STRUCT_P (ref);
2462 volatile_p = MEM_VOLATILE_P (ref);
2463 unchanging_p = RTX_UNCHANGING_P (ref);
2465 /* This is only called from alpha.md, after having had something
2466 generated from one of the insn patterns. So if everything is
2467 zero, the pattern is already up-to-date. */
2468 if (! in_struct_p && ! volatile_p && ! unchanging_p)
2471 alpha_set_memflags_1 (insn, in_struct_p, volatile_p, unchanging_p);
2474 /* Internal routine for alpha_emit_set_const to check for N or below insns. */
2477 alpha_emit_set_const_1 (rtx target, enum machine_mode mode,
2478 HOST_WIDE_INT c, int n)
2482 /* Use a pseudo if highly optimizing and still generating RTL. */
2484 = (flag_expensive_optimizations && !no_new_pseudos ? 0 : target);
2487 /* If this is a sign-extended 32-bit constant, we can do this in at most
2488 three insns, so do it if we have enough insns left. We always have
2489 a sign-extended 32-bit constant when compiling on a narrow machine. */
2491 if (HOST_BITS_PER_WIDE_INT != 64
2492 || c >> 31 == -1 || c >> 31 == 0)
2494 HOST_WIDE_INT low = ((c & 0xffff) ^ 0x8000) - 0x8000;
2495 HOST_WIDE_INT tmp1 = c - low;
2496 HOST_WIDE_INT high = (((tmp1 >> 16) & 0xffff) ^ 0x8000) - 0x8000;
2497 HOST_WIDE_INT extra = 0;
2499 /* If HIGH will be interpreted as negative but the constant is
2500 positive, we must adjust it to do two ldha insns. */
2502 if ((high & 0x8000) != 0 && c >= 0)
2506 high = ((tmp1 >> 16) & 0xffff) - 2 * ((tmp1 >> 16) & 0x8000);
2509 if (c == low || (low == 0 && extra == 0))
2511 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
2512 but that meant that we can't handle INT_MIN on 32-bit machines
2513 (like NT/Alpha), because we recurse indefinitely through
2514 emit_move_insn to gen_movdi. So instead, since we know exactly
2515 what we want, create it explicitly. */
2518 target = gen_reg_rtx (mode);
2519 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (c)));
2522 else if (n >= 2 + (extra != 0))
2526 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (high << 16)));
2530 temp = copy_to_suggested_reg (GEN_INT (high << 16),
2533 /* As of 2002-02-23, addsi3 is only available when not optimizing.
2534 This means that if we go through expand_binop, we'll try to
2535 generate extensions, etc, which will require new pseudos, which
2536 will fail during some split phases. The SImode add patterns
2537 still exist, but are not named. So build the insns by hand. */
2542 subtarget = gen_reg_rtx (mode);
2543 insn = gen_rtx_PLUS (mode, temp, GEN_INT (extra << 16));
2544 insn = gen_rtx_SET (VOIDmode, subtarget, insn);
2550 target = gen_reg_rtx (mode);
2551 insn = gen_rtx_PLUS (mode, temp, GEN_INT (low));
2552 insn = gen_rtx_SET (VOIDmode, target, insn);
2558 /* If we couldn't do it that way, try some other methods. But if we have
2559 no instructions left, don't bother. Likewise, if this is SImode and
2560 we can't make pseudos, we can't do anything since the expand_binop
2561 and expand_unop calls will widen and try to make pseudos. */
2563 if (n == 1 || (mode == SImode && no_new_pseudos))
2566 /* Next, see if we can load a related constant and then shift and possibly
2567 negate it to get the constant we want. Try this once each increasing
2568 numbers of insns. */
2570 for (i = 1; i < n; i++)
2572 /* First, see if minus some low bits, we've an easy load of
2575 new = ((c & 0xffff) ^ 0x8000) - 0x8000;
2577 && (temp = alpha_emit_set_const (subtarget, mode, c - new, i)) != 0)
2578 return expand_binop (mode, add_optab, temp, GEN_INT (new),
2579 target, 0, OPTAB_WIDEN);
2581 /* Next try complementing. */
2582 if ((temp = alpha_emit_set_const (subtarget, mode, ~ c, i)) != 0)
2583 return expand_unop (mode, one_cmpl_optab, temp, target, 0);
2585 /* Next try to form a constant and do a left shift. We can do this
2586 if some low-order bits are zero; the exact_log2 call below tells
2587 us that information. The bits we are shifting out could be any
2588 value, but here we'll just try the 0- and sign-extended forms of
2589 the constant. To try to increase the chance of having the same
2590 constant in more than one insn, start at the highest number of
2591 bits to shift, but try all possibilities in case a ZAPNOT will
2594 if ((bits = exact_log2 (c & - c)) > 0)
2595 for (; bits > 0; bits--)
2596 if ((temp = (alpha_emit_set_const
2597 (subtarget, mode, c >> bits, i))) != 0
2598 || ((temp = (alpha_emit_set_const
2600 ((unsigned HOST_WIDE_INT) c) >> bits, i)))
2602 return expand_binop (mode, ashl_optab, temp, GEN_INT (bits),
2603 target, 0, OPTAB_WIDEN);
2605 /* Now try high-order zero bits. Here we try the shifted-in bits as
2606 all zero and all ones. Be careful to avoid shifting outside the
2607 mode and to avoid shifting outside the host wide int size. */
2608 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
2609 confuse the recursive call and set all of the high 32 bits. */
2611 if ((bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
2612 - floor_log2 (c) - 1 - (HOST_BITS_PER_WIDE_INT < 64))) > 0)
2613 for (; bits > 0; bits--)
2614 if ((temp = alpha_emit_set_const (subtarget, mode,
2616 || ((temp = (alpha_emit_set_const
2618 ((c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1)),
2621 return expand_binop (mode, lshr_optab, temp, GEN_INT (bits),
2622 target, 1, OPTAB_WIDEN);
2624 /* Now try high-order 1 bits. We get that with a sign-extension.
2625 But one bit isn't enough here. Be careful to avoid shifting outside
2626 the mode and to avoid shifting outside the host wide int size. */
2628 if ((bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
2629 - floor_log2 (~ c) - 2)) > 0)
2630 for (; bits > 0; bits--)
2631 if ((temp = alpha_emit_set_const (subtarget, mode,
2633 || ((temp = (alpha_emit_set_const
2635 ((c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1)),
2638 return expand_binop (mode, ashr_optab, temp, GEN_INT (bits),
2639 target, 0, OPTAB_WIDEN);
2642 #if HOST_BITS_PER_WIDE_INT == 64
2643 /* Finally, see if can load a value into the target that is the same as the
2644 constant except that all bytes that are 0 are changed to be 0xff. If we
2645 can, then we can do a ZAPNOT to obtain the desired constant. */
2648 for (i = 0; i < 64; i += 8)
2649 if ((new & ((HOST_WIDE_INT) 0xff << i)) == 0)
2650 new |= (HOST_WIDE_INT) 0xff << i;
2652 /* We are only called for SImode and DImode. If this is SImode, ensure that
2653 we are sign extended to a full word. */
2656 new = ((new & 0xffffffff) ^ 0x80000000) - 0x80000000;
2658 if (new != c && new != -1
2659 && (temp = alpha_emit_set_const (subtarget, mode, new, n - 1)) != 0)
2660 return expand_binop (mode, and_optab, temp, GEN_INT (c | ~ new),
2661 target, 0, OPTAB_WIDEN);
2667 /* Try to output insns to set TARGET equal to the constant C if it can be
2668 done in less than N insns. Do all computations in MODE. Returns the place
2669 where the output has been placed if it can be done and the insns have been
2670 emitted. If it would take more than N insns, zero is returned and no
2671 insns and emitted. */
2674 alpha_emit_set_const (rtx target, enum machine_mode mode,
2675 HOST_WIDE_INT c, int n)
2678 rtx orig_target = target;
2681 /* If we can't make any pseudos, TARGET is an SImode hard register, we
2682 can't load this constant in one insn, do this in DImode. */
2683 if (no_new_pseudos && mode == SImode
2684 && GET_CODE (target) == REG && REGNO (target) < FIRST_PSEUDO_REGISTER
2685 && (result = alpha_emit_set_const_1 (target, mode, c, 1)) == 0)
2687 target = gen_lowpart (DImode, target);
2691 /* Try 1 insn, then 2, then up to N. */
2692 for (i = 1; i <= n; i++)
2694 result = alpha_emit_set_const_1 (target, mode, c, i);
2697 rtx insn = get_last_insn ();
2698 rtx set = single_set (insn);
2699 if (! CONSTANT_P (SET_SRC (set)))
2700 set_unique_reg_note (get_last_insn (), REG_EQUAL, GEN_INT (c));
2705 /* Allow for the case where we changed the mode of TARGET. */
2706 if (result == target)
2707 result = orig_target;
2712 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
2713 fall back to a straight forward decomposition. We do this to avoid
2714 exponential run times encountered when looking for longer sequences
2715 with alpha_emit_set_const. */
2718 alpha_emit_set_long_const (rtx target, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
2720 HOST_WIDE_INT d1, d2, d3, d4;
2722 /* Decompose the entire word */
2723 #if HOST_BITS_PER_WIDE_INT >= 64
2724 if (c2 != -(c1 < 0))
2726 d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
2728 d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
2729 c1 = (c1 - d2) >> 32;
2730 d3 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
2732 d4 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
2736 d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
2738 d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
2742 d3 = ((c2 & 0xffff) ^ 0x8000) - 0x8000;
2744 d4 = ((c2 & 0xffffffff) ^ 0x80000000) - 0x80000000;
2749 /* Construct the high word */
2752 emit_move_insn (target, GEN_INT (d4));
2754 emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d3)));
2757 emit_move_insn (target, GEN_INT (d3));
2759 /* Shift it into place */
2760 emit_move_insn (target, gen_rtx_ASHIFT (DImode, target, GEN_INT (32)));
2762 /* Add in the low bits. */
2764 emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d2)));
2766 emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d1)));
2771 /* Expand a move instruction; return true if all work is done.
2772 We don't handle non-bwx subword loads here. */
2775 alpha_expand_mov (enum machine_mode mode, rtx *operands)
2777 /* If the output is not a register, the input must be. */
2778 if (GET_CODE (operands[0]) == MEM
2779 && ! reg_or_0_operand (operands[1], mode))
2780 operands[1] = force_reg (mode, operands[1]);
2782 /* Allow legitimize_address to perform some simplifications. */
2783 if (mode == Pmode && symbolic_operand (operands[1], mode))
2787 /* With RTL inlining, at -O3, rtl is generated, stored, then actually
2788 compiled at the end of compilation. In the meantime, someone can
2789 re-encode-section-info on some symbol changing it e.g. from global
2790 to local-not-small. If this happens, we'd have emitted a plain
2791 load rather than a high+losum load and not recognize the insn.
2793 So if rtl inlining is in effect, we delay the global/not-global
2794 decision until rest_of_compilation by wrapping it in an
2796 if (TARGET_EXPLICIT_RELOCS && flag_inline_functions
2797 && rtx_equal_function_value_matters
2798 && global_symbolic_operand (operands[1], mode))
2800 emit_insn (gen_movdi_er_maybe_g (operands[0], operands[1]));
2804 tmp = alpha_legitimize_address (operands[1], operands[0], mode);
2807 if (tmp == operands[0])
2814 /* Early out for non-constants and valid constants. */
2815 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], mode))
2818 /* Split large integers. */
2819 if (GET_CODE (operands[1]) == CONST_INT
2820 || GET_CODE (operands[1]) == CONST_DOUBLE)
2822 HOST_WIDE_INT i0, i1;
2823 rtx temp = NULL_RTX;
2825 if (GET_CODE (operands[1]) == CONST_INT)
2827 i0 = INTVAL (operands[1]);
2830 else if (HOST_BITS_PER_WIDE_INT >= 64)
2832 i0 = CONST_DOUBLE_LOW (operands[1]);
2837 i0 = CONST_DOUBLE_LOW (operands[1]);
2838 i1 = CONST_DOUBLE_HIGH (operands[1]);
2841 if (HOST_BITS_PER_WIDE_INT >= 64 || i1 == -(i0 < 0))
2842 temp = alpha_emit_set_const (operands[0], mode, i0, 3);
2844 if (!temp && TARGET_BUILD_CONSTANTS)
2845 temp = alpha_emit_set_long_const (operands[0], i0, i1);
2849 if (rtx_equal_p (operands[0], temp))
2856 /* Otherwise we've nothing left but to drop the thing to memory. */
2857 operands[1] = force_const_mem (mode, operands[1]);
2858 if (reload_in_progress)
2860 emit_move_insn (operands[0], XEXP (operands[1], 0));
2861 operands[1] = copy_rtx (operands[1]);
2862 XEXP (operands[1], 0) = operands[0];
2865 operands[1] = validize_mem (operands[1]);
2869 /* Expand a non-bwx QImode or HImode move instruction;
2870 return true if all work is done. */
2873 alpha_expand_mov_nobwx (enum machine_mode mode, rtx *operands)
2875 /* If the output is not a register, the input must be. */
2876 if (GET_CODE (operands[0]) == MEM)
2877 operands[1] = force_reg (mode, operands[1]);
2879 /* Handle four memory cases, unaligned and aligned for either the input
2880 or the output. The only case where we can be called during reload is
2881 for aligned loads; all other cases require temporaries. */
2883 if (GET_CODE (operands[1]) == MEM
2884 || (GET_CODE (operands[1]) == SUBREG
2885 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
2886 || (reload_in_progress && GET_CODE (operands[1]) == REG
2887 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
2888 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
2889 && GET_CODE (SUBREG_REG (operands[1])) == REG
2890 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
2892 if (aligned_memory_operand (operands[1], mode))
2894 if (reload_in_progress)
2896 emit_insn ((mode == QImode
2897 ? gen_reload_inqi_help
2898 : gen_reload_inhi_help)
2899 (operands[0], operands[1],
2900 gen_rtx_REG (SImode, REGNO (operands[0]))));
2904 rtx aligned_mem, bitnum;
2905 rtx scratch = gen_reg_rtx (SImode);
2909 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
2911 subtarget = operands[0];
2912 if (GET_CODE (subtarget) == REG)
2913 subtarget = gen_lowpart (DImode, subtarget), copyout = false;
2915 subtarget = gen_reg_rtx (DImode), copyout = true;
2917 emit_insn ((mode == QImode
2918 ? gen_aligned_loadqi
2919 : gen_aligned_loadhi)
2920 (subtarget, aligned_mem, bitnum, scratch));
2923 emit_move_insn (operands[0], gen_lowpart (mode, subtarget));
2928 /* Don't pass these as parameters since that makes the generated
2929 code depend on parameter evaluation order which will cause
2930 bootstrap failures. */
2932 rtx temp1, temp2, seq, subtarget;
2935 temp1 = gen_reg_rtx (DImode);
2936 temp2 = gen_reg_rtx (DImode);
2938 subtarget = operands[0];
2939 if (GET_CODE (subtarget) == REG)
2940 subtarget = gen_lowpart (DImode, subtarget), copyout = false;
2942 subtarget = gen_reg_rtx (DImode), copyout = true;
2944 seq = ((mode == QImode
2945 ? gen_unaligned_loadqi
2946 : gen_unaligned_loadhi)
2947 (subtarget, get_unaligned_address (operands[1], 0),
2949 alpha_set_memflags (seq, operands[1]);
2953 emit_move_insn (operands[0], gen_lowpart (mode, subtarget));
2958 if (GET_CODE (operands[0]) == MEM
2959 || (GET_CODE (operands[0]) == SUBREG
2960 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
2961 || (reload_in_progress && GET_CODE (operands[0]) == REG
2962 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
2963 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
2964 && GET_CODE (SUBREG_REG (operands[0])) == REG
2965 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
2967 if (aligned_memory_operand (operands[0], mode))
2969 rtx aligned_mem, bitnum;
2970 rtx temp1 = gen_reg_rtx (SImode);
2971 rtx temp2 = gen_reg_rtx (SImode);
2973 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
2975 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
2980 rtx temp1 = gen_reg_rtx (DImode);
2981 rtx temp2 = gen_reg_rtx (DImode);
2982 rtx temp3 = gen_reg_rtx (DImode);
2983 rtx seq = ((mode == QImode
2984 ? gen_unaligned_storeqi
2985 : gen_unaligned_storehi)
2986 (get_unaligned_address (operands[0], 0),
2987 operands[1], temp1, temp2, temp3));
2989 alpha_set_memflags (seq, operands[0]);
2998 /* Generate an unsigned DImode to FP conversion. This is the same code
2999 optabs would emit if we didn't have TFmode patterns.
3001 For SFmode, this is the only construction I've found that can pass
3002 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
3003 intermediates will work, because you'll get intermediate rounding
3004 that ruins the end result. Some of this could be fixed by turning
3005 on round-to-positive-infinity, but that requires diddling the fpsr,
3006 which kills performance. I tried turning this around and converting
3007 to a negative number, so that I could turn on /m, but either I did
3008 it wrong or there's something else cause I wound up with the exact
3009 same single-bit error. There is a branch-less form of this same code:
3020 fcmoveq $f10,$f11,$f0
3022 I'm not using it because it's the same number of instructions as
3023 this branch-full form, and it has more serialized long latency
3024 instructions on the critical path.
3026 For DFmode, we can avoid rounding errors by breaking up the word
3027 into two pieces, converting them separately, and adding them back:
3029 LC0: .long 0,0x5f800000
3034 cpyse $f11,$f31,$f10
3035 cpyse $f31,$f11,$f11
3043 This doesn't seem to be a clear-cut win over the optabs form.
3044 It probably all depends on the distribution of numbers being
3045 converted -- in the optabs form, all but high-bit-set has a
3046 much lower minimum execution time. */
3049 alpha_emit_floatuns (rtx operands[2])
3051 rtx neglab, donelab, i0, i1, f0, in, out;
3052 enum machine_mode mode;
3055 in = force_reg (DImode, operands[1]);
3056 mode = GET_MODE (out);
3057 neglab = gen_label_rtx ();
3058 donelab = gen_label_rtx ();
3059 i0 = gen_reg_rtx (DImode);
3060 i1 = gen_reg_rtx (DImode);
3061 f0 = gen_reg_rtx (mode);
3063 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
3065 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
3066 emit_jump_insn (gen_jump (donelab));
3069 emit_label (neglab);
3071 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
3072 emit_insn (gen_anddi3 (i1, in, const1_rtx));
3073 emit_insn (gen_iordi3 (i0, i0, i1));
3074 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
3075 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
3077 emit_label (donelab);
3080 /* Generate the comparison for a conditional branch. */
3083 alpha_emit_conditional_branch (enum rtx_code code)
3085 enum rtx_code cmp_code, branch_code;
3086 enum machine_mode cmp_mode, branch_mode = VOIDmode;
3087 rtx op0 = alpha_compare.op0, op1 = alpha_compare.op1;
3090 if (alpha_compare.fp_p && GET_MODE (op0) == TFmode)
3092 if (! TARGET_HAS_XFLOATING_LIBS)
3095 /* X_floating library comparison functions return
3099 Convert the compare against the raw return value. */
3121 op0 = alpha_emit_xfloating_compare (cmp_code, op0, op1);
3123 alpha_compare.fp_p = 0;
3126 /* The general case: fold the comparison code to the types of compares
3127 that we have, choosing the branch as necessary. */
3130 case EQ: case LE: case LT: case LEU: case LTU:
3132 /* We have these compares: */
3133 cmp_code = code, branch_code = NE;
3138 /* These must be reversed. */
3139 cmp_code = reverse_condition (code), branch_code = EQ;
3142 case GE: case GT: case GEU: case GTU:
3143 /* For FP, we swap them, for INT, we reverse them. */
3144 if (alpha_compare.fp_p)
3146 cmp_code = swap_condition (code);
3148 tem = op0, op0 = op1, op1 = tem;
3152 cmp_code = reverse_condition (code);
3161 if (alpha_compare.fp_p)
3164 if (flag_unsafe_math_optimizations)
3166 /* When we are not as concerned about non-finite values, and we
3167 are comparing against zero, we can branch directly. */
3168 if (op1 == CONST0_RTX (DFmode))
3169 cmp_code = NIL, branch_code = code;
3170 else if (op0 == CONST0_RTX (DFmode))
3172 /* Undo the swap we probably did just above. */
3173 tem = op0, op0 = op1, op1 = tem;
3174 branch_code = swap_condition (cmp_code);
3180 /* ??? We mark the branch mode to be CCmode to prevent the
3181 compare and branch from being combined, since the compare
3182 insn follows IEEE rules that the branch does not. */
3183 branch_mode = CCmode;
3190 /* The following optimizations are only for signed compares. */
3191 if (code != LEU && code != LTU && code != GEU && code != GTU)
3193 /* Whee. Compare and branch against 0 directly. */
3194 if (op1 == const0_rtx)
3195 cmp_code = NIL, branch_code = code;
3197 /* If the constants doesn't fit into an immediate, but can
3198 be generated by lda/ldah, we adjust the argument and
3199 compare against zero, so we can use beq/bne directly. */
3200 /* ??? Don't do this when comparing against symbols, otherwise
3201 we'll reduce (&x == 0x1234) to (&x-0x1234 == 0), which will
3202 be declared false out of hand (at least for non-weak). */
3203 else if (GET_CODE (op1) == CONST_INT
3204 && (code == EQ || code == NE)
3205 && !(symbolic_operand (op0, VOIDmode)
3206 || (GET_CODE (op0) == REG && REG_POINTER (op0))))
3208 HOST_WIDE_INT v = INTVAL (op1), n = -v;
3210 if (! CONST_OK_FOR_LETTER_P (v, 'I')
3211 && (CONST_OK_FOR_LETTER_P (n, 'K')
3212 || CONST_OK_FOR_LETTER_P (n, 'L')))
3214 cmp_code = PLUS, branch_code = code;
3220 if (!reg_or_0_operand (op0, DImode))
3221 op0 = force_reg (DImode, op0);
3222 if (cmp_code != PLUS && !reg_or_8bit_operand (op1, DImode))
3223 op1 = force_reg (DImode, op1);
3226 /* Emit an initial compare instruction, if necessary. */
3228 if (cmp_code != NIL)
3230 tem = gen_reg_rtx (cmp_mode);
3231 emit_move_insn (tem, gen_rtx_fmt_ee (cmp_code, cmp_mode, op0, op1));
3234 /* Zero the operands. */
3235 memset (&alpha_compare, 0, sizeof (alpha_compare));
3237 /* Return the branch comparison. */
3238 return gen_rtx_fmt_ee (branch_code, branch_mode, tem, CONST0_RTX (cmp_mode));
3241 /* Certain simplifications can be done to make invalid setcc operations
3242 valid. Return the final comparison, or NULL if we can't work. */
3245 alpha_emit_setcc (enum rtx_code code)
3247 enum rtx_code cmp_code;
3248 rtx op0 = alpha_compare.op0, op1 = alpha_compare.op1;
3249 int fp_p = alpha_compare.fp_p;
3252 /* Zero the operands. */
3253 memset (&alpha_compare, 0, sizeof (alpha_compare));
3255 if (fp_p && GET_MODE (op0) == TFmode)
3257 if (! TARGET_HAS_XFLOATING_LIBS)
3260 /* X_floating library comparison functions return
3264 Convert the compare against the raw return value. */
3266 if (code == UNORDERED || code == ORDERED)
3271 op0 = alpha_emit_xfloating_compare (cmp_code, op0, op1);
3275 if (code == UNORDERED)
3277 else if (code == ORDERED)
3283 if (fp_p && !TARGET_FIX)
3286 /* The general case: fold the comparison code to the types of compares
3287 that we have, choosing the branch as necessary. */
3292 case EQ: case LE: case LT: case LEU: case LTU:
3294 /* We have these compares. */
3296 cmp_code = code, code = NE;
3300 if (!fp_p && op1 == const0_rtx)
3305 cmp_code = reverse_condition (code);
3309 case GE: case GT: case GEU: case GTU:
3310 /* These normally need swapping, but for integer zero we have
3311 special patterns that recognize swapped operands. */
3312 if (!fp_p && op1 == const0_rtx)
3314 code = swap_condition (code);
3316 cmp_code = code, code = NE;
3317 tmp = op0, op0 = op1, op1 = tmp;
3326 if (!register_operand (op0, DImode))
3327 op0 = force_reg (DImode, op0);
3328 if (!reg_or_8bit_operand (op1, DImode))
3329 op1 = force_reg (DImode, op1);
3332 /* Emit an initial compare instruction, if necessary. */
3333 if (cmp_code != NIL)
3335 enum machine_mode mode = fp_p ? DFmode : DImode;
3337 tmp = gen_reg_rtx (mode);
3338 emit_insn (gen_rtx_SET (VOIDmode, tmp,
3339 gen_rtx_fmt_ee (cmp_code, mode, op0, op1)));
3341 op0 = fp_p ? gen_lowpart (DImode, tmp) : tmp;
3345 /* Return the setcc comparison. */
3346 return gen_rtx_fmt_ee (code, DImode, op0, op1);
3350 /* Rewrite a comparison against zero CMP of the form
3351 (CODE (cc0) (const_int 0)) so it can be written validly in
3352 a conditional move (if_then_else CMP ...).
3353 If both of the operands that set cc0 are nonzero we must emit
3354 an insn to perform the compare (it can't be done within
3355 the conditional move). */
3358 alpha_emit_conditional_move (rtx cmp, enum machine_mode mode)
3360 enum rtx_code code = GET_CODE (cmp);
3361 enum rtx_code cmov_code = NE;
3362 rtx op0 = alpha_compare.op0;
3363 rtx op1 = alpha_compare.op1;
3364 int fp_p = alpha_compare.fp_p;
3365 enum machine_mode cmp_mode
3366 = (GET_MODE (op0) == VOIDmode ? DImode : GET_MODE (op0));
3367 enum machine_mode cmp_op_mode = fp_p ? DFmode : DImode;
3368 enum machine_mode cmov_mode = VOIDmode;
3369 int local_fast_math = flag_unsafe_math_optimizations;
3372 /* Zero the operands. */
3373 memset (&alpha_compare, 0, sizeof (alpha_compare));
3375 if (fp_p != FLOAT_MODE_P (mode))
3377 enum rtx_code cmp_code;
3382 /* If we have fp<->int register move instructions, do a cmov by
3383 performing the comparison in fp registers, and move the
3384 zero/nonzero value to integer registers, where we can then
3385 use a normal cmov, or vice-versa. */
3389 case EQ: case LE: case LT: case LEU: case LTU:
3390 /* We have these compares. */
3391 cmp_code = code, code = NE;
3395 /* This must be reversed. */
3396 cmp_code = EQ, code = EQ;
3399 case GE: case GT: case GEU: case GTU:
3400 /* These normally need swapping, but for integer zero we have
3401 special patterns that recognize swapped operands. */
3402 if (!fp_p && op1 == const0_rtx)
3403 cmp_code = code, code = NE;
3406 cmp_code = swap_condition (code);
3408 tem = op0, op0 = op1, op1 = tem;
3416 tem = gen_reg_rtx (cmp_op_mode);
3417 emit_insn (gen_rtx_SET (VOIDmode, tem,
3418 gen_rtx_fmt_ee (cmp_code, cmp_op_mode,
3421 cmp_mode = cmp_op_mode = fp_p ? DImode : DFmode;
3422 op0 = gen_lowpart (cmp_op_mode, tem);
3423 op1 = CONST0_RTX (cmp_op_mode);
3425 local_fast_math = 1;
3428 /* We may be able to use a conditional move directly.
3429 This avoids emitting spurious compares. */
3430 if (signed_comparison_operator (cmp, VOIDmode)
3431 && (!fp_p || local_fast_math)
3432 && (op0 == CONST0_RTX (cmp_mode) || op1 == CONST0_RTX (cmp_mode)))
3433 return gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
3435 /* We can't put the comparison inside the conditional move;
3436 emit a compare instruction and put that inside the
3437 conditional move. Make sure we emit only comparisons we have;
3438 swap or reverse as necessary. */
3445 case EQ: case LE: case LT: case LEU: case LTU:
3446 /* We have these compares: */
3450 /* This must be reversed. */
3451 code = reverse_condition (code);
3455 case GE: case GT: case GEU: case GTU:
3456 /* These must be swapped. */
3457 if (op1 != CONST0_RTX (cmp_mode))
3459 code = swap_condition (code);
3460 tem = op0, op0 = op1, op1 = tem;
3470 if (!reg_or_0_operand (op0, DImode))
3471 op0 = force_reg (DImode, op0);
3472 if (!reg_or_8bit_operand (op1, DImode))
3473 op1 = force_reg (DImode, op1);
3476 /* ??? We mark the branch mode to be CCmode to prevent the compare
3477 and cmov from being combined, since the compare insn follows IEEE
3478 rules that the cmov does not. */
3479 if (fp_p && !local_fast_math)
3482 tem = gen_reg_rtx (cmp_op_mode);
3483 emit_move_insn (tem, gen_rtx_fmt_ee (code, cmp_op_mode, op0, op1));
3484 return gen_rtx_fmt_ee (cmov_code, cmov_mode, tem, CONST0_RTX (cmp_op_mode));
3487 /* Simplify a conditional move of two constants into a setcc with
3488 arithmetic. This is done with a splitter since combine would
3489 just undo the work if done during code generation. It also catches
3490 cases we wouldn't have before cse. */
3493 alpha_split_conditional_move (enum rtx_code code, rtx dest, rtx cond,
3494 rtx t_rtx, rtx f_rtx)
3496 HOST_WIDE_INT t, f, diff;
3497 enum machine_mode mode;
3498 rtx target, subtarget, tmp;
3500 mode = GET_MODE (dest);
3505 if (((code == NE || code == EQ) && diff < 0)
3506 || (code == GE || code == GT))
3508 code = reverse_condition (code);
3509 diff = t, t = f, f = diff;
3513 subtarget = target = dest;
3516 target = gen_lowpart (DImode, dest);
3517 if (! no_new_pseudos)
3518 subtarget = gen_reg_rtx (DImode);
3522 /* Below, we must be careful to use copy_rtx on target and subtarget
3523 in intermediate insns, as they may be a subreg rtx, which may not
3526 if (f == 0 && exact_log2 (diff) > 0
3527 /* On EV6, we've got enough shifters to make non-arithmetic shifts
3528 viable over a longer latency cmove. On EV5, the E0 slot is a
3529 scarce resource, and on EV4 shift has the same latency as a cmove. */
3530 && (diff <= 8 || alpha_cpu == PROCESSOR_EV6))
3532 tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
3533 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
3535 tmp = gen_rtx_ASHIFT (DImode, copy_rtx (subtarget),
3536 GEN_INT (exact_log2 (t)));
3537 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
3539 else if (f == 0 && t == -1)
3541 tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
3542 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
3544 emit_insn (gen_negdi2 (target, copy_rtx (subtarget)));
3546 else if (diff == 1 || diff == 4 || diff == 8)
3550 tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
3551 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
3554 emit_insn (gen_adddi3 (target, copy_rtx (subtarget), GEN_INT (f)));
3557 add_op = GEN_INT (f);
3558 if (sext_add_operand (add_op, mode))
3560 tmp = gen_rtx_MULT (DImode, copy_rtx (subtarget),
3562 tmp = gen_rtx_PLUS (DImode, tmp, add_op);
3563 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
3575 /* Look up the function X_floating library function name for the
3579 alpha_lookup_xfloating_lib_func (enum rtx_code code)
3583 const enum rtx_code code;
3584 const char *const func;
3587 static const struct xfloating_op vms_xfloating_ops[] =
3589 { PLUS, "OTS$ADD_X" },
3590 { MINUS, "OTS$SUB_X" },
3591 { MULT, "OTS$MUL_X" },
3592 { DIV, "OTS$DIV_X" },
3593 { EQ, "OTS$EQL_X" },
3594 { NE, "OTS$NEQ_X" },
3595 { LT, "OTS$LSS_X" },
3596 { LE, "OTS$LEQ_X" },
3597 { GT, "OTS$GTR_X" },
3598 { GE, "OTS$GEQ_X" },
3599 { FIX, "OTS$CVTXQ" },
3600 { FLOAT, "OTS$CVTQX" },
3601 { UNSIGNED_FLOAT, "OTS$CVTQUX" },
3602 { FLOAT_EXTEND, "OTS$CVT_FLOAT_T_X" },
3603 { FLOAT_TRUNCATE, "OTS$CVT_FLOAT_X_T" },
3606 static const struct xfloating_op osf_xfloating_ops[] =
3608 { PLUS, "_OtsAddX" },
3609 { MINUS, "_OtsSubX" },
3610 { MULT, "_OtsMulX" },
3611 { DIV, "_OtsDivX" },
3618 { FIX, "_OtsCvtXQ" },
3619 { FLOAT, "_OtsCvtQX" },
3620 { UNSIGNED_FLOAT, "_OtsCvtQUX" },
3621 { FLOAT_EXTEND, "_OtsConvertFloatTX" },
3622 { FLOAT_TRUNCATE, "_OtsConvertFloatXT" },
3625 const struct xfloating_op *ops;
3626 const long n = ARRAY_SIZE (osf_xfloating_ops);
3629 /* How irritating. Nothing to key off for the table. Hardcode
3630 knowledge of the G_floating routines. */
3631 if (TARGET_FLOAT_VAX)
3633 if (TARGET_ABI_OPEN_VMS)
3635 if (code == FLOAT_EXTEND)
3636 return "OTS$CVT_FLOAT_G_X";
3637 if (code == FLOAT_TRUNCATE)
3638 return "OTS$CVT_FLOAT_X_G";
3642 if (code == FLOAT_EXTEND)
3643 return "_OtsConvertFloatGX";
3644 if (code == FLOAT_TRUNCATE)
3645 return "_OtsConvertFloatXG";
3649 if (TARGET_ABI_OPEN_VMS)
3650 ops = vms_xfloating_ops;
3652 ops = osf_xfloating_ops;
3654 for (i = 0; i < n; ++i)
3655 if (ops[i].code == code)
3661 /* Most X_floating operations take the rounding mode as an argument.
3662 Compute that here. */
3665 alpha_compute_xfloating_mode_arg (enum rtx_code code,
3666 enum alpha_fp_rounding_mode round)
3672 case ALPHA_FPRM_NORM:
3675 case ALPHA_FPRM_MINF:
3678 case ALPHA_FPRM_CHOP:
3681 case ALPHA_FPRM_DYN:
3687 /* XXX For reference, round to +inf is mode = 3. */
3690 if (code == FLOAT_TRUNCATE && alpha_fptm == ALPHA_FPTM_N)
3696 /* Emit an X_floating library function call.
3698 Note that these functions do not follow normal calling conventions:
3699 TFmode arguments are passed in two integer registers (as opposed to
3700 indirect); TFmode return values appear in R16+R17.
3702 FUNC is the function name to call.
3703 TARGET is where the output belongs.
3704 OPERANDS are the inputs.
3705 NOPERANDS is the count of inputs.
3706 EQUIV is the expression equivalent for the function.
3710 alpha_emit_xfloating_libcall (const char *func, rtx target, rtx operands[],
3711 int noperands, rtx equiv)
3713 rtx usage = NULL_RTX, tmp, reg;
3718 for (i = 0; i < noperands; ++i)
3720 switch (GET_MODE (operands[i]))
3723 reg = gen_rtx_REG (TFmode, regno);
3728 reg = gen_rtx_REG (DFmode, regno + 32);
3733 if (GET_CODE (operands[i]) != CONST_INT)
3737 reg = gen_rtx_REG (DImode, regno);
3745 emit_move_insn (reg, operands[i]);
3746 usage = alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode, reg), usage);
3749 switch (GET_MODE (target))
3752 reg = gen_rtx_REG (TFmode, 16);
3755 reg = gen_rtx_REG (DFmode, 32);
3758 reg = gen_rtx_REG (DImode, 0);
3764 tmp = gen_rtx_MEM (QImode, init_one_libfunc (func));
3765 tmp = emit_call_insn (GEN_CALL_VALUE (reg, tmp, const0_rtx,
3766 const0_rtx, const0_rtx));
3767 CALL_INSN_FUNCTION_USAGE (tmp) = usage;
3772 emit_libcall_block (tmp, target, reg, equiv);
3775 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
3778 alpha_emit_xfloating_arith (enum rtx_code code, rtx operands[])
3782 rtx out_operands[3];
3784 func = alpha_lookup_xfloating_lib_func (code);
3785 mode = alpha_compute_xfloating_mode_arg (code, alpha_fprm);
3787 out_operands[0] = operands[1];
3788 out_operands[1] = operands[2];
3789 out_operands[2] = GEN_INT (mode);
3790 alpha_emit_xfloating_libcall (func, operands[0], out_operands, 3,
3791 gen_rtx_fmt_ee (code, TFmode, operands[1],
3795 /* Emit an X_floating library function call for a comparison. */
3798 alpha_emit_xfloating_compare (enum rtx_code code, rtx op0, rtx op1)
3801 rtx out, operands[2];
3803 func = alpha_lookup_xfloating_lib_func (code);
3807 out = gen_reg_rtx (DImode);
3809 /* ??? Strange mode for equiv because what's actually returned
3810 is -1,0,1, not a proper boolean value. */
3811 alpha_emit_xfloating_libcall (func, out, operands, 2,
3812 gen_rtx_fmt_ee (code, CCmode, op0, op1));
3817 /* Emit an X_floating library function call for a conversion. */
3820 alpha_emit_xfloating_cvt (enum rtx_code orig_code, rtx operands[])
3822 int noperands = 1, mode;
3823 rtx out_operands[2];
3825 enum rtx_code code = orig_code;
3827 if (code == UNSIGNED_FIX)
3830 func = alpha_lookup_xfloating_lib_func (code);
3832 out_operands[0] = operands[1];
3837 mode = alpha_compute_xfloating_mode_arg (code, ALPHA_FPRM_CHOP);
3838 out_operands[1] = GEN_INT (mode);
3841 case FLOAT_TRUNCATE:
3842 mode = alpha_compute_xfloating_mode_arg (code, alpha_fprm);
3843 out_operands[1] = GEN_INT (mode);
3850 alpha_emit_xfloating_libcall (func, operands[0], out_operands, noperands,
3851 gen_rtx_fmt_e (orig_code,
3852 GET_MODE (operands[0]),
3856 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
3857 OP[0] into OP[0,1]. Naturally, output operand ordering is
3861 alpha_split_tfmode_pair (rtx operands[4])
3863 if (GET_CODE (operands[1]) == REG)
3865 operands[3] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1);
3866 operands[2] = gen_rtx_REG (DImode, REGNO (operands[1]));
3868 else if (GET_CODE (operands[1]) == MEM)
3870 operands[3] = adjust_address (operands[1], DImode, 8);
3871 operands[2] = adjust_address (operands[1], DImode, 0);
3873 else if (operands[1] == CONST0_RTX (TFmode))
3874 operands[2] = operands[3] = const0_rtx;
3878 if (GET_CODE (operands[0]) == REG)
3880 operands[1] = gen_rtx_REG (DImode, REGNO (operands[0]) + 1);
3881 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
3883 else if (GET_CODE (operands[0]) == MEM)
3885 operands[1] = adjust_address (operands[0], DImode, 8);
3886 operands[0] = adjust_address (operands[0], DImode, 0);
3892 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
3893 op2 is a register containing the sign bit, operation is the
3894 logical operation to be performed. */
3897 alpha_split_tfmode_frobsign (rtx operands[3], rtx (*operation) (rtx, rtx, rtx))
3899 rtx high_bit = operands[2];
3903 alpha_split_tfmode_pair (operands);
3905 /* Detect three flavors of operand overlap. */
3907 if (rtx_equal_p (operands[0], operands[2]))
3909 else if (rtx_equal_p (operands[1], operands[2]))
3911 if (rtx_equal_p (operands[0], high_bit))
3918 emit_move_insn (operands[0], operands[2]);
3920 /* ??? If the destination overlaps both source tf and high_bit, then
3921 assume source tf is dead in its entirety and use the other half
3922 for a scratch register. Otherwise "scratch" is just the proper
3923 destination register. */
3924 scratch = operands[move < 2 ? 1 : 3];
3926 emit_insn ((*operation) (scratch, high_bit, operands[3]));
3930 emit_move_insn (operands[0], operands[2]);
3932 emit_move_insn (operands[1], scratch);
3936 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
3940 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
3941 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
3942 lda r3,X(r11) lda r3,X+2(r11)
3943 extwl r1,r3,r1 extql r1,r3,r1
3944 extwh r2,r3,r2 extqh r2,r3,r2
3945 or r1.r2.r1 or r1,r2,r1
3948 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
3949 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
3950 lda r3,X(r11) lda r3,X(r11)
3951 extll r1,r3,r1 extll r1,r3,r1
3952 extlh r2,r3,r2 extlh r2,r3,r2
3953 or r1.r2.r1 addl r1,r2,r1
3955 quad: ldq_u r1,X(r11)
3964 alpha_expand_unaligned_load (rtx tgt, rtx mem, HOST_WIDE_INT size,
3965 HOST_WIDE_INT ofs, int sign)
3967 rtx meml, memh, addr, extl, exth, tmp, mema;
3968 enum machine_mode mode;
3970 meml = gen_reg_rtx (DImode);
3971 memh = gen_reg_rtx (DImode);
3972 addr = gen_reg_rtx (DImode);
3973 extl = gen_reg_rtx (DImode);
3974 exth = gen_reg_rtx (DImode);
3976 mema = XEXP (mem, 0);
3977 if (GET_CODE (mema) == LO_SUM)
3978 mema = force_reg (Pmode, mema);
3980 /* AND addresses cannot be in any alias set, since they may implicitly
3981 alias surrounding code. Ideally we'd have some alias set that
3982 covered all types except those with alignment 8 or higher. */
3984 tmp = change_address (mem, DImode,
3985 gen_rtx_AND (DImode,
3986 plus_constant (mema, ofs),
3988 set_mem_alias_set (tmp, 0);
3989 emit_move_insn (meml, tmp);
3991 tmp = change_address (mem, DImode,
3992 gen_rtx_AND (DImode,
3993 plus_constant (mema, ofs + size - 1),
3995 set_mem_alias_set (tmp, 0);
3996 emit_move_insn (memh, tmp);
3998 if (WORDS_BIG_ENDIAN && sign && (size == 2 || size == 4))
4000 emit_move_insn (addr, plus_constant (mema, -1));
4002 emit_insn (gen_extqh_be (extl, meml, addr));
4003 emit_insn (gen_extxl_be (exth, memh, GEN_INT (64), addr));
4005 addr = expand_binop (DImode, ior_optab, extl, exth, tgt, 1, OPTAB_WIDEN);
4006 addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (64 - size*8),
4007 addr, 1, OPTAB_WIDEN);
4009 else if (sign && size == 2)
4011 emit_move_insn (addr, plus_constant (mema, ofs+2));
4013 emit_insn (gen_extxl_le (extl, meml, GEN_INT (64), addr));
4014 emit_insn (gen_extqh_le (exth, memh, addr));
4016 /* We must use tgt here for the target. Alpha-vms port fails if we use
4017 addr for the target, because addr is marked as a pointer and combine
4018 knows that pointers are always sign-extended 32 bit values. */
4019 addr = expand_binop (DImode, ior_optab, extl, exth, tgt, 1, OPTAB_WIDEN);
4020 addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (48),
4021 addr, 1, OPTAB_WIDEN);
4025 if (WORDS_BIG_ENDIAN)
4027 emit_move_insn (addr, plus_constant (mema, ofs+size-1));
4031 emit_insn (gen_extwh_be (extl, meml, addr));
4036 emit_insn (gen_extlh_be (extl, meml, addr));
4041 emit_insn (gen_extqh_be (extl, meml, addr));
4048 emit_insn (gen_extxl_be (exth, memh, GEN_INT (size*8), addr));
4052 emit_move_insn (addr, plus_constant (mema, ofs));
4053 emit_insn (gen_extxl_le (extl, meml, GEN_INT (size*8), addr));
4057 emit_insn (gen_extwh_le (exth, memh, addr));
4062 emit_insn (gen_extlh_le (exth, memh, addr));
4067 emit_insn (gen_extqh_le (exth, memh, addr));
4076 addr = expand_binop (mode, ior_optab, gen_lowpart (mode, extl),
4077 gen_lowpart (mode, exth), gen_lowpart (mode, tgt),
4082 emit_move_insn (tgt, gen_lowpart(GET_MODE (tgt), addr));
4085 /* Similarly, use ins and msk instructions to perform unaligned stores. */
4088 alpha_expand_unaligned_store (rtx dst, rtx src,
4089 HOST_WIDE_INT size, HOST_WIDE_INT ofs)
4091 rtx dstl, dsth, addr, insl, insh, meml, memh, dsta;
4093 dstl = gen_reg_rtx (DImode);
4094 dsth = gen_reg_rtx (DImode);
4095 insl = gen_reg_rtx (DImode);
4096 insh = gen_reg_rtx (DImode);
4098 dsta = XEXP (dst, 0);
4099 if (GET_CODE (dsta) == LO_SUM)
4100 dsta = force_reg (Pmode, dsta);
4102 /* AND addresses cannot be in any alias set, since they may implicitly
4103 alias surrounding code. Ideally we'd have some alias set that
4104 covered all types except those with alignment 8 or higher. */
4106 meml = change_address (dst, DImode,
4107 gen_rtx_AND (DImode,
4108 plus_constant (dsta, ofs),
4110 set_mem_alias_set (meml, 0);
4112 memh = change_address (dst, DImode,
4113 gen_rtx_AND (DImode,
4114 plus_constant (dsta, ofs + size - 1),
4116 set_mem_alias_set (memh, 0);
4118 emit_move_insn (dsth, memh);
4119 emit_move_insn (dstl, meml);
4120 if (WORDS_BIG_ENDIAN)
4122 addr = copy_addr_to_reg (plus_constant (dsta, ofs+size-1));
4124 if (src != const0_rtx)
4129 emit_insn (gen_inswl_be (insh, gen_lowpart (HImode,src), addr));
4132 emit_insn (gen_insll_be (insh, gen_lowpart (SImode,src), addr));
4135 emit_insn (gen_insql_be (insh, gen_lowpart (DImode,src), addr));
4138 emit_insn (gen_insxh (insl, gen_lowpart (DImode, src),
4139 GEN_INT (size*8), addr));
4145 emit_insn (gen_mskxl_be (dsth, dsth, GEN_INT (0xffff), addr));
4149 rtx msk = immed_double_const (0xffffffff, 0, DImode);
4150 emit_insn (gen_mskxl_be (dsth, dsth, msk, addr));
4154 emit_insn (gen_mskxl_be (dsth, dsth, constm1_rtx, addr));
4158 emit_insn (gen_mskxh (dstl, dstl, GEN_INT (size*8), addr));
4162 addr = copy_addr_to_reg (plus_constant (dsta, ofs));
4164 if (src != const0_rtx)
4166 emit_insn (gen_insxh (insh, gen_lowpart (DImode, src),
4167 GEN_INT (size*8), addr));
4172 emit_insn (gen_inswl_le (insl, gen_lowpart (HImode, src), addr));
4175 emit_insn (gen_insll_le (insl, gen_lowpart (SImode, src), addr));
4178 emit_insn (gen_insql_le (insl, src, addr));
4183 emit_insn (gen_mskxh (dsth, dsth, GEN_INT (size*8), addr));
4188 emit_insn (gen_mskxl_le (dstl, dstl, GEN_INT (0xffff), addr));
4192 rtx msk = immed_double_const (0xffffffff, 0, DImode);
4193 emit_insn (gen_mskxl_le (dstl, dstl, msk, addr));
4197 emit_insn (gen_mskxl_le (dstl, dstl, constm1_rtx, addr));
4202 if (src != const0_rtx)
4204 dsth = expand_binop (DImode, ior_optab, insh, dsth, dsth, 0, OPTAB_WIDEN);
4205 dstl = expand_binop (DImode, ior_optab, insl, dstl, dstl, 0, OPTAB_WIDEN);
4208 if (WORDS_BIG_ENDIAN)
4210 emit_move_insn (meml, dstl);
4211 emit_move_insn (memh, dsth);
4215 /* Must store high before low for degenerate case of aligned. */
4216 emit_move_insn (memh, dsth);
4217 emit_move_insn (meml, dstl);
4221 /* The block move code tries to maximize speed by separating loads and
4222 stores at the expense of register pressure: we load all of the data
4223 before we store it back out. There are two secondary effects worth
4224 mentioning, that this speeds copying to/from aligned and unaligned
4225 buffers, and that it makes the code significantly easier to write. */
4227 #define MAX_MOVE_WORDS 8
4229 /* Load an integral number of consecutive unaligned quadwords. */
4232 alpha_expand_unaligned_load_words (rtx *out_regs, rtx smem,
4233 HOST_WIDE_INT words, HOST_WIDE_INT ofs)
4235 rtx const im8 = GEN_INT (-8);
4236 rtx const i64 = GEN_INT (64);
4237 rtx ext_tmps[MAX_MOVE_WORDS], data_regs[MAX_MOVE_WORDS+1];
4238 rtx sreg, areg, tmp, smema;
4241 smema = XEXP (smem, 0);
4242 if (GET_CODE (smema) == LO_SUM)
4243 smema = force_reg (Pmode, smema);
4245 /* Generate all the tmp registers we need. */
4246 for (i = 0; i < words; ++i)
4248 data_regs[i] = out_regs[i];
4249 ext_tmps[i] = gen_reg_rtx (DImode);
4251 data_regs[words] = gen_reg_rtx (DImode);
4254 smem = adjust_address (smem, GET_MODE (smem), ofs);
4256 /* Load up all of the source data. */
4257 for (i = 0; i < words; ++i)
4259 tmp = change_address (smem, DImode,
4260 gen_rtx_AND (DImode,
4261 plus_constant (smema, 8*i),
4263 set_mem_alias_set (tmp, 0);
4264 emit_move_insn (data_regs[i], tmp);
4267 tmp = change_address (smem, DImode,
4268 gen_rtx_AND (DImode,
4269 plus_constant (smema, 8*words - 1),
4271 set_mem_alias_set (tmp, 0);
4272 emit_move_insn (data_regs[words], tmp);
4274 /* Extract the half-word fragments. Unfortunately DEC decided to make
4275 extxh with offset zero a noop instead of zeroing the register, so
4276 we must take care of that edge condition ourselves with cmov. */
4278 sreg = copy_addr_to_reg (smema);
4279 areg = expand_binop (DImode, and_optab, sreg, GEN_INT (7), NULL,
4281 if (WORDS_BIG_ENDIAN)
4282 emit_move_insn (sreg, plus_constant (sreg, 7));
4283 for (i = 0; i < words; ++i)
4285 if (WORDS_BIG_ENDIAN)
4287 emit_insn (gen_extqh_be (data_regs[i], data_regs[i], sreg));
4288 emit_insn (gen_extxl_be (ext_tmps[i], data_regs[i+1], i64, sreg));
4292 emit_insn (gen_extxl_le (data_regs[i], data_regs[i], i64, sreg));
4293 emit_insn (gen_extqh_le (ext_tmps[i], data_regs[i+1], sreg));
4295 emit_insn (gen_rtx_SET (VOIDmode, ext_tmps[i],
4296 gen_rtx_IF_THEN_ELSE (DImode,
4297 gen_rtx_EQ (DImode, areg,
4299 const0_rtx, ext_tmps[i])));
4302 /* Merge the half-words into whole words. */
4303 for (i = 0; i < words; ++i)
4305 out_regs[i] = expand_binop (DImode, ior_optab, data_regs[i],
4306 ext_tmps[i], data_regs[i], 1, OPTAB_WIDEN);
4310 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
4311 may be NULL to store zeros. */
4314 alpha_expand_unaligned_store_words (rtx *data_regs, rtx dmem,
4315 HOST_WIDE_INT words, HOST_WIDE_INT ofs)
4317 rtx const im8 = GEN_INT (-8);
4318 rtx const i64 = GEN_INT (64);
4319 rtx ins_tmps[MAX_MOVE_WORDS];
4320 rtx st_tmp_1, st_tmp_2, dreg;
4321 rtx st_addr_1, st_addr_2, dmema;
4324 dmema = XEXP (dmem, 0);
4325 if (GET_CODE (dmema) == LO_SUM)
4326 dmema = force_reg (Pmode, dmema);
4328 /* Generate all the tmp registers we need. */
4329 if (data_regs != NULL)
4330 for (i = 0; i < words; ++i)
4331 ins_tmps[i] = gen_reg_rtx(DImode);
4332 st_tmp_1 = gen_reg_rtx(DImode);
4333 st_tmp_2 = gen_reg_rtx(DImode);
4336 dmem = adjust_address (dmem, GET_MODE (dmem), ofs);
4338 st_addr_2 = change_address (dmem, DImode,
4339 gen_rtx_AND (DImode,
4340 plus_constant (dmema, words*8 - 1),
4342 set_mem_alias_set (st_addr_2, 0);
4344 st_addr_1 = change_address (dmem, DImode,
4345 gen_rtx_AND (DImode, dmema, im8));
4346 set_mem_alias_set (st_addr_1, 0);
4348 /* Load up the destination end bits. */
4349 emit_move_insn (st_tmp_2, st_addr_2);
4350 emit_move_insn (st_tmp_1, st_addr_1);
4352 /* Shift the input data into place. */
4353 dreg = copy_addr_to_reg (dmema);
4354 if (WORDS_BIG_ENDIAN)
4355 emit_move_insn (dreg, plus_constant (dreg, 7));
4356 if (data_regs != NULL)
4358 for (i = words-1; i >= 0; --i)
4360 if (WORDS_BIG_ENDIAN)
4362 emit_insn (gen_insql_be (ins_tmps[i], data_regs[i], dreg));
4363 emit_insn (gen_insxh (data_regs[i], data_regs[i], i64, dreg));
4367 emit_insn (gen_insxh (ins_tmps[i], data_regs[i], i64, dreg));
4368 emit_insn (gen_insql_le (data_regs[i], data_regs[i], dreg));
4371 for (i = words-1; i > 0; --i)
4373 ins_tmps[i-1] = expand_binop (DImode, ior_optab, data_regs[i],
4374 ins_tmps[i-1], ins_tmps[i-1], 1,
4379 /* Split and merge the ends with the destination data. */
4380 if (WORDS_BIG_ENDIAN)
4382 emit_insn (gen_mskxl_be (st_tmp_2, st_tmp_2, constm1_rtx, dreg));
4383 emit_insn (gen_mskxh (st_tmp_1, st_tmp_1, i64, dreg));
4387 emit_insn (gen_mskxh (st_tmp_2, st_tmp_2, i64, dreg));
4388 emit_insn (gen_mskxl_le (st_tmp_1, st_tmp_1, constm1_rtx, dreg));
4391 if (data_regs != NULL)
4393 st_tmp_2 = expand_binop (DImode, ior_optab, st_tmp_2, ins_tmps[words-1],
4394 st_tmp_2, 1, OPTAB_WIDEN);
4395 st_tmp_1 = expand_binop (DImode, ior_optab, st_tmp_1, data_regs[0],
4396 st_tmp_1, 1, OPTAB_WIDEN);
4400 if (WORDS_BIG_ENDIAN)
4401 emit_move_insn (st_addr_1, st_tmp_1);
4403 emit_move_insn (st_addr_2, st_tmp_2);
4404 for (i = words-1; i > 0; --i)
4406 rtx tmp = change_address (dmem, DImode,
4407 gen_rtx_AND (DImode,
4408 plus_constant(dmema,
4409 WORDS_BIG_ENDIAN ? i*8-1 : i*8),
4411 set_mem_alias_set (tmp, 0);
4412 emit_move_insn (tmp, data_regs ? ins_tmps[i-1] : const0_rtx);
4414 if (WORDS_BIG_ENDIAN)
4415 emit_move_insn (st_addr_2, st_tmp_2);
4417 emit_move_insn (st_addr_1, st_tmp_1);
4421 /* Expand string/block move operations.
4423 operands[0] is the pointer to the destination.
4424 operands[1] is the pointer to the source.
4425 operands[2] is the number of bytes to move.
4426 operands[3] is the alignment. */
4429 alpha_expand_block_move (rtx operands[])
4431 rtx bytes_rtx = operands[2];
4432 rtx align_rtx = operands[3];
4433 HOST_WIDE_INT orig_bytes = INTVAL (bytes_rtx);
4434 HOST_WIDE_INT bytes = orig_bytes;
4435 HOST_WIDE_INT src_align = INTVAL (align_rtx) * BITS_PER_UNIT;
4436 HOST_WIDE_INT dst_align = src_align;
4437 rtx orig_src = operands[1];
4438 rtx orig_dst = operands[0];
4439 rtx data_regs[2 * MAX_MOVE_WORDS + 16];
4441 unsigned int i, words, ofs, nregs = 0;
4443 if (orig_bytes <= 0)
4445 else if (orig_bytes > MAX_MOVE_WORDS * UNITS_PER_WORD)
4448 /* Look for additional alignment information from recorded register info. */
4450 tmp = XEXP (orig_src, 0);
4451 if (GET_CODE (tmp) == REG)
4452 src_align = MAX (src_align, REGNO_POINTER_ALIGN (REGNO (tmp)));
4453 else if (GET_CODE (tmp) == PLUS
4454 && GET_CODE (XEXP (tmp, 0)) == REG
4455 && GET_CODE (XEXP (tmp, 1)) == CONST_INT)
4457 unsigned HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
4458 unsigned int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
4462 if (a >= 64 && c % 8 == 0)
4464 else if (a >= 32 && c % 4 == 0)
4466 else if (a >= 16 && c % 2 == 0)
4471 tmp = XEXP (orig_dst, 0);
4472 if (GET_CODE (tmp) == REG)
4473 dst_align = MAX (dst_align, REGNO_POINTER_ALIGN (REGNO (tmp)));
4474 else if (GET_CODE (tmp) == PLUS
4475 && GET_CODE (XEXP (tmp, 0)) == REG
4476 && GET_CODE (XEXP (tmp, 1)) == CONST_INT)
4478 unsigned HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
4479 unsigned int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
4483 if (a >= 64 && c % 8 == 0)
4485 else if (a >= 32 && c % 4 == 0)
4487 else if (a >= 16 && c % 2 == 0)
4492 /* Load the entire block into registers. */
4493 if (GET_CODE (XEXP (orig_src, 0)) == ADDRESSOF)
4495 enum machine_mode mode;
4497 tmp = XEXP (XEXP (orig_src, 0), 0);
4499 /* Don't use the existing register if we're reading more than
4500 is held in the register. Nor if there is not a mode that
4501 handles the exact size. */
4502 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 1);
4503 if (GET_CODE (tmp) == REG
4505 && GET_MODE_SIZE (GET_MODE (tmp)) >= bytes)
4509 data_regs[nregs] = gen_lowpart (DImode, tmp);
4510 data_regs[nregs + 1] = gen_highpart (DImode, tmp);
4514 data_regs[nregs++] = gen_lowpart (mode, tmp);
4519 /* No appropriate mode; fall back on memory. */
4520 orig_src = replace_equiv_address (orig_src,
4521 copy_addr_to_reg (XEXP (orig_src, 0)));
4522 src_align = GET_MODE_BITSIZE (GET_MODE (tmp));
4526 if (src_align >= 64 && bytes >= 8)
4530 for (i = 0; i < words; ++i)
4531 data_regs[nregs + i] = gen_reg_rtx (DImode);
4533 for (i = 0; i < words; ++i)
4534 emit_move_insn (data_regs[nregs + i],
4535 adjust_address (orig_src, DImode, ofs + i * 8));
4542 if (src_align >= 32 && bytes >= 4)
4546 for (i = 0; i < words; ++i)
4547 data_regs[nregs + i] = gen_reg_rtx (SImode);
4549 for (i = 0; i < words; ++i)
4550 emit_move_insn (data_regs[nregs + i],
4551 adjust_address (orig_src, SImode, ofs + i * 4));
4562 for (i = 0; i < words+1; ++i)
4563 data_regs[nregs + i] = gen_reg_rtx (DImode);
4565 alpha_expand_unaligned_load_words (data_regs + nregs, orig_src,
4573 if (! TARGET_BWX && bytes >= 4)
4575 data_regs[nregs++] = tmp = gen_reg_rtx (SImode);
4576 alpha_expand_unaligned_load (tmp, orig_src, 4, ofs, 0);
4583 if (src_align >= 16)
4586 data_regs[nregs++] = tmp = gen_reg_rtx (HImode);
4587 emit_move_insn (tmp, adjust_address (orig_src, HImode, ofs));
4590 } while (bytes >= 2);
4592 else if (! TARGET_BWX)
4594 data_regs[nregs++] = tmp = gen_reg_rtx (HImode);
4595 alpha_expand_unaligned_load (tmp, orig_src, 2, ofs, 0);
4603 data_regs[nregs++] = tmp = gen_reg_rtx (QImode);
4604 emit_move_insn (tmp, adjust_address (orig_src, QImode, ofs));
4611 if (nregs > ARRAY_SIZE (data_regs))
4614 /* Now save it back out again. */
4618 if (GET_CODE (XEXP (orig_dst, 0)) == ADDRESSOF)
4620 enum machine_mode mode;
4621 tmp = XEXP (XEXP (orig_dst, 0), 0);
4623 mode = mode_for_size (orig_bytes * BITS_PER_UNIT, MODE_INT, 1);
4624 if (GET_CODE (tmp) == REG && GET_MODE (tmp) == mode)
4628 emit_move_insn (tmp, data_regs[0]);
4633 else if (nregs == 2 && mode == TImode)
4635 /* Undo the subregging done above when copying between
4636 two TImode registers. */
4637 if (GET_CODE (data_regs[0]) == SUBREG
4638 && GET_MODE (SUBREG_REG (data_regs[0])) == TImode)
4639 emit_move_insn (tmp, SUBREG_REG (data_regs[0]));
4645 emit_move_insn (gen_lowpart (DImode, tmp), data_regs[0]);
4646 emit_move_insn (gen_highpart (DImode, tmp), data_regs[1]);
4650 emit_no_conflict_block (seq, tmp, data_regs[0],
4651 data_regs[1], NULL_RTX);
4659 /* ??? If nregs > 1, consider reconstructing the word in regs. */
4660 /* ??? Optimize mode < dst_mode with strict_low_part. */
4662 /* No appropriate mode; fall back on memory. We can speed things
4663 up by recognizing extra alignment information. */
4664 orig_dst = replace_equiv_address (orig_dst,
4665 copy_addr_to_reg (XEXP (orig_dst, 0)));
4666 dst_align = GET_MODE_BITSIZE (GET_MODE (tmp));
4669 /* Write out the data in whatever chunks reading the source allowed. */
4670 if (dst_align >= 64)
4672 while (i < nregs && GET_MODE (data_regs[i]) == DImode)
4674 emit_move_insn (adjust_address (orig_dst, DImode, ofs),
4681 if (dst_align >= 32)
4683 /* If the source has remaining DImode regs, write them out in
4685 while (i < nregs && GET_MODE (data_regs[i]) == DImode)
4687 tmp = expand_binop (DImode, lshr_optab, data_regs[i], GEN_INT (32),
4688 NULL_RTX, 1, OPTAB_WIDEN);
4690 emit_move_insn (adjust_address (orig_dst, SImode, ofs),
4691 gen_lowpart (SImode, data_regs[i]));
4692 emit_move_insn (adjust_address (orig_dst, SImode, ofs + 4),
4693 gen_lowpart (SImode, tmp));
4698 while (i < nregs && GET_MODE (data_regs[i]) == SImode)
4700 emit_move_insn (adjust_address (orig_dst, SImode, ofs),
4707 if (i < nregs && GET_MODE (data_regs[i]) == DImode)
4709 /* Write out a remaining block of words using unaligned methods. */
4711 for (words = 1; i + words < nregs; words++)
4712 if (GET_MODE (data_regs[i + words]) != DImode)
4716 alpha_expand_unaligned_store (orig_dst, data_regs[i], 8, ofs);
4718 alpha_expand_unaligned_store_words (data_regs + i, orig_dst,
4725 /* Due to the above, this won't be aligned. */
4726 /* ??? If we have more than one of these, consider constructing full
4727 words in registers and using alpha_expand_unaligned_store_words. */
4728 while (i < nregs && GET_MODE (data_regs[i]) == SImode)
4730 alpha_expand_unaligned_store (orig_dst, data_regs[i], 4, ofs);
4735 if (dst_align >= 16)
4736 while (i < nregs && GET_MODE (data_regs[i]) == HImode)
4738 emit_move_insn (adjust_address (orig_dst, HImode, ofs), data_regs[i]);
4743 while (i < nregs && GET_MODE (data_regs[i]) == HImode)
4745 alpha_expand_unaligned_store (orig_dst, data_regs[i], 2, ofs);
4750 while (i < nregs && GET_MODE (data_regs[i]) == QImode)
4752 emit_move_insn (adjust_address (orig_dst, QImode, ofs), data_regs[i]);
4766 alpha_expand_block_clear (rtx operands[])
4768 rtx bytes_rtx = operands[1];
4769 rtx align_rtx = operands[2];
4770 HOST_WIDE_INT orig_bytes = INTVAL (bytes_rtx);
4771 HOST_WIDE_INT bytes = orig_bytes;
4772 HOST_WIDE_INT align = INTVAL (align_rtx) * BITS_PER_UNIT;
4773 HOST_WIDE_INT alignofs = 0;
4774 rtx orig_dst = operands[0];
4776 int i, words, ofs = 0;
4778 if (orig_bytes <= 0)
4780 if (orig_bytes > MAX_MOVE_WORDS * UNITS_PER_WORD)
4783 /* Look for stricter alignment. */
4784 tmp = XEXP (orig_dst, 0);
4785 if (GET_CODE (tmp) == REG)
4786 align = MAX (align, REGNO_POINTER_ALIGN (REGNO (tmp)));
4787 else if (GET_CODE (tmp) == PLUS
4788 && GET_CODE (XEXP (tmp, 0)) == REG
4789 && GET_CODE (XEXP (tmp, 1)) == CONST_INT)
4791 HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
4792 int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
4797 align = a, alignofs = 8 - c % 8;
4799 align = a, alignofs = 4 - c % 4;
4801 align = a, alignofs = 2 - c % 2;
4804 else if (GET_CODE (tmp) == ADDRESSOF)
4806 enum machine_mode mode;
4808 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 1);
4809 if (GET_MODE (XEXP (tmp, 0)) == mode)
4811 emit_move_insn (XEXP (tmp, 0), const0_rtx);
4815 /* No appropriate mode; fall back on memory. */
4816 orig_dst = replace_equiv_address (orig_dst, copy_addr_to_reg (tmp));
4817 align = GET_MODE_BITSIZE (GET_MODE (XEXP (tmp, 0)));
4820 /* Handle an unaligned prefix first. */
4824 #if HOST_BITS_PER_WIDE_INT >= 64
4825 /* Given that alignofs is bounded by align, the only time BWX could
4826 generate three stores is for a 7 byte fill. Prefer two individual
4827 stores over a load/mask/store sequence. */
4828 if ((!TARGET_BWX || alignofs == 7)
4830 && !(alignofs == 4 && bytes >= 4))
4832 enum machine_mode mode = (align >= 64 ? DImode : SImode);
4833 int inv_alignofs = (align >= 64 ? 8 : 4) - alignofs;
4837 mem = adjust_address (orig_dst, mode, ofs - inv_alignofs);
4838 set_mem_alias_set (mem, 0);
4840 mask = ~(~(HOST_WIDE_INT)0 << (inv_alignofs * 8));
4841 if (bytes < alignofs)
4843 mask |= ~(HOST_WIDE_INT)0 << ((inv_alignofs + bytes) * 8);
4854 tmp = expand_binop (mode, and_optab, mem, GEN_INT (mask),
4855 NULL_RTX, 1, OPTAB_WIDEN);
4857 emit_move_insn (mem, tmp);
4861 if (TARGET_BWX && (alignofs & 1) && bytes >= 1)
4863 emit_move_insn (adjust_address (orig_dst, QImode, ofs), const0_rtx);
4868 if (TARGET_BWX && align >= 16 && (alignofs & 3) == 2 && bytes >= 2)
4870 emit_move_insn (adjust_address (orig_dst, HImode, ofs), const0_rtx);
4875 if (alignofs == 4 && bytes >= 4)
4877 emit_move_insn (adjust_address (orig_dst, SImode, ofs), const0_rtx);
4883 /* If we've not used the extra lead alignment information by now,
4884 we won't be able to. Downgrade align to match what's left over. */
4887 alignofs = alignofs & -alignofs;
4888 align = MIN (align, alignofs * BITS_PER_UNIT);
4892 /* Handle a block of contiguous long-words. */
4894 if (align >= 64 && bytes >= 8)
4898 for (i = 0; i < words; ++i)
4899 emit_move_insn (adjust_address (orig_dst, DImode, ofs + i * 8),
4906 /* If the block is large and appropriately aligned, emit a single
4907 store followed by a sequence of stq_u insns. */
4909 if (align >= 32 && bytes > 16)
4913 emit_move_insn (adjust_address (orig_dst, SImode, ofs), const0_rtx);
4917 orig_dsta = XEXP (orig_dst, 0);
4918 if (GET_CODE (orig_dsta) == LO_SUM)
4919 orig_dsta = force_reg (Pmode, orig_dsta);
4922 for (i = 0; i < words; ++i)
4925 = change_address (orig_dst, DImode,
4926 gen_rtx_AND (DImode,
4927 plus_constant (orig_dsta, ofs + i*8),
4929 set_mem_alias_set (mem, 0);
4930 emit_move_insn (mem, const0_rtx);
4933 /* Depending on the alignment, the first stq_u may have overlapped
4934 with the initial stl, which means that the last stq_u didn't
4935 write as much as it would appear. Leave those questionable bytes
4937 bytes -= words * 8 - 4;
4938 ofs += words * 8 - 4;
4941 /* Handle a smaller block of aligned words. */
4943 if ((align >= 64 && bytes == 4)
4944 || (align == 32 && bytes >= 4))
4948 for (i = 0; i < words; ++i)
4949 emit_move_insn (adjust_address (orig_dst, SImode, ofs + i * 4),
4956 /* An unaligned block uses stq_u stores for as many as possible. */
4962 alpha_expand_unaligned_store_words (NULL, orig_dst, words, ofs);
4968 /* Next clean up any trailing pieces. */
4970 #if HOST_BITS_PER_WIDE_INT >= 64
4971 /* Count the number of bits in BYTES for which aligned stores could
4974 for (i = (TARGET_BWX ? 1 : 4); i * BITS_PER_UNIT <= align ; i <<= 1)
4978 /* If we have appropriate alignment (and it wouldn't take too many
4979 instructions otherwise), mask out the bytes we need. */
4980 if (TARGET_BWX ? words > 2 : bytes > 0)
4987 mem = adjust_address (orig_dst, DImode, ofs);
4988 set_mem_alias_set (mem, 0);
4990 mask = ~(HOST_WIDE_INT)0 << (bytes * 8);
4992 tmp = expand_binop (DImode, and_optab, mem, GEN_INT (mask),
4993 NULL_RTX, 1, OPTAB_WIDEN);
4995 emit_move_insn (mem, tmp);
4998 else if (align >= 32 && bytes < 4)
5003 mem = adjust_address (orig_dst, SImode, ofs);
5004 set_mem_alias_set (mem, 0);
5006 mask = ~(HOST_WIDE_INT)0 << (bytes * 8);
5008 tmp = expand_binop (SImode, and_optab, mem, GEN_INT (mask),
5009 NULL_RTX, 1, OPTAB_WIDEN);
5011 emit_move_insn (mem, tmp);
5017 if (!TARGET_BWX && bytes >= 4)
5019 alpha_expand_unaligned_store (orig_dst, const0_rtx, 4, ofs);
5029 emit_move_insn (adjust_address (orig_dst, HImode, ofs),
5033 } while (bytes >= 2);
5035 else if (! TARGET_BWX)
5037 alpha_expand_unaligned_store (orig_dst, const0_rtx, 2, ofs);
5045 emit_move_insn (adjust_address (orig_dst, QImode, ofs), const0_rtx);
5053 /* Returns a mask so that zap(x, value) == x & mask. */
5056 alpha_expand_zap_mask (HOST_WIDE_INT value)
5061 if (HOST_BITS_PER_WIDE_INT >= 64)
5063 HOST_WIDE_INT mask = 0;
5065 for (i = 7; i >= 0; --i)
5068 if (!((value >> i) & 1))
5072 result = gen_int_mode (mask, DImode);
5074 else if (HOST_BITS_PER_WIDE_INT == 32)
5076 HOST_WIDE_INT mask_lo = 0, mask_hi = 0;
5078 for (i = 7; i >= 4; --i)
5081 if (!((value >> i) & 1))
5085 for (i = 3; i >= 0; --i)
5088 if (!((value >> i) & 1))
5092 result = immed_double_const (mask_lo, mask_hi, DImode);
5101 alpha_expand_builtin_vector_binop (rtx (*gen) (rtx, rtx, rtx),
5102 enum machine_mode mode,
5103 rtx op0, rtx op1, rtx op2)
5105 op0 = gen_lowpart (mode, op0);
5107 if (op1 == const0_rtx)
5108 op1 = CONST0_RTX (mode);
5110 op1 = gen_lowpart (mode, op1);
5112 if (op2 == const0_rtx)
5113 op2 = CONST0_RTX (mode);
5115 op2 = gen_lowpart (mode, op2);
5117 emit_insn ((*gen) (op0, op1, op2));
5120 /* Adjust the cost of a scheduling dependency. Return the new cost of
5121 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5124 alpha_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
5126 enum attr_type insn_type, dep_insn_type;
5128 /* If the dependence is an anti-dependence, there is no cost. For an
5129 output dependence, there is sometimes a cost, but it doesn't seem
5130 worth handling those few cases. */
5131 if (REG_NOTE_KIND (link) != 0)
5134 /* If we can't recognize the insns, we can't really do anything. */
5135 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
5138 insn_type = get_attr_type (insn);
5139 dep_insn_type = get_attr_type (dep_insn);
5141 /* Bring in the user-defined memory latency. */
5142 if (dep_insn_type == TYPE_ILD
5143 || dep_insn_type == TYPE_FLD
5144 || dep_insn_type == TYPE_LDSYM)
5145 cost += alpha_memory_latency-1;
5147 /* Everything else handled in DFA bypasses now. */
5152 /* The number of instructions that can be issued per cycle. */
5155 alpha_issue_rate (void)
5157 return (alpha_cpu == PROCESSOR_EV4 ? 2 : 4);
5161 alpha_use_dfa_pipeline_interface (void)
5166 /* How many alternative schedules to try. This should be as wide as the
5167 scheduling freedom in the DFA, but no wider. Making this value too
5168 large results extra work for the scheduler.
5170 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
5171 alternative schedules. For EV5, we can choose between E0/E1 and
5172 FA/FM. For EV6, an arithmetic insn can be issued to U0/U1/L0/L1. */
5175 alpha_multipass_dfa_lookahead (void)
5177 return (alpha_cpu == PROCESSOR_EV6 ? 4 : 2);
5180 /* Machine-specific function data. */
5182 struct machine_function GTY(())
5185 /* List of call information words for calls from this function. */
5186 struct rtx_def *first_ciw;
5187 struct rtx_def *last_ciw;
5190 /* List of deferred case vectors. */
5191 struct rtx_def *addr_list;
5194 const char *some_ld_name;
5197 /* How to allocate a 'struct machine_function'. */
5199 static struct machine_function *
5200 alpha_init_machine_status (void)
5202 return ((struct machine_function *)
5203 ggc_alloc_cleared (sizeof (struct machine_function)));
5206 /* Functions to save and restore alpha_return_addr_rtx. */
5208 /* Start the ball rolling with RETURN_ADDR_RTX. */
5211 alpha_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
5216 return get_hard_reg_initial_val (Pmode, REG_RA);
5219 /* Return or create a pseudo containing the gp value for the current
5220 function. Needed only if TARGET_LD_BUGGY_LDGP. */
5223 alpha_gp_save_rtx (void)
5225 rtx r = get_hard_reg_initial_val (DImode, 29);
5226 if (GET_CODE (r) != MEM)
5227 r = gen_mem_addressof (r, NULL_TREE, /*rescan=*/true);
5232 alpha_ra_ever_killed (void)
5236 if (!has_hard_reg_initial_val (Pmode, REG_RA))
5237 return regs_ever_live[REG_RA];
5239 push_topmost_sequence ();
5241 pop_topmost_sequence ();
5243 return reg_set_between_p (gen_rtx_REG (Pmode, REG_RA), top, NULL_RTX);
5247 /* Return the trap mode suffix applicable to the current
5248 instruction, or NULL. */
5251 get_trap_mode_suffix (void)
5253 enum attr_trap_suffix s = get_attr_trap_suffix (current_output_insn);
5257 case TRAP_SUFFIX_NONE:
5260 case TRAP_SUFFIX_SU:
5261 if (alpha_fptm >= ALPHA_FPTM_SU)
5265 case TRAP_SUFFIX_SUI:
5266 if (alpha_fptm >= ALPHA_FPTM_SUI)
5270 case TRAP_SUFFIX_V_SV:
5278 case ALPHA_FPTM_SUI:
5283 case TRAP_SUFFIX_V_SV_SVI:
5292 case ALPHA_FPTM_SUI:
5297 case TRAP_SUFFIX_U_SU_SUI:
5306 case ALPHA_FPTM_SUI:
5314 /* Return the rounding mode suffix applicable to the current
5315 instruction, or NULL. */
5318 get_round_mode_suffix (void)
5320 enum attr_round_suffix s = get_attr_round_suffix (current_output_insn);
5324 case ROUND_SUFFIX_NONE:
5326 case ROUND_SUFFIX_NORMAL:
5329 case ALPHA_FPRM_NORM:
5331 case ALPHA_FPRM_MINF:
5333 case ALPHA_FPRM_CHOP:
5335 case ALPHA_FPRM_DYN:
5340 case ROUND_SUFFIX_C:
5346 /* Locate some local-dynamic symbol still in use by this function
5347 so that we can print its name in some movdi_er_tlsldm pattern. */
5350 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
5354 if (GET_CODE (x) == SYMBOL_REF
5355 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
5357 cfun->machine->some_ld_name = XSTR (x, 0);
5365 get_some_local_dynamic_name (void)
5369 if (cfun->machine->some_ld_name)
5370 return cfun->machine->some_ld_name;
5372 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
5374 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
5375 return cfun->machine->some_ld_name;
5380 /* Print an operand. Recognize special options, documented below. */
5383 print_operand (FILE *file, rtx x, int code)
5390 /* Print the assembler name of the current function. */
5391 assemble_name (file, alpha_fnname);
5395 assemble_name (file, get_some_local_dynamic_name ());
5400 const char *trap = get_trap_mode_suffix ();
5401 const char *round = get_round_mode_suffix ();
5404 fprintf (file, (TARGET_AS_SLASH_BEFORE_SUFFIX ? "/%s%s" : "%s%s"),
5405 (trap ? trap : ""), (round ? round : ""));
5410 /* Generates single precision instruction suffix. */
5411 fputc ((TARGET_FLOAT_VAX ? 'f' : 's'), file);
5415 /* Generates double precision instruction suffix. */
5416 fputc ((TARGET_FLOAT_VAX ? 'g' : 't'), file);
5420 /* Generates a nop after a noreturn call at the very end of the
5422 if (next_real_insn (current_output_insn) == 0)
5423 fprintf (file, "\n\tnop");
5427 if (alpha_this_literal_sequence_number == 0)
5428 alpha_this_literal_sequence_number = alpha_next_sequence_number++;
5429 fprintf (file, "%d", alpha_this_literal_sequence_number);
5433 if (alpha_this_gpdisp_sequence_number == 0)
5434 alpha_this_gpdisp_sequence_number = alpha_next_sequence_number++;
5435 fprintf (file, "%d", alpha_this_gpdisp_sequence_number);
5439 if (GET_CODE (x) == HIGH)
5440 output_addr_const (file, XEXP (x, 0));
5442 output_operand_lossage ("invalid %%H value");
5449 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD_CALL)
5451 x = XVECEXP (x, 0, 0);
5452 lituse = "lituse_tlsgd";
5454 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM_CALL)
5456 x = XVECEXP (x, 0, 0);
5457 lituse = "lituse_tlsldm";
5459 else if (GET_CODE (x) == CONST_INT)
5460 lituse = "lituse_jsr";
5463 output_operand_lossage ("invalid %%J value");
5467 if (x != const0_rtx)
5468 fprintf (file, "\t\t!%s!%d", lituse, (int) INTVAL (x));
5476 #ifdef HAVE_AS_JSRDIRECT_RELOCS
5477 lituse = "lituse_jsrdirect";
5479 lituse = "lituse_jsr";
5482 if (INTVAL (x) == 0)
5484 fprintf (file, "\t\t!%s!%d", lituse, (int) INTVAL (x));
5488 /* If this operand is the constant zero, write it as "$31". */
5489 if (GET_CODE (x) == REG)
5490 fprintf (file, "%s", reg_names[REGNO (x)]);
5491 else if (x == CONST0_RTX (GET_MODE (x)))
5492 fprintf (file, "$31");
5494 output_operand_lossage ("invalid %%r value");
5498 /* Similar, but for floating-point. */
5499 if (GET_CODE (x) == REG)
5500 fprintf (file, "%s", reg_names[REGNO (x)]);
5501 else if (x == CONST0_RTX (GET_MODE (x)))
5502 fprintf (file, "$f31");
5504 output_operand_lossage ("invalid %%R value");
5508 /* Write the 1's complement of a constant. */
5509 if (GET_CODE (x) != CONST_INT)
5510 output_operand_lossage ("invalid %%N value");
5512 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x));
5516 /* Write 1 << C, for a constant C. */
5517 if (GET_CODE (x) != CONST_INT)
5518 output_operand_lossage ("invalid %%P value");
5520 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT) 1 << INTVAL (x));
5524 /* Write the high-order 16 bits of a constant, sign-extended. */
5525 if (GET_CODE (x) != CONST_INT)
5526 output_operand_lossage ("invalid %%h value");
5528 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) >> 16);
5532 /* Write the low-order 16 bits of a constant, sign-extended. */
5533 if (GET_CODE (x) != CONST_INT)
5534 output_operand_lossage ("invalid %%L value");
5536 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5537 (INTVAL (x) & 0xffff) - 2 * (INTVAL (x) & 0x8000));
5541 /* Write mask for ZAP insn. */
5542 if (GET_CODE (x) == CONST_DOUBLE)
5544 HOST_WIDE_INT mask = 0;
5545 HOST_WIDE_INT value;
5547 value = CONST_DOUBLE_LOW (x);
5548 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
5553 value = CONST_DOUBLE_HIGH (x);
5554 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
5557 mask |= (1 << (i + sizeof (int)));
5559 fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask & 0xff);
5562 else if (GET_CODE (x) == CONST_INT)
5564 HOST_WIDE_INT mask = 0, value = INTVAL (x);
5566 for (i = 0; i < 8; i++, value >>= 8)
5570 fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask);
5573 output_operand_lossage ("invalid %%m value");
5577 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5578 if (GET_CODE (x) != CONST_INT
5579 || (INTVAL (x) != 8 && INTVAL (x) != 16
5580 && INTVAL (x) != 32 && INTVAL (x) != 64))
5581 output_operand_lossage ("invalid %%M value");
5583 fprintf (file, "%s",
5584 (INTVAL (x) == 8 ? "b"
5585 : INTVAL (x) == 16 ? "w"
5586 : INTVAL (x) == 32 ? "l"
5591 /* Similar, except do it from the mask. */
5592 if (GET_CODE (x) == CONST_INT)
5594 HOST_WIDE_INT value = INTVAL (x);
5601 if (value == 0xffff)
5606 if (value == 0xffffffff)
5617 else if (HOST_BITS_PER_WIDE_INT == 32
5618 && GET_CODE (x) == CONST_DOUBLE
5619 && CONST_DOUBLE_LOW (x) == 0xffffffff
5620 && CONST_DOUBLE_HIGH (x) == 0)
5625 output_operand_lossage ("invalid %%U value");
5629 /* Write the constant value divided by 8 for little-endian mode or
5630 (56 - value) / 8 for big-endian mode. */
5632 if (GET_CODE (x) != CONST_INT
5633 || (unsigned HOST_WIDE_INT) INTVAL (x) >= (WORDS_BIG_ENDIAN
5636 || (INTVAL (x) & 7) != 0)
5637 output_operand_lossage ("invalid %%s value");
5639 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5641 ? (56 - INTVAL (x)) / 8
5646 /* Same, except compute (64 - c) / 8 */
5648 if (GET_CODE (x) != CONST_INT
5649 && (unsigned HOST_WIDE_INT) INTVAL (x) >= 64
5650 && (INTVAL (x) & 7) != 8)
5651 output_operand_lossage ("invalid %%s value");
5653 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (64 - INTVAL (x)) / 8);
5658 /* On Unicos/Mk systems: use a DEX expression if the symbol
5659 clashes with a register name. */
5660 int dex = unicosmk_need_dex (x);
5662 fprintf (file, "DEX(%d)", dex);
5664 output_addr_const (file, x);
5668 case 'C': case 'D': case 'c': case 'd':
5669 /* Write out comparison name. */
5671 enum rtx_code c = GET_CODE (x);
5673 if (GET_RTX_CLASS (c) != '<')
5674 output_operand_lossage ("invalid %%C value");
5676 else if (code == 'D')
5677 c = reverse_condition (c);
5678 else if (code == 'c')
5679 c = swap_condition (c);
5680 else if (code == 'd')
5681 c = swap_condition (reverse_condition (c));
5684 fprintf (file, "ule");
5686 fprintf (file, "ult");
5687 else if (c == UNORDERED)
5688 fprintf (file, "un");
5690 fprintf (file, "%s", GET_RTX_NAME (c));
5695 /* Write the divide or modulus operator. */
5696 switch (GET_CODE (x))
5699 fprintf (file, "div%s", GET_MODE (x) == SImode ? "l" : "q");
5702 fprintf (file, "div%su", GET_MODE (x) == SImode ? "l" : "q");
5705 fprintf (file, "rem%s", GET_MODE (x) == SImode ? "l" : "q");
5708 fprintf (file, "rem%su", GET_MODE (x) == SImode ? "l" : "q");
5711 output_operand_lossage ("invalid %%E value");
5717 /* Write "_u" for unaligned access. */
5718 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == AND)
5719 fprintf (file, "_u");
5723 if (GET_CODE (x) == REG)
5724 fprintf (file, "%s", reg_names[REGNO (x)]);
5725 else if (GET_CODE (x) == MEM)
5726 output_address (XEXP (x, 0));
5727 else if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == UNSPEC)
5729 switch (XINT (XEXP (x, 0), 1))
5733 output_addr_const (file, XVECEXP (XEXP (x, 0), 0, 0));
5736 output_operand_lossage ("unknown relocation unspec");
5741 output_addr_const (file, x);
5745 output_operand_lossage ("invalid %%xn code");
5750 print_operand_address (FILE *file, rtx addr)
5753 HOST_WIDE_INT offset = 0;
5755 if (GET_CODE (addr) == AND)
5756 addr = XEXP (addr, 0);
5758 if (GET_CODE (addr) == PLUS
5759 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
5761 offset = INTVAL (XEXP (addr, 1));
5762 addr = XEXP (addr, 0);
5765 if (GET_CODE (addr) == LO_SUM)
5767 const char *reloc16, *reloclo;
5768 rtx op1 = XEXP (addr, 1);
5770 if (GET_CODE (op1) == CONST && GET_CODE (XEXP (op1, 0)) == UNSPEC)
5772 op1 = XEXP (op1, 0);
5773 switch (XINT (op1, 1))
5777 reloclo = (alpha_tls_size == 16 ? "dtprel" : "dtprello");
5781 reloclo = (alpha_tls_size == 16 ? "tprel" : "tprello");
5784 output_operand_lossage ("unknown relocation unspec");
5788 output_addr_const (file, XVECEXP (op1, 0, 0));
5793 reloclo = "gprellow";
5794 output_addr_const (file, op1);
5798 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
5800 addr = XEXP (addr, 0);
5801 if (GET_CODE (addr) == REG)
5802 basereg = REGNO (addr);
5803 else if (GET_CODE (addr) == SUBREG
5804 && GET_CODE (SUBREG_REG (addr)) == REG)
5805 basereg = subreg_regno (addr);
5809 fprintf (file, "($%d)\t\t!%s", basereg,
5810 (basereg == 29 ? reloc16 : reloclo));
5814 if (GET_CODE (addr) == REG)
5815 basereg = REGNO (addr);
5816 else if (GET_CODE (addr) == SUBREG
5817 && GET_CODE (SUBREG_REG (addr)) == REG)
5818 basereg = subreg_regno (addr);
5819 else if (GET_CODE (addr) == CONST_INT)
5820 offset = INTVAL (addr);
5822 #if TARGET_ABI_OPEN_VMS
5823 else if (GET_CODE (addr) == SYMBOL_REF)
5825 fprintf (file, "%s", XSTR (addr, 0));
5828 else if (GET_CODE (addr) == CONST
5829 && GET_CODE (XEXP (addr, 0)) == PLUS
5830 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF)
5832 fprintf (file, "%s+" HOST_WIDE_INT_PRINT_DEC,
5833 XSTR (XEXP (XEXP (addr, 0), 0), 0),
5834 INTVAL (XEXP (XEXP (addr, 0), 1)));
5842 fprintf (file, HOST_WIDE_INT_PRINT_DEC "($%d)", offset, basereg);
5845 /* Emit RTL insns to initialize the variable parts of a trampoline at
5846 TRAMP. FNADDR is an RTX for the address of the function's pure
5847 code. CXT is an RTX for the static chain value for the function.
5849 The three offset parameters are for the individual template's
5850 layout. A JMPOFS < 0 indicates that the trampoline does not
5851 contain instructions at all.
5853 We assume here that a function will be called many more times than
5854 its address is taken (e.g., it might be passed to qsort), so we
5855 take the trouble to initialize the "hint" field in the JMP insn.
5856 Note that the hint field is PC (new) + 4 * bits 13:0. */
5859 alpha_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt,
5860 int fnofs, int cxtofs, int jmpofs)
5862 rtx temp, temp1, addr;
5863 /* VMS really uses DImode pointers in memory at this point. */
5864 enum machine_mode mode = TARGET_ABI_OPEN_VMS ? Pmode : ptr_mode;
5866 #ifdef POINTERS_EXTEND_UNSIGNED
5867 fnaddr = convert_memory_address (mode, fnaddr);
5868 cxt = convert_memory_address (mode, cxt);
5871 /* Store function address and CXT. */
5872 addr = memory_address (mode, plus_constant (tramp, fnofs));
5873 emit_move_insn (gen_rtx_MEM (mode, addr), fnaddr);
5874 addr = memory_address (mode, plus_constant (tramp, cxtofs));
5875 emit_move_insn (gen_rtx_MEM (mode, addr), cxt);
5877 /* This has been disabled since the hint only has a 32k range, and in
5878 no existing OS is the stack within 32k of the text segment. */
5879 if (0 && jmpofs >= 0)
5881 /* Compute hint value. */
5882 temp = force_operand (plus_constant (tramp, jmpofs+4), NULL_RTX);
5883 temp = expand_binop (DImode, sub_optab, fnaddr, temp, temp, 1,
5885 temp = expand_shift (RSHIFT_EXPR, Pmode, temp,
5886 build_int_2 (2, 0), NULL_RTX, 1);
5887 temp = expand_and (SImode, gen_lowpart (SImode, temp),
5888 GEN_INT (0x3fff), 0);
5890 /* Merge in the hint. */
5891 addr = memory_address (SImode, plus_constant (tramp, jmpofs));
5892 temp1 = force_reg (SImode, gen_rtx_MEM (SImode, addr));
5893 temp1 = expand_and (SImode, temp1, GEN_INT (0xffffc000), NULL_RTX);
5894 temp1 = expand_binop (SImode, ior_optab, temp1, temp, temp1, 1,
5896 emit_move_insn (gen_rtx_MEM (SImode, addr), temp1);
5899 #ifdef ENABLE_EXECUTE_STACK
5900 emit_library_call (init_one_libfunc ("__enable_execute_stack"),
5901 0, VOIDmode, 1, tramp, Pmode);
5905 emit_insn (gen_imb ());
5908 /* Determine where to put an argument to a function.
5909 Value is zero to push the argument on the stack,
5910 or a hard register in which to store the argument.
5912 MODE is the argument's machine mode.
5913 TYPE is the data type of the argument (as a tree).
5914 This is null for libcalls where that information may
5916 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5917 the preceding args and about the function being called.
5918 NAMED is nonzero if this argument is a named parameter
5919 (otherwise it is an extra parameter matching an ellipsis).
5921 On Alpha the first 6 words of args are normally in registers
5922 and the rest are pushed. */
5925 function_arg (CUMULATIVE_ARGS cum, enum machine_mode mode, tree type,
5926 int named ATTRIBUTE_UNUSED)
5931 /* Don't get confused and pass small structures in FP registers. */
5932 if (type && AGGREGATE_TYPE_P (type))
5936 #ifdef ENABLE_CHECKING
5937 /* With alpha_split_complex_arg, we shouldn't see any raw complex
5939 if (COMPLEX_MODE_P (mode))
5943 /* Set up defaults for FP operands passed in FP registers, and
5944 integral operands passed in integer registers. */
5945 if (TARGET_FPREGS && GET_MODE_CLASS (mode) == MODE_FLOAT)
5951 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
5952 the three platforms, so we can't avoid conditional compilation. */
5953 #if TARGET_ABI_OPEN_VMS
5955 if (mode == VOIDmode)
5956 return alpha_arg_info_reg_val (cum);
5958 num_args = cum.num_args;
5959 if (num_args >= 6 || MUST_PASS_IN_STACK (mode, type))
5962 #elif TARGET_ABI_UNICOSMK
5966 /* If this is the last argument, generate the call info word (CIW). */
5967 /* ??? We don't include the caller's line number in the CIW because
5968 I don't know how to determine it if debug infos are turned off. */
5969 if (mode == VOIDmode)
5978 for (i = 0; i < cum.num_reg_words && i < 5; i++)
5979 if (cum.reg_args_type[i])
5980 lo |= (1 << (7 - i));
5982 if (cum.num_reg_words == 6 && cum.reg_args_type[5])
5985 lo |= cum.num_reg_words;
5987 #if HOST_BITS_PER_WIDE_INT == 32
5988 hi = (cum.num_args << 20) | cum.num_arg_words;
5990 lo = lo | ((HOST_WIDE_INT) cum.num_args << 52)
5991 | ((HOST_WIDE_INT) cum.num_arg_words << 32);
5994 ciw = immed_double_const (lo, hi, DImode);
5996 return gen_rtx_UNSPEC (DImode, gen_rtvec (1, ciw),
5997 UNSPEC_UMK_LOAD_CIW);
6000 size = ALPHA_ARG_SIZE (mode, type, named);
6001 num_args = cum.num_reg_words;
6002 if (MUST_PASS_IN_STACK (mode, type)
6003 || cum.num_reg_words + size > 6 || cum.force_stack)
6005 else if (type && TYPE_MODE (type) == BLKmode)
6009 reg1 = gen_rtx_REG (DImode, num_args + 16);
6010 reg1 = gen_rtx_EXPR_LIST (DImode, reg1, const0_rtx);
6012 /* The argument fits in two registers. Note that we still need to
6013 reserve a register for empty structures. */
6017 return gen_rtx_PARALLEL (mode, gen_rtvec (1, reg1));
6020 reg2 = gen_rtx_REG (DImode, num_args + 17);
6021 reg2 = gen_rtx_EXPR_LIST (DImode, reg2, GEN_INT (8));
6022 return gen_rtx_PARALLEL (mode, gen_rtvec (2, reg1, reg2));
6026 #elif TARGET_ABI_OSF
6032 /* VOID is passed as a special flag for "last argument". */
6033 if (type == void_type_node)
6035 else if (MUST_PASS_IN_STACK (mode, type))
6037 else if (FUNCTION_ARG_PASS_BY_REFERENCE (cum, mode, type, named))
6041 #error Unhandled ABI
6044 return gen_rtx_REG (mode, num_args + basereg);
6047 /* Return true if TYPE must be returned in memory, instead of in registers. */
6050 alpha_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
6052 enum machine_mode mode = VOIDmode;
6057 mode = TYPE_MODE (type);
6059 /* All aggregates are returned in memory. */
6060 if (AGGREGATE_TYPE_P (type))
6064 size = GET_MODE_SIZE (mode);
6065 switch (GET_MODE_CLASS (mode))
6067 case MODE_VECTOR_FLOAT:
6068 /* Pass all float vectors in memory, like an aggregate. */
6071 case MODE_COMPLEX_FLOAT:
6072 /* We judge complex floats on the size of their element,
6073 not the size of the whole type. */
6074 size = GET_MODE_UNIT_SIZE (mode);
6079 case MODE_COMPLEX_INT:
6080 case MODE_VECTOR_INT:
6084 /* ??? We get called on all sorts of random stuff from
6085 aggregate_value_p. We can't abort, but it's not clear
6086 what's safe to return. Pretend it's a struct I guess. */
6090 /* Otherwise types must fit in one register. */
6091 return size > UNITS_PER_WORD;
6094 /* Define how to find the value returned by a function. VALTYPE is the
6095 data type of the value (as a tree). If the precise function being
6096 called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0.
6097 MODE is set instead of VALTYPE for libcalls.
6099 On Alpha the value is found in $0 for integer functions and
6100 $f0 for floating-point functions. */
6103 function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
6104 enum machine_mode mode)
6106 unsigned int regnum;
6107 enum mode_class class;
6109 #ifdef ENABLE_CHECKING
6110 if (valtype && alpha_return_in_memory (valtype, func))
6115 mode = TYPE_MODE (valtype);
6117 class = GET_MODE_CLASS (mode);
6121 /* Do the same thing as PROMOTE_MODE. */
6125 case MODE_COMPLEX_INT:
6126 case MODE_VECTOR_INT:
6134 case MODE_COMPLEX_FLOAT:
6136 enum machine_mode cmode = GET_MODE_INNER (mode);
6138 return gen_rtx_PARALLEL
6141 gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (cmode, 32),
6143 gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (cmode, 33),
6144 GEN_INT (GET_MODE_SIZE (cmode)))));
6151 return gen_rtx_REG (mode, regnum);
6154 /* TCmode complex values are passed by invisible reference. We
6155 should not split these values. */
6158 alpha_split_complex_arg (tree type)
6160 return TYPE_MODE (type) != TCmode;
6164 alpha_build_builtin_va_list (void)
6166 tree base, ofs, space, record, type_decl;
6168 if (TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK)
6169 return ptr_type_node;
6171 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6172 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6173 TREE_CHAIN (record) = type_decl;
6174 TYPE_NAME (record) = type_decl;
6176 /* C++? SET_IS_AGGR_TYPE (record, 1); */
6178 /* Dummy field to prevent alignment warnings. */
6179 space = build_decl (FIELD_DECL, NULL_TREE, integer_type_node);
6180 DECL_FIELD_CONTEXT (space) = record;
6181 DECL_ARTIFICIAL (space) = 1;
6182 DECL_IGNORED_P (space) = 1;
6184 ofs = build_decl (FIELD_DECL, get_identifier ("__offset"),
6186 DECL_FIELD_CONTEXT (ofs) = record;
6187 TREE_CHAIN (ofs) = space;
6189 base = build_decl (FIELD_DECL, get_identifier ("__base"),
6191 DECL_FIELD_CONTEXT (base) = record;
6192 TREE_CHAIN (base) = ofs;
6194 TYPE_FIELDS (record) = base;
6195 layout_type (record);
6200 /* Perform any needed actions needed for a function that is receiving a
6201 variable number of arguments. */
6204 alpha_setup_incoming_varargs (CUMULATIVE_ARGS *pcum,
6205 enum machine_mode mode ATTRIBUTE_UNUSED,
6206 tree type ATTRIBUTE_UNUSED,
6207 int *pretend_size, int no_rtl)
6209 #if TARGET_ABI_UNICOSMK
6210 /* On Unicos/Mk, the standard subroutine __T3E_MISMATCH stores all register
6211 arguments on the stack. Unfortunately, it doesn't always store the first
6212 one (i.e. the one that arrives in $16 or $f16). This is not a problem
6213 with stdargs as we always have at least one named argument there. */
6214 int num_reg_words = pcum->num_reg_words;
6215 if (num_reg_words < 6)
6219 emit_insn (gen_umk_mismatch_args (GEN_INT (num_reg_words + 1)));
6220 emit_insn (gen_arg_home_umk ());
6224 #elif TARGET_ABI_OPEN_VMS
6225 /* For VMS, we allocate space for all 6 arg registers plus a count.
6227 However, if NO registers need to be saved, don't allocate any space.
6228 This is not only because we won't need the space, but because AP
6229 includes the current_pretend_args_size and we don't want to mess up
6230 any ap-relative addresses already made. */
6231 if (pcum->num_args < 6)
6235 emit_move_insn (gen_rtx_REG (DImode, 1), virtual_incoming_args_rtx);
6236 emit_insn (gen_arg_home ());
6238 *pretend_size = 7 * UNITS_PER_WORD;
6241 /* On OSF/1 and friends, we allocate space for all 12 arg registers, but
6242 only push those that are remaining. However, if NO registers need to
6243 be saved, don't allocate any space. This is not only because we won't
6244 need the space, but because AP includes the current_pretend_args_size
6245 and we don't want to mess up any ap-relative addresses already made.
6247 If we are not to use the floating-point registers, save the integer
6248 registers where we would put the floating-point registers. This is
6249 not the most efficient way to implement varargs with just one register
6250 class, but it isn't worth doing anything more efficient in this rare
6252 CUMULATIVE_ARGS cum = *pcum;
6259 int set = get_varargs_alias_set ();
6262 tmp = gen_rtx_MEM (BLKmode,
6263 plus_constant (virtual_incoming_args_rtx,
6264 (cum + 6) * UNITS_PER_WORD));
6265 set_mem_alias_set (tmp, set);
6266 move_block_from_reg (16 + cum, tmp, 6 - cum);
6268 tmp = gen_rtx_MEM (BLKmode,
6269 plus_constant (virtual_incoming_args_rtx,
6270 cum * UNITS_PER_WORD));
6271 set_mem_alias_set (tmp, set);
6272 move_block_from_reg (16 + (TARGET_FPREGS ? 32 : 0) + cum, tmp,
6275 *pretend_size = 12 * UNITS_PER_WORD;
6280 alpha_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
6282 HOST_WIDE_INT offset;
6283 tree t, offset_field, base_field;
6285 if (TREE_CODE (TREE_TYPE (valist)) == ERROR_MARK)
6288 if (TARGET_ABI_UNICOSMK)
6289 std_expand_builtin_va_start (valist, nextarg);
6291 /* For Unix, SETUP_INCOMING_VARARGS moves the starting address base
6292 up by 48, storing fp arg registers in the first 48 bytes, and the
6293 integer arg registers in the next 48 bytes. This is only done,
6294 however, if any integer registers need to be stored.
6296 If no integer registers need be stored, then we must subtract 48
6297 in order to account for the integer arg registers which are counted
6298 in argsize above, but which are not actually stored on the stack.
6299 Must further be careful here about structures straddling the last
6300 integer argument register; that futzes with pretend_args_size,
6301 which changes the meaning of AP. */
6304 offset = TARGET_ABI_OPEN_VMS ? UNITS_PER_WORD : 6 * UNITS_PER_WORD;
6306 offset = -6 * UNITS_PER_WORD + current_function_pretend_args_size;
6308 if (TARGET_ABI_OPEN_VMS)
6310 nextarg = plus_constant (nextarg, offset);
6311 nextarg = plus_constant (nextarg, NUM_ARGS * UNITS_PER_WORD);
6312 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist,
6313 make_tree (ptr_type_node, nextarg));
6314 TREE_SIDE_EFFECTS (t) = 1;
6316 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6320 base_field = TYPE_FIELDS (TREE_TYPE (valist));
6321 offset_field = TREE_CHAIN (base_field);
6323 base_field = build (COMPONENT_REF, TREE_TYPE (base_field),
6324 valist, base_field);
6325 offset_field = build (COMPONENT_REF, TREE_TYPE (offset_field),
6326 valist, offset_field);
6328 t = make_tree (ptr_type_node, virtual_incoming_args_rtx);
6329 t = build (PLUS_EXPR, ptr_type_node, t, build_int_2 (offset, 0));
6330 t = build (MODIFY_EXPR, TREE_TYPE (base_field), base_field, t);
6331 TREE_SIDE_EFFECTS (t) = 1;
6332 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6334 t = build_int_2 (NUM_ARGS * UNITS_PER_WORD, 0);
6335 t = build (MODIFY_EXPR, TREE_TYPE (offset_field), offset_field, t);
6336 TREE_SIDE_EFFECTS (t) = 1;
6337 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6342 alpha_va_arg (tree valist, tree type)
6345 tree t, type_size, rounded_size;
6346 tree offset_field, base_field, addr_tree, addend;
6347 tree wide_type, wide_ofs;
6350 if (TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK)
6351 return std_expand_builtin_va_arg (valist, type);
6353 if (type == error_mark_node
6354 || (type_size = TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type))) == NULL
6355 || TREE_OVERFLOW (type_size))
6356 rounded_size = size_zero_node;
6358 rounded_size = fold (build (MULT_EXPR, sizetype,
6359 fold (build (TRUNC_DIV_EXPR, sizetype,
6360 fold (build (PLUS_EXPR, sizetype,
6366 base_field = TYPE_FIELDS (TREE_TYPE (valist));
6367 offset_field = TREE_CHAIN (base_field);
6369 base_field = build (COMPONENT_REF, TREE_TYPE (base_field),
6370 valist, base_field);
6371 offset_field = build (COMPONENT_REF, TREE_TYPE (offset_field),
6372 valist, offset_field);
6374 /* If the type could not be passed in registers, skip the block
6375 reserved for the registers. */
6376 if (MUST_PASS_IN_STACK (TYPE_MODE (type), type))
6378 t = build (MODIFY_EXPR, TREE_TYPE (offset_field), offset_field,
6379 build (MAX_EXPR, TREE_TYPE (offset_field),
6380 offset_field, build_int_2 (6*8, 0)));
6381 TREE_SIDE_EFFECTS (t) = 1;
6382 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6385 wide_type = make_signed_type (64);
6386 wide_ofs = save_expr (build1 (CONVERT_EXPR, wide_type, offset_field));
6390 if (TYPE_MODE (type) == TFmode || TYPE_MODE (type) == TCmode)
6393 rounded_size = size_int (UNITS_PER_WORD);
6395 else if (TREE_CODE (type) == COMPLEX_TYPE)
6397 rtx real_part, imag_part, value, tmp;
6399 real_part = alpha_va_arg (valist, TREE_TYPE (type));
6400 imag_part = alpha_va_arg (valist, TREE_TYPE (type));
6402 /* ??? Most irritatingly, we're not returning the value here,
6403 but the address. Since real_part and imag_part are not
6404 necessarily contiguous, we must copy to local storage. */
6406 real_part = gen_rtx_MEM (TYPE_MODE (TREE_TYPE (type)), real_part);
6407 imag_part = gen_rtx_MEM (TYPE_MODE (TREE_TYPE (type)), imag_part);
6408 value = gen_rtx_CONCAT (TYPE_MODE (type), real_part, imag_part);
6410 tmp = assign_temp (type, 0, 1, 0);
6411 emit_move_insn (tmp, value);
6413 return XEXP (tmp, 0);
6415 else if (TREE_CODE (type) == REAL_TYPE)
6417 tree fpaddend, cond;
6419 fpaddend = fold (build (PLUS_EXPR, TREE_TYPE (addend),
6420 addend, build_int_2 (-6*8, 0)));
6422 cond = fold (build (LT_EXPR, integer_type_node,
6423 wide_ofs, build_int_2 (6*8, 0)));
6425 addend = fold (build (COND_EXPR, TREE_TYPE (addend), cond,
6429 addr_tree = build (PLUS_EXPR, TREE_TYPE (base_field),
6430 base_field, addend);
6432 addr = expand_expr (addr_tree, NULL_RTX, Pmode, EXPAND_NORMAL);
6433 addr = copy_to_reg (addr);
6435 t = build (MODIFY_EXPR, TREE_TYPE (offset_field), offset_field,
6436 build (PLUS_EXPR, TREE_TYPE (offset_field),
6437 offset_field, rounded_size));
6438 TREE_SIDE_EFFECTS (t) = 1;
6439 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6443 addr = force_reg (Pmode, addr);
6444 addr = gen_rtx_MEM (Pmode, addr);
6454 ALPHA_BUILTIN_CMPBGE,
6455 ALPHA_BUILTIN_EXTBL,
6456 ALPHA_BUILTIN_EXTWL,
6457 ALPHA_BUILTIN_EXTLL,
6458 ALPHA_BUILTIN_EXTQL,
6459 ALPHA_BUILTIN_EXTWH,
6460 ALPHA_BUILTIN_EXTLH,
6461 ALPHA_BUILTIN_EXTQH,
6462 ALPHA_BUILTIN_INSBL,
6463 ALPHA_BUILTIN_INSWL,
6464 ALPHA_BUILTIN_INSLL,
6465 ALPHA_BUILTIN_INSQL,
6466 ALPHA_BUILTIN_INSWH,
6467 ALPHA_BUILTIN_INSLH,
6468 ALPHA_BUILTIN_INSQH,
6469 ALPHA_BUILTIN_MSKBL,
6470 ALPHA_BUILTIN_MSKWL,
6471 ALPHA_BUILTIN_MSKLL,
6472 ALPHA_BUILTIN_MSKQL,
6473 ALPHA_BUILTIN_MSKWH,
6474 ALPHA_BUILTIN_MSKLH,
6475 ALPHA_BUILTIN_MSKQH,
6476 ALPHA_BUILTIN_UMULH,
6478 ALPHA_BUILTIN_ZAPNOT,
6479 ALPHA_BUILTIN_AMASK,
6480 ALPHA_BUILTIN_IMPLVER,
6482 ALPHA_BUILTIN_THREAD_POINTER,
6483 ALPHA_BUILTIN_SET_THREAD_POINTER,
6486 ALPHA_BUILTIN_MINUB8,
6487 ALPHA_BUILTIN_MINSB8,
6488 ALPHA_BUILTIN_MINUW4,
6489 ALPHA_BUILTIN_MINSW4,
6490 ALPHA_BUILTIN_MAXUB8,
6491 ALPHA_BUILTIN_MAXSB8,
6492 ALPHA_BUILTIN_MAXUW4,
6493 ALPHA_BUILTIN_MAXSW4,
6497 ALPHA_BUILTIN_UNPKBL,
6498 ALPHA_BUILTIN_UNPKBW,
6503 ALPHA_BUILTIN_CTPOP,
6508 static unsigned int const code_for_builtin[ALPHA_BUILTIN_max] = {
6509 CODE_FOR_builtin_cmpbge,
6510 CODE_FOR_builtin_extbl,
6511 CODE_FOR_builtin_extwl,
6512 CODE_FOR_builtin_extll,
6513 CODE_FOR_builtin_extql,
6514 CODE_FOR_builtin_extwh,
6515 CODE_FOR_builtin_extlh,
6516 CODE_FOR_builtin_extqh,
6517 CODE_FOR_builtin_insbl,
6518 CODE_FOR_builtin_inswl,
6519 CODE_FOR_builtin_insll,
6520 CODE_FOR_builtin_insql,
6521 CODE_FOR_builtin_inswh,
6522 CODE_FOR_builtin_inslh,
6523 CODE_FOR_builtin_insqh,
6524 CODE_FOR_builtin_mskbl,
6525 CODE_FOR_builtin_mskwl,
6526 CODE_FOR_builtin_mskll,
6527 CODE_FOR_builtin_mskql,
6528 CODE_FOR_builtin_mskwh,
6529 CODE_FOR_builtin_msklh,
6530 CODE_FOR_builtin_mskqh,
6531 CODE_FOR_umuldi3_highpart,
6532 CODE_FOR_builtin_zap,
6533 CODE_FOR_builtin_zapnot,
6534 CODE_FOR_builtin_amask,
6535 CODE_FOR_builtin_implver,
6536 CODE_FOR_builtin_rpcc,
6541 CODE_FOR_builtin_minub8,
6542 CODE_FOR_builtin_minsb8,
6543 CODE_FOR_builtin_minuw4,
6544 CODE_FOR_builtin_minsw4,
6545 CODE_FOR_builtin_maxub8,
6546 CODE_FOR_builtin_maxsb8,
6547 CODE_FOR_builtin_maxuw4,
6548 CODE_FOR_builtin_maxsw4,
6549 CODE_FOR_builtin_perr,
6550 CODE_FOR_builtin_pklb,
6551 CODE_FOR_builtin_pkwb,
6552 CODE_FOR_builtin_unpkbl,
6553 CODE_FOR_builtin_unpkbw,
6556 CODE_FOR_builtin_cttz,
6557 CODE_FOR_builtin_ctlz,
6558 CODE_FOR_builtin_ctpop
6561 struct alpha_builtin_def
6564 enum alpha_builtin code;
6565 unsigned int target_mask;
6568 static struct alpha_builtin_def const zero_arg_builtins[] = {
6569 { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER, 0 },
6570 { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC, 0 }
6573 static struct alpha_builtin_def const one_arg_builtins[] = {
6574 { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK, 0 },
6575 { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB, MASK_MAX },
6576 { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB, MASK_MAX },
6577 { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL, MASK_MAX },
6578 { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW, MASK_MAX },
6579 { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ, MASK_CIX },
6580 { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ, MASK_CIX },
6581 { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP, MASK_CIX }
6584 static struct alpha_builtin_def const two_arg_builtins[] = {
6585 { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE, 0 },
6586 { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL, 0 },
6587 { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL, 0 },
6588 { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL, 0 },
6589 { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL, 0 },
6590 { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH, 0 },
6591 { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH, 0 },
6592 { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH, 0 },
6593 { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL, 0 },
6594 { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL, 0 },
6595 { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL, 0 },
6596 { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL, 0 },
6597 { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH, 0 },
6598 { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH, 0 },
6599 { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH, 0 },
6600 { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL, 0 },
6601 { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL, 0 },
6602 { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL, 0 },
6603 { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL, 0 },
6604 { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH, 0 },
6605 { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH, 0 },
6606 { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH, 0 },
6607 { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH, 0 },
6608 { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP, 0 },
6609 { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT, 0 },
6610 { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8, MASK_MAX },
6611 { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8, MASK_MAX },
6612 { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4, MASK_MAX },
6613 { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4, MASK_MAX },
6614 { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8, MASK_MAX },
6615 { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8, MASK_MAX },
6616 { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4, MASK_MAX },
6617 { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4, MASK_MAX },
6618 { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR, MASK_MAX }
6622 alpha_init_builtins (void)
6624 const struct alpha_builtin_def *p;
6628 ftype = build_function_type (long_integer_type_node, void_list_node);
6630 p = zero_arg_builtins;
6631 for (i = 0; i < ARRAY_SIZE (zero_arg_builtins); ++i, ++p)
6632 if ((target_flags & p->target_mask) == p->target_mask)
6633 builtin_function (p->name, ftype, p->code, BUILT_IN_MD,
6636 ftype = build_function_type_list (long_integer_type_node,
6637 long_integer_type_node, NULL_TREE);
6639 p = one_arg_builtins;
6640 for (i = 0; i < ARRAY_SIZE (one_arg_builtins); ++i, ++p)
6641 if ((target_flags & p->target_mask) == p->target_mask)
6642 builtin_function (p->name, ftype, p->code, BUILT_IN_MD,
6645 ftype = build_function_type_list (long_integer_type_node,
6646 long_integer_type_node,
6647 long_integer_type_node, NULL_TREE);
6649 p = two_arg_builtins;
6650 for (i = 0; i < ARRAY_SIZE (two_arg_builtins); ++i, ++p)
6651 if ((target_flags & p->target_mask) == p->target_mask)
6652 builtin_function (p->name, ftype, p->code, BUILT_IN_MD,
6655 ftype = build_function_type (ptr_type_node, void_list_node);
6656 builtin_function ("__builtin_thread_pointer", ftype,
6657 ALPHA_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
6660 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
6661 builtin_function ("__builtin_set_thread_pointer", ftype,
6662 ALPHA_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
6666 /* Expand an expression EXP that calls a built-in function,
6667 with result going to TARGET if that's convenient
6668 (and in mode MODE if that's convenient).
6669 SUBTARGET may be used as the target for computing one of EXP's operands.
6670 IGNORE is nonzero if the value is to be ignored. */
6673 alpha_expand_builtin (tree exp, rtx target,
6674 rtx subtarget ATTRIBUTE_UNUSED,
6675 enum machine_mode mode ATTRIBUTE_UNUSED,
6676 int ignore ATTRIBUTE_UNUSED)
6680 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6681 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6682 tree arglist = TREE_OPERAND (exp, 1);
6683 enum insn_code icode;
6684 rtx op[MAX_ARGS], pat;
6688 if (fcode >= ALPHA_BUILTIN_max)
6689 internal_error ("bad builtin fcode");
6690 icode = code_for_builtin[fcode];
6692 internal_error ("bad builtin fcode");
6694 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
6696 for (arglist = TREE_OPERAND (exp, 1), arity = 0;
6698 arglist = TREE_CHAIN (arglist), arity++)
6700 const struct insn_operand_data *insn_op;
6702 tree arg = TREE_VALUE (arglist);
6703 if (arg == error_mark_node)
6705 if (arity > MAX_ARGS)
6708 insn_op = &insn_data[icode].operand[arity + nonvoid];
6710 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, 0);
6712 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
6713 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
6718 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6720 || GET_MODE (target) != tmode
6721 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
6722 target = gen_reg_rtx (tmode);
6728 pat = GEN_FCN (icode) (target);
6732 pat = GEN_FCN (icode) (target, op[0]);
6734 pat = GEN_FCN (icode) (op[0]);
6737 pat = GEN_FCN (icode) (target, op[0], op[1]);
6752 /* This page contains routines that are used to determine what the function
6753 prologue and epilogue code will do and write them out. */
6755 /* Compute the size of the save area in the stack. */
6757 /* These variables are used for communication between the following functions.
6758 They indicate various things about the current function being compiled
6759 that are used to tell what kind of prologue, epilogue and procedure
6760 descriptor to generate. */
6762 /* Nonzero if we need a stack procedure. */
6763 enum alpha_procedure_types {PT_NULL = 0, PT_REGISTER = 1, PT_STACK = 2};
6764 static enum alpha_procedure_types alpha_procedure_type;
6766 /* Register number (either FP or SP) that is used to unwind the frame. */
6767 static int vms_unwind_regno;
6769 /* Register number used to save FP. We need not have one for RA since
6770 we don't modify it for register procedures. This is only defined
6771 for register frame procedures. */
6772 static int vms_save_fp_regno;
6774 /* Register number used to reference objects off our PV. */
6775 static int vms_base_regno;
6777 /* Compute register masks for saved registers. */
6780 alpha_sa_mask (unsigned long *imaskP, unsigned long *fmaskP)
6782 unsigned long imask = 0;
6783 unsigned long fmask = 0;
6786 /* When outputting a thunk, we don't have valid register life info,
6787 but assemble_start_function wants to output .frame and .mask
6789 if (current_function_is_thunk)
6796 if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
6797 imask |= (1UL << HARD_FRAME_POINTER_REGNUM);
6799 /* One for every register we have to save. */
6800 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
6801 if (! fixed_regs[i] && ! call_used_regs[i]
6802 && regs_ever_live[i] && i != REG_RA
6803 && (!TARGET_ABI_UNICOSMK || i != HARD_FRAME_POINTER_REGNUM))
6806 imask |= (1UL << i);
6808 fmask |= (1UL << (i - 32));
6811 /* We need to restore these for the handler. */
6812 if (current_function_calls_eh_return)
6816 unsigned regno = EH_RETURN_DATA_REGNO (i);
6817 if (regno == INVALID_REGNUM)
6819 imask |= 1UL << regno;
6823 /* If any register spilled, then spill the return address also. */
6824 /* ??? This is required by the Digital stack unwind specification
6825 and isn't needed if we're doing Dwarf2 unwinding. */
6826 if (imask || fmask || alpha_ra_ever_killed ())
6827 imask |= (1UL << REG_RA);
6834 alpha_sa_size (void)
6836 unsigned long mask[2];
6840 alpha_sa_mask (&mask[0], &mask[1]);
6842 if (TARGET_ABI_UNICOSMK)
6844 if (mask[0] || mask[1])
6849 for (j = 0; j < 2; ++j)
6850 for (i = 0; i < 32; ++i)
6851 if ((mask[j] >> i) & 1)
6855 if (TARGET_ABI_UNICOSMK)
6857 /* We might not need to generate a frame if we don't make any calls
6858 (including calls to __T3E_MISMATCH if this is a vararg function),
6859 don't have any local variables which require stack slots, don't
6860 use alloca and have not determined that we need a frame for other
6863 alpha_procedure_type
6864 = (sa_size || get_frame_size() != 0
6865 || current_function_outgoing_args_size
6866 || current_function_stdarg || current_function_calls_alloca
6867 || frame_pointer_needed)
6868 ? PT_STACK : PT_REGISTER;
6870 /* Always reserve space for saving callee-saved registers if we
6871 need a frame as required by the calling convention. */
6872 if (alpha_procedure_type == PT_STACK)
6875 else if (TARGET_ABI_OPEN_VMS)
6877 /* Start by assuming we can use a register procedure if we don't
6878 make any calls (REG_RA not used) or need to save any
6879 registers and a stack procedure if we do. */
6880 if ((mask[0] >> REG_RA) & 1)
6881 alpha_procedure_type = PT_STACK;
6882 else if (get_frame_size() != 0)
6883 alpha_procedure_type = PT_REGISTER;
6885 alpha_procedure_type = PT_NULL;
6887 /* Don't reserve space for saving FP & RA yet. Do that later after we've
6888 made the final decision on stack procedure vs register procedure. */
6889 if (alpha_procedure_type == PT_STACK)
6892 /* Decide whether to refer to objects off our PV via FP or PV.
6893 If we need FP for something else or if we receive a nonlocal
6894 goto (which expects PV to contain the value), we must use PV.
6895 Otherwise, start by assuming we can use FP. */
6898 = (frame_pointer_needed
6899 || current_function_has_nonlocal_label
6900 || alpha_procedure_type == PT_STACK
6901 || current_function_outgoing_args_size)
6902 ? REG_PV : HARD_FRAME_POINTER_REGNUM;
6904 /* If we want to copy PV into FP, we need to find some register
6905 in which to save FP. */
6907 vms_save_fp_regno = -1;
6908 if (vms_base_regno == HARD_FRAME_POINTER_REGNUM)
6909 for (i = 0; i < 32; i++)
6910 if (! fixed_regs[i] && call_used_regs[i] && ! regs_ever_live[i])
6911 vms_save_fp_regno = i;
6913 if (vms_save_fp_regno == -1 && alpha_procedure_type == PT_REGISTER)
6914 vms_base_regno = REG_PV, alpha_procedure_type = PT_STACK;
6915 else if (alpha_procedure_type == PT_NULL)
6916 vms_base_regno = REG_PV;
6918 /* Stack unwinding should be done via FP unless we use it for PV. */
6919 vms_unwind_regno = (vms_base_regno == REG_PV
6920 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
6922 /* If this is a stack procedure, allow space for saving FP and RA. */
6923 if (alpha_procedure_type == PT_STACK)
6928 /* Our size must be even (multiple of 16 bytes). */
6936 /* Define the offset between two registers, one to be eliminated,
6937 and the other its replacement, at the start of a routine. */
6940 alpha_initial_elimination_offset (unsigned int from,
6941 unsigned int to ATTRIBUTE_UNUSED)
6945 ret = alpha_sa_size ();
6946 ret += ALPHA_ROUND (current_function_outgoing_args_size);
6948 if (from == FRAME_POINTER_REGNUM)
6950 else if (from == ARG_POINTER_REGNUM)
6951 ret += (ALPHA_ROUND (get_frame_size ()
6952 + current_function_pretend_args_size)
6953 - current_function_pretend_args_size);
6961 alpha_pv_save_size (void)
6964 return alpha_procedure_type == PT_STACK ? 8 : 0;
6968 alpha_using_fp (void)
6971 return vms_unwind_regno == HARD_FRAME_POINTER_REGNUM;
6974 #if TARGET_ABI_OPEN_VMS
6976 const struct attribute_spec vms_attribute_table[] =
6978 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6979 { "overlaid", 0, 0, true, false, false, NULL },
6980 { "global", 0, 0, true, false, false, NULL },
6981 { "initialize", 0, 0, true, false, false, NULL },
6982 { NULL, 0, 0, false, false, false, NULL }
6988 find_lo_sum_using_gp (rtx *px, void *data ATTRIBUTE_UNUSED)
6990 return GET_CODE (*px) == LO_SUM && XEXP (*px, 0) == pic_offset_table_rtx;
6994 alpha_find_lo_sum_using_gp (rtx insn)
6996 return for_each_rtx (&PATTERN (insn), find_lo_sum_using_gp, NULL) > 0;
7000 alpha_does_function_need_gp (void)
7004 /* The GP being variable is an OSF abi thing. */
7005 if (! TARGET_ABI_OSF)
7008 /* We need the gp to load the address of __mcount. */
7009 if (TARGET_PROFILING_NEEDS_GP && current_function_profile)
7012 /* The code emitted by alpha_output_mi_thunk_osf uses the gp. */
7013 if (current_function_is_thunk)
7016 /* The nonlocal receiver pattern assumes that the gp is valid for
7017 the nested function. Reasonable because it's almost always set
7018 correctly already. For the cases where that's wrong, make sure
7019 the nested function loads its gp on entry. */
7020 if (current_function_has_nonlocal_goto)
7023 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
7024 Even if we are a static function, we still need to do this in case
7025 our address is taken and passed to something like qsort. */
7027 push_topmost_sequence ();
7028 insn = get_insns ();
7029 pop_topmost_sequence ();
7031 for (; insn; insn = NEXT_INSN (insn))
7033 && GET_CODE (PATTERN (insn)) != USE
7034 && GET_CODE (PATTERN (insn)) != CLOBBER
7035 && get_attr_usegp (insn))
7042 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
7046 set_frame_related_p (void)
7048 rtx seq = get_insns ();
7059 while (insn != NULL_RTX)
7061 RTX_FRAME_RELATED_P (insn) = 1;
7062 insn = NEXT_INSN (insn);
7064 seq = emit_insn (seq);
7068 seq = emit_insn (seq);
7069 RTX_FRAME_RELATED_P (seq) = 1;
7074 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
7076 /* Generates a store with the proper unwind info attached. VALUE is
7077 stored at BASE_REG+BASE_OFS. If FRAME_BIAS is non-zero, then BASE_REG
7078 contains SP+FRAME_BIAS, and that is the unwind info that should be
7079 generated. If FRAME_REG != VALUE, then VALUE is being stored on
7080 behalf of FRAME_REG, and FRAME_REG should be present in the unwind. */
7083 emit_frame_store_1 (rtx value, rtx base_reg, HOST_WIDE_INT frame_bias,
7084 HOST_WIDE_INT base_ofs, rtx frame_reg)
7086 rtx addr, mem, insn;
7088 addr = plus_constant (base_reg, base_ofs);
7089 mem = gen_rtx_MEM (DImode, addr);
7090 set_mem_alias_set (mem, alpha_sr_alias_set);
7092 insn = emit_move_insn (mem, value);
7093 RTX_FRAME_RELATED_P (insn) = 1;
7095 if (frame_bias || value != frame_reg)
7099 addr = plus_constant (stack_pointer_rtx, frame_bias + base_ofs);
7100 mem = gen_rtx_MEM (DImode, addr);
7104 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7105 gen_rtx_SET (VOIDmode, mem, frame_reg),
7111 emit_frame_store (unsigned int regno, rtx base_reg,
7112 HOST_WIDE_INT frame_bias, HOST_WIDE_INT base_ofs)
7114 rtx reg = gen_rtx_REG (DImode, regno);
7115 emit_frame_store_1 (reg, base_reg, frame_bias, base_ofs, reg);
7118 /* Write function prologue. */
7120 /* On vms we have two kinds of functions:
7122 - stack frame (PROC_STACK)
7123 these are 'normal' functions with local vars and which are
7124 calling other functions
7125 - register frame (PROC_REGISTER)
7126 keeps all data in registers, needs no stack
7128 We must pass this to the assembler so it can generate the
7129 proper pdsc (procedure descriptor)
7130 This is done with the '.pdesc' command.
7132 On not-vms, we don't really differentiate between the two, as we can
7133 simply allocate stack without saving registers. */
7136 alpha_expand_prologue (void)
7138 /* Registers to save. */
7139 unsigned long imask = 0;
7140 unsigned long fmask = 0;
7141 /* Stack space needed for pushing registers clobbered by us. */
7142 HOST_WIDE_INT sa_size;
7143 /* Complete stack size needed. */
7144 HOST_WIDE_INT frame_size;
7145 /* Offset from base reg to register save area. */
7146 HOST_WIDE_INT reg_offset;
7150 sa_size = alpha_sa_size ();
7152 frame_size = get_frame_size ();
7153 if (TARGET_ABI_OPEN_VMS)
7154 frame_size = ALPHA_ROUND (sa_size
7155 + (alpha_procedure_type == PT_STACK ? 8 : 0)
7157 + current_function_pretend_args_size);
7158 else if (TARGET_ABI_UNICOSMK)
7159 /* We have to allocate space for the DSIB if we generate a frame. */
7160 frame_size = ALPHA_ROUND (sa_size
7161 + (alpha_procedure_type == PT_STACK ? 48 : 0))
7162 + ALPHA_ROUND (frame_size
7163 + current_function_outgoing_args_size);
7165 frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
7167 + ALPHA_ROUND (frame_size
7168 + current_function_pretend_args_size));
7170 if (TARGET_ABI_OPEN_VMS)
7173 reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
7175 alpha_sa_mask (&imask, &fmask);
7177 /* Emit an insn to reload GP, if needed. */
7180 alpha_function_needs_gp = alpha_does_function_need_gp ();
7181 if (alpha_function_needs_gp)
7182 emit_insn (gen_prologue_ldgp ());
7185 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
7186 the call to mcount ourselves, rather than having the linker do it
7187 magically in response to -pg. Since _mcount has special linkage,
7188 don't represent the call as a call. */
7189 if (TARGET_PROFILING_NEEDS_GP && current_function_profile)
7190 emit_insn (gen_prologue_mcount ());
7192 if (TARGET_ABI_UNICOSMK)
7193 unicosmk_gen_dsib (&imask);
7195 /* Adjust the stack by the frame size. If the frame size is > 4096
7196 bytes, we need to be sure we probe somewhere in the first and last
7197 4096 bytes (we can probably get away without the latter test) and
7198 every 8192 bytes in between. If the frame size is > 32768, we
7199 do this in a loop. Otherwise, we generate the explicit probe
7202 Note that we are only allowed to adjust sp once in the prologue. */
7204 if (frame_size <= 32768)
7206 if (frame_size > 4096)
7211 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
7214 while ((probed += 8192) < frame_size);
7216 /* We only have to do this probe if we aren't saving registers. */
7217 if (sa_size == 0 && probed + 4096 < frame_size)
7218 emit_insn (gen_probe_stack (GEN_INT (-frame_size)));
7221 if (frame_size != 0)
7222 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
7223 GEN_INT (TARGET_ABI_UNICOSMK
7229 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
7230 number of 8192 byte blocks to probe. We then probe each block
7231 in the loop and then set SP to the proper location. If the
7232 amount remaining is > 4096, we have to do one more probe if we
7233 are not saving any registers. */
7235 HOST_WIDE_INT blocks = (frame_size + 4096) / 8192;
7236 HOST_WIDE_INT leftover = frame_size + 4096 - blocks * 8192;
7237 rtx ptr = gen_rtx_REG (DImode, 22);
7238 rtx count = gen_rtx_REG (DImode, 23);
7241 emit_move_insn (count, GEN_INT (blocks));
7242 emit_insn (gen_adddi3 (ptr, stack_pointer_rtx,
7243 GEN_INT (TARGET_ABI_UNICOSMK ? 4096 - 64 : 4096)));
7245 /* Because of the difficulty in emitting a new basic block this
7246 late in the compilation, generate the loop as a single insn. */
7247 emit_insn (gen_prologue_stack_probe_loop (count, ptr));
7249 if (leftover > 4096 && sa_size == 0)
7251 rtx last = gen_rtx_MEM (DImode, plus_constant (ptr, -leftover));
7252 MEM_VOLATILE_P (last) = 1;
7253 emit_move_insn (last, const0_rtx);
7256 if (TARGET_ABI_WINDOWS_NT)
7258 /* For NT stack unwind (done by 'reverse execution'), it's
7259 not OK to take the result of a loop, even though the value
7260 is already in ptr, so we reload it via a single operation
7261 and subtract it to sp.
7263 Yes, that's correct -- we have to reload the whole constant
7264 into a temporary via ldah+lda then subtract from sp. */
7266 HOST_WIDE_INT lo, hi;
7267 lo = ((frame_size & 0xffff) ^ 0x8000) - 0x8000;
7268 hi = frame_size - lo;
7270 emit_move_insn (ptr, GEN_INT (hi));
7271 emit_insn (gen_adddi3 (ptr, ptr, GEN_INT (lo)));
7272 seq = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
7277 seq = emit_insn (gen_adddi3 (stack_pointer_rtx, ptr,
7278 GEN_INT (-leftover)));
7281 /* This alternative is special, because the DWARF code cannot
7282 possibly intuit through the loop above. So we invent this
7283 note it looks at instead. */
7284 RTX_FRAME_RELATED_P (seq) = 1;
7286 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7287 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7288 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7289 GEN_INT (TARGET_ABI_UNICOSMK
7295 if (!TARGET_ABI_UNICOSMK)
7297 HOST_WIDE_INT sa_bias = 0;
7299 /* Cope with very large offsets to the register save area. */
7300 sa_reg = stack_pointer_rtx;
7301 if (reg_offset + sa_size > 0x8000)
7303 int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000;
7306 if (low + sa_size <= 0x8000)
7307 sa_bias = reg_offset - low, reg_offset = low;
7309 sa_bias = reg_offset, reg_offset = 0;
7311 sa_reg = gen_rtx_REG (DImode, 24);
7312 sa_bias_rtx = GEN_INT (sa_bias);
7314 if (add_operand (sa_bias_rtx, DImode))
7315 emit_insn (gen_adddi3 (sa_reg, stack_pointer_rtx, sa_bias_rtx));
7318 emit_move_insn (sa_reg, sa_bias_rtx);
7319 emit_insn (gen_adddi3 (sa_reg, stack_pointer_rtx, sa_reg));
7323 /* Save regs in stack order. Beginning with VMS PV. */
7324 if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
7325 emit_frame_store (REG_PV, stack_pointer_rtx, 0, 0);
7327 /* Save register RA next. */
7328 if (imask & (1UL << REG_RA))
7330 emit_frame_store (REG_RA, sa_reg, sa_bias, reg_offset);
7331 imask &= ~(1UL << REG_RA);
7335 /* Now save any other registers required to be saved. */
7336 for (i = 0; i < 31; i++)
7337 if (imask & (1UL << i))
7339 emit_frame_store (i, sa_reg, sa_bias, reg_offset);
7343 for (i = 0; i < 31; i++)
7344 if (fmask & (1UL << i))
7346 emit_frame_store (i+32, sa_reg, sa_bias, reg_offset);
7350 else if (TARGET_ABI_UNICOSMK && alpha_procedure_type == PT_STACK)
7352 /* The standard frame on the T3E includes space for saving registers.
7353 We just have to use it. We don't have to save the return address and
7354 the old frame pointer here - they are saved in the DSIB. */
7357 for (i = 9; i < 15; i++)
7358 if (imask & (1UL << i))
7360 emit_frame_store (i, hard_frame_pointer_rtx, 0, reg_offset);
7363 for (i = 2; i < 10; i++)
7364 if (fmask & (1UL << i))
7366 emit_frame_store (i+32, hard_frame_pointer_rtx, 0, reg_offset);
7371 if (TARGET_ABI_OPEN_VMS)
7373 if (alpha_procedure_type == PT_REGISTER)
7374 /* Register frame procedures save the fp.
7375 ?? Ought to have a dwarf2 save for this. */
7376 emit_move_insn (gen_rtx_REG (DImode, vms_save_fp_regno),
7377 hard_frame_pointer_rtx);
7379 if (alpha_procedure_type != PT_NULL && vms_base_regno != REG_PV)
7380 emit_insn (gen_force_movdi (gen_rtx_REG (DImode, vms_base_regno),
7381 gen_rtx_REG (DImode, REG_PV)));
7383 if (alpha_procedure_type != PT_NULL
7384 && vms_unwind_regno == HARD_FRAME_POINTER_REGNUM)
7385 FRP (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx));
7387 /* If we have to allocate space for outgoing args, do it now. */
7388 if (current_function_outgoing_args_size != 0)
7391 = emit_move_insn (stack_pointer_rtx,
7393 (hard_frame_pointer_rtx,
7395 (current_function_outgoing_args_size))));
7397 /* Only set FRAME_RELATED_P on the stack adjustment we just emitted
7398 if ! frame_pointer_needed. Setting the bit will change the CFA
7399 computation rule to use sp again, which would be wrong if we had
7400 frame_pointer_needed, as this means sp might move unpredictably
7404 frame_pointer_needed
7405 => vms_unwind_regno == HARD_FRAME_POINTER_REGNUM
7407 current_function_outgoing_args_size != 0
7408 => alpha_procedure_type != PT_NULL,
7410 so when we are not setting the bit here, we are guaranteed to
7411 have emitted an FRP frame pointer update just before. */
7412 RTX_FRAME_RELATED_P (seq) = ! frame_pointer_needed;
7415 else if (!TARGET_ABI_UNICOSMK)
7417 /* If we need a frame pointer, set it from the stack pointer. */
7418 if (frame_pointer_needed)
7420 if (TARGET_CAN_FAULT_IN_PROLOGUE)
7421 FRP (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx));
7423 /* This must always be the last instruction in the
7424 prologue, thus we emit a special move + clobber. */
7425 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx,
7426 stack_pointer_rtx, sa_reg)));
7430 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
7431 the prologue, for exception handling reasons, we cannot do this for
7432 any insn that might fault. We could prevent this for mems with a
7433 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
7434 have to prevent all such scheduling with a blockage.
7436 Linux, on the other hand, never bothered to implement OSF/1's
7437 exception handling, and so doesn't care about such things. Anyone
7438 planning to use dwarf2 frame-unwind info can also omit the blockage. */
7440 if (! TARGET_CAN_FAULT_IN_PROLOGUE)
7441 emit_insn (gen_blockage ());
7444 /* Output the textual info surrounding the prologue. */
7447 alpha_start_function (FILE *file, const char *fnname,
7448 tree decl ATTRIBUTE_UNUSED)
7450 unsigned long imask = 0;
7451 unsigned long fmask = 0;
7452 /* Stack space needed for pushing registers clobbered by us. */
7453 HOST_WIDE_INT sa_size;
7454 /* Complete stack size needed. */
7455 unsigned HOST_WIDE_INT frame_size;
7456 /* Offset from base reg to register save area. */
7457 HOST_WIDE_INT reg_offset;
7458 char *entry_label = (char *) alloca (strlen (fnname) + 6);
7461 /* Don't emit an extern directive for functions defined in the same file. */
7462 if (TARGET_ABI_UNICOSMK)
7465 name_tree = get_identifier (fnname);
7466 TREE_ASM_WRITTEN (name_tree) = 1;
7469 alpha_fnname = fnname;
7470 sa_size = alpha_sa_size ();
7472 frame_size = get_frame_size ();
7473 if (TARGET_ABI_OPEN_VMS)
7474 frame_size = ALPHA_ROUND (sa_size
7475 + (alpha_procedure_type == PT_STACK ? 8 : 0)
7477 + current_function_pretend_args_size);
7478 else if (TARGET_ABI_UNICOSMK)
7479 frame_size = ALPHA_ROUND (sa_size
7480 + (alpha_procedure_type == PT_STACK ? 48 : 0))
7481 + ALPHA_ROUND (frame_size
7482 + current_function_outgoing_args_size);
7484 frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
7486 + ALPHA_ROUND (frame_size
7487 + current_function_pretend_args_size));
7489 if (TARGET_ABI_OPEN_VMS)
7492 reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
7494 alpha_sa_mask (&imask, &fmask);
7496 /* Ecoff can handle multiple .file directives, so put out file and lineno.
7497 We have to do that before the .ent directive as we cannot switch
7498 files within procedures with native ecoff because line numbers are
7499 linked to procedure descriptors.
7500 Outputting the lineno helps debugging of one line functions as they
7501 would otherwise get no line number at all. Please note that we would
7502 like to put out last_linenum from final.c, but it is not accessible. */
7504 if (write_symbols == SDB_DEBUG)
7506 #ifdef ASM_OUTPUT_SOURCE_FILENAME
7507 ASM_OUTPUT_SOURCE_FILENAME (file,
7508 DECL_SOURCE_FILE (current_function_decl));
7510 #ifdef ASM_OUTPUT_SOURCE_LINE
7511 if (debug_info_level != DINFO_LEVEL_TERSE)
7512 ASM_OUTPUT_SOURCE_LINE (file,
7513 DECL_SOURCE_LINE (current_function_decl), 0);
7517 /* Issue function start and label. */
7518 if (TARGET_ABI_OPEN_VMS
7519 || (!TARGET_ABI_UNICOSMK && !flag_inhibit_size_directive))
7521 fputs ("\t.ent ", file);
7522 assemble_name (file, fnname);
7525 /* If the function needs GP, we'll write the "..ng" label there.
7526 Otherwise, do it here. */
7528 && ! alpha_function_needs_gp
7529 && ! current_function_is_thunk)
7532 assemble_name (file, fnname);
7533 fputs ("..ng:\n", file);
7537 strcpy (entry_label, fnname);
7538 if (TARGET_ABI_OPEN_VMS)
7539 strcat (entry_label, "..en");
7541 /* For public functions, the label must be globalized by appending an
7542 additional colon. */
7543 if (TARGET_ABI_UNICOSMK && TREE_PUBLIC (decl))
7544 strcat (entry_label, ":");
7546 ASM_OUTPUT_LABEL (file, entry_label);
7547 inside_function = TRUE;
7549 if (TARGET_ABI_OPEN_VMS)
7550 fprintf (file, "\t.base $%d\n", vms_base_regno);
7552 if (!TARGET_ABI_OPEN_VMS && !TARGET_ABI_UNICOSMK && TARGET_IEEE_CONFORMANT
7553 && !flag_inhibit_size_directive)
7555 /* Set flags in procedure descriptor to request IEEE-conformant
7556 math-library routines. The value we set it to is PDSC_EXC_IEEE
7557 (/usr/include/pdsc.h). */
7558 fputs ("\t.eflag 48\n", file);
7561 /* Set up offsets to alpha virtual arg/local debugging pointer. */
7562 alpha_auto_offset = -frame_size + current_function_pretend_args_size;
7563 alpha_arg_offset = -frame_size + 48;
7565 /* Describe our frame. If the frame size is larger than an integer,
7566 print it as zero to avoid an assembler error. We won't be
7567 properly describing such a frame, but that's the best we can do. */
7568 if (TARGET_ABI_UNICOSMK)
7570 else if (TARGET_ABI_OPEN_VMS)
7571 fprintf (file, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC ",$26,"
7572 HOST_WIDE_INT_PRINT_DEC "\n",
7574 frame_size >= (1UL << 31) ? 0 : frame_size,
7576 else if (!flag_inhibit_size_directive)
7577 fprintf (file, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC ",$26,%d\n",
7578 (frame_pointer_needed
7579 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM),
7580 frame_size >= (1UL << 31) ? 0 : frame_size,
7581 current_function_pretend_args_size);
7583 /* Describe which registers were spilled. */
7584 if (TARGET_ABI_UNICOSMK)
7586 else if (TARGET_ABI_OPEN_VMS)
7589 /* ??? Does VMS care if mask contains ra? The old code didn't
7590 set it, so I don't here. */
7591 fprintf (file, "\t.mask 0x%lx,0\n", imask & ~(1UL << REG_RA));
7593 fprintf (file, "\t.fmask 0x%lx,0\n", fmask);
7594 if (alpha_procedure_type == PT_REGISTER)
7595 fprintf (file, "\t.fp_save $%d\n", vms_save_fp_regno);
7597 else if (!flag_inhibit_size_directive)
7601 fprintf (file, "\t.mask 0x%lx," HOST_WIDE_INT_PRINT_DEC "\n", imask,
7602 frame_size >= (1UL << 31) ? 0 : reg_offset - frame_size);
7604 for (i = 0; i < 32; ++i)
7605 if (imask & (1UL << i))
7610 fprintf (file, "\t.fmask 0x%lx," HOST_WIDE_INT_PRINT_DEC "\n", fmask,
7611 frame_size >= (1UL << 31) ? 0 : reg_offset - frame_size);
7614 #if TARGET_ABI_OPEN_VMS
7615 /* Ifdef'ed cause link_section are only available then. */
7616 readonly_data_section ();
7617 fprintf (file, "\t.align 3\n");
7618 assemble_name (file, fnname); fputs ("..na:\n", file);
7619 fputs ("\t.ascii \"", file);
7620 assemble_name (file, fnname);
7621 fputs ("\\0\"\n", file);
7622 alpha_need_linkage (fnname, 1);
7627 /* Emit the .prologue note at the scheduled end of the prologue. */
7630 alpha_output_function_end_prologue (FILE *file)
7632 if (TARGET_ABI_UNICOSMK)
7634 else if (TARGET_ABI_OPEN_VMS)
7635 fputs ("\t.prologue\n", file);
7636 else if (TARGET_ABI_WINDOWS_NT)
7637 fputs ("\t.prologue 0\n", file);
7638 else if (!flag_inhibit_size_directive)
7639 fprintf (file, "\t.prologue %d\n",
7640 alpha_function_needs_gp || current_function_is_thunk);
7643 /* Write function epilogue. */
7645 /* ??? At some point we will want to support full unwind, and so will
7646 need to mark the epilogue as well. At the moment, we just confuse
7649 #define FRP(exp) exp
7652 alpha_expand_epilogue (void)
7654 /* Registers to save. */
7655 unsigned long imask = 0;
7656 unsigned long fmask = 0;
7657 /* Stack space needed for pushing registers clobbered by us. */
7658 HOST_WIDE_INT sa_size;
7659 /* Complete stack size needed. */
7660 HOST_WIDE_INT frame_size;
7661 /* Offset from base reg to register save area. */
7662 HOST_WIDE_INT reg_offset;
7663 int fp_is_frame_pointer, fp_offset;
7664 rtx sa_reg, sa_reg_exp = NULL;
7665 rtx sp_adj1, sp_adj2, mem;
7669 sa_size = alpha_sa_size ();
7671 frame_size = get_frame_size ();
7672 if (TARGET_ABI_OPEN_VMS)
7673 frame_size = ALPHA_ROUND (sa_size
7674 + (alpha_procedure_type == PT_STACK ? 8 : 0)
7676 + current_function_pretend_args_size);
7677 else if (TARGET_ABI_UNICOSMK)
7678 frame_size = ALPHA_ROUND (sa_size
7679 + (alpha_procedure_type == PT_STACK ? 48 : 0))
7680 + ALPHA_ROUND (frame_size
7681 + current_function_outgoing_args_size);
7683 frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
7685 + ALPHA_ROUND (frame_size
7686 + current_function_pretend_args_size));
7688 if (TARGET_ABI_OPEN_VMS)
7690 if (alpha_procedure_type == PT_STACK)
7696 reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
7698 alpha_sa_mask (&imask, &fmask);
7701 = ((TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
7702 || (!TARGET_ABI_OPEN_VMS && frame_pointer_needed));
7704 sa_reg = stack_pointer_rtx;
7706 if (current_function_calls_eh_return)
7707 eh_ofs = EH_RETURN_STACKADJ_RTX;
7711 if (!TARGET_ABI_UNICOSMK && sa_size)
7713 /* If we have a frame pointer, restore SP from it. */
7714 if ((TARGET_ABI_OPEN_VMS
7715 && vms_unwind_regno == HARD_FRAME_POINTER_REGNUM)
7716 || (!TARGET_ABI_OPEN_VMS && frame_pointer_needed))
7717 FRP (emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx));
7719 /* Cope with very large offsets to the register save area. */
7720 if (reg_offset + sa_size > 0x8000)
7722 int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000;
7725 if (low + sa_size <= 0x8000)
7726 bias = reg_offset - low, reg_offset = low;
7728 bias = reg_offset, reg_offset = 0;
7730 sa_reg = gen_rtx_REG (DImode, 22);
7731 sa_reg_exp = plus_constant (stack_pointer_rtx, bias);
7733 FRP (emit_move_insn (sa_reg, sa_reg_exp));
7736 /* Restore registers in order, excepting a true frame pointer. */
7738 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
7740 set_mem_alias_set (mem, alpha_sr_alias_set);
7741 FRP (emit_move_insn (gen_rtx_REG (DImode, REG_RA), mem));
7744 imask &= ~(1UL << REG_RA);
7746 for (i = 0; i < 31; ++i)
7747 if (imask & (1UL << i))
7749 if (i == HARD_FRAME_POINTER_REGNUM && fp_is_frame_pointer)
7750 fp_offset = reg_offset;
7753 mem = gen_rtx_MEM (DImode, plus_constant(sa_reg, reg_offset));
7754 set_mem_alias_set (mem, alpha_sr_alias_set);
7755 FRP (emit_move_insn (gen_rtx_REG (DImode, i), mem));
7760 for (i = 0; i < 31; ++i)
7761 if (fmask & (1UL << i))
7763 mem = gen_rtx_MEM (DFmode, plus_constant(sa_reg, reg_offset));
7764 set_mem_alias_set (mem, alpha_sr_alias_set);
7765 FRP (emit_move_insn (gen_rtx_REG (DFmode, i+32), mem));
7769 else if (TARGET_ABI_UNICOSMK && alpha_procedure_type == PT_STACK)
7771 /* Restore callee-saved general-purpose registers. */
7775 for (i = 9; i < 15; i++)
7776 if (imask & (1UL << i))
7778 mem = gen_rtx_MEM (DImode, plus_constant(hard_frame_pointer_rtx,
7780 set_mem_alias_set (mem, alpha_sr_alias_set);
7781 FRP (emit_move_insn (gen_rtx_REG (DImode, i), mem));
7785 for (i = 2; i < 10; i++)
7786 if (fmask & (1UL << i))
7788 mem = gen_rtx_MEM (DFmode, plus_constant(hard_frame_pointer_rtx,
7790 set_mem_alias_set (mem, alpha_sr_alias_set);
7791 FRP (emit_move_insn (gen_rtx_REG (DFmode, i+32), mem));
7795 /* Restore the return address from the DSIB. */
7797 mem = gen_rtx_MEM (DImode, plus_constant(hard_frame_pointer_rtx, -8));
7798 set_mem_alias_set (mem, alpha_sr_alias_set);
7799 FRP (emit_move_insn (gen_rtx_REG (DImode, REG_RA), mem));
7802 if (frame_size || eh_ofs)
7804 sp_adj1 = stack_pointer_rtx;
7808 sp_adj1 = gen_rtx_REG (DImode, 23);
7809 emit_move_insn (sp_adj1,
7810 gen_rtx_PLUS (Pmode, stack_pointer_rtx, eh_ofs));
7813 /* If the stack size is large, begin computation into a temporary
7814 register so as not to interfere with a potential fp restore,
7815 which must be consecutive with an SP restore. */
7816 if (frame_size < 32768
7817 && ! (TARGET_ABI_UNICOSMK && current_function_calls_alloca))
7818 sp_adj2 = GEN_INT (frame_size);
7819 else if (TARGET_ABI_UNICOSMK)
7821 sp_adj1 = gen_rtx_REG (DImode, 23);
7822 FRP (emit_move_insn (sp_adj1, hard_frame_pointer_rtx));
7823 sp_adj2 = const0_rtx;
7825 else if (frame_size < 0x40007fffL)
7827 int low = ((frame_size & 0xffff) ^ 0x8000) - 0x8000;
7829 sp_adj2 = plus_constant (sp_adj1, frame_size - low);
7830 if (sa_reg_exp && rtx_equal_p (sa_reg_exp, sp_adj2))
7834 sp_adj1 = gen_rtx_REG (DImode, 23);
7835 FRP (emit_move_insn (sp_adj1, sp_adj2));
7837 sp_adj2 = GEN_INT (low);
7841 rtx tmp = gen_rtx_REG (DImode, 23);
7842 FRP (sp_adj2 = alpha_emit_set_const (tmp, DImode, frame_size, 3));
7845 /* We can't drop new things to memory this late, afaik,
7846 so build it up by pieces. */
7847 FRP (sp_adj2 = alpha_emit_set_long_const (tmp, frame_size,
7848 -(frame_size < 0)));
7854 /* From now on, things must be in order. So emit blockages. */
7856 /* Restore the frame pointer. */
7857 if (TARGET_ABI_UNICOSMK)
7859 emit_insn (gen_blockage ());
7860 mem = gen_rtx_MEM (DImode,
7861 plus_constant (hard_frame_pointer_rtx, -16));
7862 set_mem_alias_set (mem, alpha_sr_alias_set);
7863 FRP (emit_move_insn (hard_frame_pointer_rtx, mem));
7865 else if (fp_is_frame_pointer)
7867 emit_insn (gen_blockage ());
7868 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, fp_offset));
7869 set_mem_alias_set (mem, alpha_sr_alias_set);
7870 FRP (emit_move_insn (hard_frame_pointer_rtx, mem));
7872 else if (TARGET_ABI_OPEN_VMS)
7874 emit_insn (gen_blockage ());
7875 FRP (emit_move_insn (hard_frame_pointer_rtx,
7876 gen_rtx_REG (DImode, vms_save_fp_regno)));
7879 /* Restore the stack pointer. */
7880 emit_insn (gen_blockage ());
7881 if (sp_adj2 == const0_rtx)
7882 FRP (emit_move_insn (stack_pointer_rtx, sp_adj1));
7884 FRP (emit_move_insn (stack_pointer_rtx,
7885 gen_rtx_PLUS (DImode, sp_adj1, sp_adj2)));
7889 if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_REGISTER)
7891 emit_insn (gen_blockage ());
7892 FRP (emit_move_insn (hard_frame_pointer_rtx,
7893 gen_rtx_REG (DImode, vms_save_fp_regno)));
7895 else if (TARGET_ABI_UNICOSMK && alpha_procedure_type != PT_STACK)
7897 /* Decrement the frame pointer if the function does not have a
7900 emit_insn (gen_blockage ());
7901 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7902 hard_frame_pointer_rtx, GEN_INT (-1))));
7907 /* Output the rest of the textual info surrounding the epilogue. */
7910 alpha_end_function (FILE *file, const char *fnname, tree decl ATTRIBUTE_UNUSED)
7912 /* End the function. */
7913 if (!TARGET_ABI_UNICOSMK && !flag_inhibit_size_directive)
7915 fputs ("\t.end ", file);
7916 assemble_name (file, fnname);
7919 inside_function = FALSE;
7921 #if TARGET_ABI_OPEN_VMS
7922 alpha_write_linkage (file, fnname, decl);
7925 /* Output jump tables and the static subroutine information block. */
7926 if (TARGET_ABI_UNICOSMK)
7928 unicosmk_output_ssib (file, fnname);
7929 unicosmk_output_deferred_case_vectors (file);
7934 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
7936 In order to avoid the hordes of differences between generated code
7937 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
7938 lots of code loading up large constants, generate rtl and emit it
7939 instead of going straight to text.
7941 Not sure why this idea hasn't been explored before... */
7944 alpha_output_mi_thunk_osf (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
7945 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
7948 HOST_WIDE_INT hi, lo;
7949 rtx this, insn, funexp;
7951 /* We always require a valid GP. */
7952 emit_insn (gen_prologue_ldgp ());
7953 emit_note (NOTE_INSN_PROLOGUE_END);
7955 /* Find the "this" pointer. If the function returns a structure,
7956 the structure return pointer is in $16. */
7957 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
7958 this = gen_rtx_REG (Pmode, 17);
7960 this = gen_rtx_REG (Pmode, 16);
7962 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
7963 entire constant for the add. */
7964 lo = ((delta & 0xffff) ^ 0x8000) - 0x8000;
7965 hi = (((delta - lo) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7966 if (hi + lo == delta)
7969 emit_insn (gen_adddi3 (this, this, GEN_INT (hi)));
7971 emit_insn (gen_adddi3 (this, this, GEN_INT (lo)));
7975 rtx tmp = alpha_emit_set_long_const (gen_rtx_REG (Pmode, 0),
7976 delta, -(delta < 0));
7977 emit_insn (gen_adddi3 (this, this, tmp));
7980 /* Add a delta stored in the vtable at VCALL_OFFSET. */
7985 tmp = gen_rtx_REG (Pmode, 0);
7986 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
7988 lo = ((vcall_offset & 0xffff) ^ 0x8000) - 0x8000;
7989 hi = (((vcall_offset - lo) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7990 if (hi + lo == vcall_offset)
7993 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT (hi)));
7997 tmp2 = alpha_emit_set_long_const (gen_rtx_REG (Pmode, 1),
7998 vcall_offset, -(vcall_offset < 0));
7999 emit_insn (gen_adddi3 (tmp, tmp, tmp2));
8003 tmp2 = gen_rtx_PLUS (Pmode, tmp, GEN_INT (lo));
8006 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp2));
8008 emit_insn (gen_adddi3 (this, this, tmp));
8011 /* Generate a tail call to the target function. */
8012 if (! TREE_USED (function))
8014 assemble_external (function);
8015 TREE_USED (function) = 1;
8017 funexp = XEXP (DECL_RTL (function), 0);
8018 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
8019 insn = emit_call_insn (gen_sibcall (funexp, const0_rtx));
8020 SIBLING_CALL_P (insn) = 1;
8022 /* Run just enough of rest_of_compilation to get the insns emitted.
8023 There's not really enough bulk here to make other passes such as
8024 instruction scheduling worth while. Note that use_thunk calls
8025 assemble_start_function and assemble_end_function. */
8026 insn = get_insns ();
8027 insn_locators_initialize ();
8028 shorten_branches (insn);
8029 final_start_function (insn, file, 1);
8030 final (insn, file, 1, 0);
8031 final_end_function ();
8033 #endif /* TARGET_ABI_OSF */
8035 /* Debugging support. */
8039 /* Count the number of sdb related labels are generated (to find block
8040 start and end boundaries). */
8042 int sdb_label_count = 0;
8044 /* Next label # for each statement. */
8046 static int sym_lineno = 0;
8048 /* Count the number of .file directives, so that .loc is up to date. */
8050 static int num_source_filenames = 0;
8052 /* Name of the file containing the current function. */
8054 static const char *current_function_file = "";
8056 /* Offsets to alpha virtual arg/local debugging pointers. */
8058 long alpha_arg_offset;
8059 long alpha_auto_offset;
8061 /* Emit a new filename to a stream. */
8064 alpha_output_filename (FILE *stream, const char *name)
8066 static int first_time = TRUE;
8067 char ltext_label_name[100];
8072 ++num_source_filenames;
8073 current_function_file = name;
8074 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8075 output_quoted_string (stream, name);
8076 fprintf (stream, "\n");
8077 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
8078 fprintf (stream, "\t#@stabs\n");
8081 else if (write_symbols == DBX_DEBUG)
8083 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
8084 fprintf (stream, "%s", ASM_STABS_OP);
8085 output_quoted_string (stream, name);
8086 fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]);
8089 else if (name != current_function_file
8090 && strcmp (name, current_function_file) != 0)
8092 if (inside_function && ! TARGET_GAS)
8093 fprintf (stream, "\t#.file\t%d ", num_source_filenames);
8096 ++num_source_filenames;
8097 current_function_file = name;
8098 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8101 output_quoted_string (stream, name);
8102 fprintf (stream, "\n");
8106 /* Emit a linenumber to a stream. */
8109 alpha_output_lineno (FILE *stream, int line)
8111 if (write_symbols == DBX_DEBUG)
8113 /* mips-tfile doesn't understand .stabd directives. */
8115 fprintf (stream, "$LM%d:\n%s%d,0,%d,$LM%d\n",
8116 sym_lineno, ASM_STABN_OP, N_SLINE, line, sym_lineno);
8119 fprintf (stream, "\n\t.loc\t%d %d\n", num_source_filenames, line);
8122 /* Structure to show the current status of registers and memory. */
8124 struct shadow_summary
8127 unsigned int i : 31; /* Mask of int regs */
8128 unsigned int fp : 31; /* Mask of fp regs */
8129 unsigned int mem : 1; /* mem == imem | fpmem */
8133 /* Summary the effects of expression X on the machine. Update SUM, a pointer
8134 to the summary structure. SET is nonzero if the insn is setting the
8135 object, otherwise zero. */
8138 summarize_insn (rtx x, struct shadow_summary *sum, int set)
8140 const char *format_ptr;
8146 switch (GET_CODE (x))
8148 /* ??? Note that this case would be incorrect if the Alpha had a
8149 ZERO_EXTRACT in SET_DEST. */
8151 summarize_insn (SET_SRC (x), sum, 0);
8152 summarize_insn (SET_DEST (x), sum, 1);
8156 summarize_insn (XEXP (x, 0), sum, 1);
8160 summarize_insn (XEXP (x, 0), sum, 0);
8164 for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; i--)
8165 summarize_insn (ASM_OPERANDS_INPUT (x, i), sum, 0);
8169 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
8170 summarize_insn (XVECEXP (x, 0, i), sum, 0);
8174 summarize_insn (SUBREG_REG (x), sum, 0);
8179 int regno = REGNO (x);
8180 unsigned long mask = ((unsigned long) 1) << (regno % 32);
8182 if (regno == 31 || regno == 63)
8188 sum->defd.i |= mask;
8190 sum->defd.fp |= mask;
8195 sum->used.i |= mask;
8197 sum->used.fp |= mask;
8208 /* Find the regs used in memory address computation: */
8209 summarize_insn (XEXP (x, 0), sum, 0);
8212 case CONST_INT: case CONST_DOUBLE:
8213 case SYMBOL_REF: case LABEL_REF: case CONST:
8214 case SCRATCH: case ASM_INPUT:
8217 /* Handle common unary and binary ops for efficiency. */
8218 case COMPARE: case PLUS: case MINUS: case MULT: case DIV:
8219 case MOD: case UDIV: case UMOD: case AND: case IOR:
8220 case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT:
8221 case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX:
8222 case NE: case EQ: case GE: case GT: case LE:
8223 case LT: case GEU: case GTU: case LEU: case LTU:
8224 summarize_insn (XEXP (x, 0), sum, 0);
8225 summarize_insn (XEXP (x, 1), sum, 0);
8228 case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND:
8229 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT:
8230 case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS:
8231 case SQRT: case FFS:
8232 summarize_insn (XEXP (x, 0), sum, 0);
8236 format_ptr = GET_RTX_FORMAT (GET_CODE (x));
8237 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
8238 switch (format_ptr[i])
8241 summarize_insn (XEXP (x, i), sum, 0);
8245 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8246 summarize_insn (XVECEXP (x, i, j), sum, 0);
8258 /* Ensure a sufficient number of `trapb' insns are in the code when
8259 the user requests code with a trap precision of functions or
8262 In naive mode, when the user requests a trap-precision of
8263 "instruction", a trapb is needed after every instruction that may
8264 generate a trap. This ensures that the code is resumption safe but
8267 When optimizations are turned on, we delay issuing a trapb as long
8268 as possible. In this context, a trap shadow is the sequence of
8269 instructions that starts with a (potentially) trap generating
8270 instruction and extends to the next trapb or call_pal instruction
8271 (but GCC never generates call_pal by itself). We can delay (and
8272 therefore sometimes omit) a trapb subject to the following
8275 (a) On entry to the trap shadow, if any Alpha register or memory
8276 location contains a value that is used as an operand value by some
8277 instruction in the trap shadow (live on entry), then no instruction
8278 in the trap shadow may modify the register or memory location.
8280 (b) Within the trap shadow, the computation of the base register
8281 for a memory load or store instruction may not involve using the
8282 result of an instruction that might generate an UNPREDICTABLE
8285 (c) Within the trap shadow, no register may be used more than once
8286 as a destination register. (This is to make life easier for the
8289 (d) The trap shadow may not include any branch instructions. */
8292 alpha_handle_trap_shadows (void)
8294 struct shadow_summary shadow;
8295 int trap_pending, exception_nesting;
8299 exception_nesting = 0;
8302 shadow.used.mem = 0;
8303 shadow.defd = shadow.used;
8305 for (i = get_insns (); i ; i = NEXT_INSN (i))
8307 if (GET_CODE (i) == NOTE)
8309 switch (NOTE_LINE_NUMBER (i))
8311 case NOTE_INSN_EH_REGION_BEG:
8312 exception_nesting++;
8317 case NOTE_INSN_EH_REGION_END:
8318 exception_nesting--;
8323 case NOTE_INSN_EPILOGUE_BEG:
8324 if (trap_pending && alpha_tp >= ALPHA_TP_FUNC)
8329 else if (trap_pending)
8331 if (alpha_tp == ALPHA_TP_FUNC)
8333 if (GET_CODE (i) == JUMP_INSN
8334 && GET_CODE (PATTERN (i)) == RETURN)
8337 else if (alpha_tp == ALPHA_TP_INSN)
8341 struct shadow_summary sum;
8346 sum.defd = sum.used;
8348 switch (GET_CODE (i))
8351 /* Annoyingly, get_attr_trap will abort on these. */
8352 if (GET_CODE (PATTERN (i)) == USE
8353 || GET_CODE (PATTERN (i)) == CLOBBER)
8356 summarize_insn (PATTERN (i), &sum, 0);
8358 if ((sum.defd.i & shadow.defd.i)
8359 || (sum.defd.fp & shadow.defd.fp))
8361 /* (c) would be violated */
8365 /* Combine shadow with summary of current insn: */
8366 shadow.used.i |= sum.used.i;
8367 shadow.used.fp |= sum.used.fp;
8368 shadow.used.mem |= sum.used.mem;
8369 shadow.defd.i |= sum.defd.i;
8370 shadow.defd.fp |= sum.defd.fp;
8371 shadow.defd.mem |= sum.defd.mem;
8373 if ((sum.defd.i & shadow.used.i)
8374 || (sum.defd.fp & shadow.used.fp)
8375 || (sum.defd.mem & shadow.used.mem))
8377 /* (a) would be violated (also takes care of (b)) */
8378 if (get_attr_trap (i) == TRAP_YES
8379 && ((sum.defd.i & sum.used.i)
8380 || (sum.defd.fp & sum.used.fp)))
8399 n = emit_insn_before (gen_trapb (), i);
8400 PUT_MODE (n, TImode);
8401 PUT_MODE (i, TImode);
8405 shadow.used.mem = 0;
8406 shadow.defd = shadow.used;
8411 if ((exception_nesting > 0 || alpha_tp >= ALPHA_TP_FUNC)
8412 && GET_CODE (i) == INSN
8413 && GET_CODE (PATTERN (i)) != USE
8414 && GET_CODE (PATTERN (i)) != CLOBBER
8415 && get_attr_trap (i) == TRAP_YES)
8417 if (optimize && !trap_pending)
8418 summarize_insn (PATTERN (i), &shadow, 0);
8424 /* Alpha can only issue instruction groups simultaneously if they are
8425 suitably aligned. This is very processor-specific. */
8427 enum alphaev4_pipe {
8434 enum alphaev5_pipe {
8445 static enum alphaev4_pipe
8446 alphaev4_insn_pipe (rtx insn)
8448 if (recog_memoized (insn) < 0)
8450 if (get_attr_length (insn) != 4)
8453 switch (get_attr_type (insn))
8487 static enum alphaev5_pipe
8488 alphaev5_insn_pipe (rtx insn)
8490 if (recog_memoized (insn) < 0)
8492 if (get_attr_length (insn) != 4)
8495 switch (get_attr_type (insn))
8536 /* IN_USE is a mask of the slots currently filled within the insn group.
8537 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
8538 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
8540 LEN is, of course, the length of the group in bytes. */
8543 alphaev4_next_group (rtx insn, int *pin_use, int *plen)
8550 || GET_CODE (PATTERN (insn)) == CLOBBER
8551 || GET_CODE (PATTERN (insn)) == USE)
8556 enum alphaev4_pipe pipe;
8558 pipe = alphaev4_insn_pipe (insn);
8562 /* Force complex instructions to start new groups. */
8566 /* If this is a completely unrecognized insn, its an asm.
8567 We don't know how long it is, so record length as -1 to
8568 signal a needed realignment. */
8569 if (recog_memoized (insn) < 0)
8572 len = get_attr_length (insn);
8576 if (in_use & EV4_IB0)
8578 if (in_use & EV4_IB1)
8583 in_use |= EV4_IB0 | EV4_IBX;
8587 if (in_use & EV4_IB0)
8589 if (!(in_use & EV4_IBX) || (in_use & EV4_IB1))
8597 if (in_use & EV4_IB1)
8607 /* Haifa doesn't do well scheduling branches. */
8608 if (GET_CODE (insn) == JUMP_INSN)
8612 insn = next_nonnote_insn (insn);
8614 if (!insn || ! INSN_P (insn))
8617 /* Let Haifa tell us where it thinks insn group boundaries are. */
8618 if (GET_MODE (insn) == TImode)
8621 if (GET_CODE (insn) == CLOBBER || GET_CODE (insn) == USE)
8626 insn = next_nonnote_insn (insn);
8634 /* IN_USE is a mask of the slots currently filled within the insn group.
8635 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
8636 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
8638 LEN is, of course, the length of the group in bytes. */
8641 alphaev5_next_group (rtx insn, int *pin_use, int *plen)
8648 || GET_CODE (PATTERN (insn)) == CLOBBER
8649 || GET_CODE (PATTERN (insn)) == USE)
8654 enum alphaev5_pipe pipe;
8656 pipe = alphaev5_insn_pipe (insn);
8660 /* Force complex instructions to start new groups. */
8664 /* If this is a completely unrecognized insn, its an asm.
8665 We don't know how long it is, so record length as -1 to
8666 signal a needed realignment. */
8667 if (recog_memoized (insn) < 0)
8670 len = get_attr_length (insn);
8673 /* ??? Most of the places below, we would like to abort, as
8674 it would indicate an error either in Haifa, or in the
8675 scheduling description. Unfortunately, Haifa never
8676 schedules the last instruction of the BB, so we don't
8677 have an accurate TI bit to go off. */
8679 if (in_use & EV5_E0)
8681 if (in_use & EV5_E1)
8686 in_use |= EV5_E0 | EV5_E01;
8690 if (in_use & EV5_E0)
8692 if (!(in_use & EV5_E01) || (in_use & EV5_E1))
8700 if (in_use & EV5_E1)
8706 if (in_use & EV5_FA)
8708 if (in_use & EV5_FM)
8713 in_use |= EV5_FA | EV5_FAM;
8717 if (in_use & EV5_FA)
8723 if (in_use & EV5_FM)
8736 /* Haifa doesn't do well scheduling branches. */
8737 /* ??? If this is predicted not-taken, slotting continues, except
8738 that no more IBR, FBR, or JSR insns may be slotted. */
8739 if (GET_CODE (insn) == JUMP_INSN)
8743 insn = next_nonnote_insn (insn);
8745 if (!insn || ! INSN_P (insn))
8748 /* Let Haifa tell us where it thinks insn group boundaries are. */
8749 if (GET_MODE (insn) == TImode)
8752 if (GET_CODE (insn) == CLOBBER || GET_CODE (insn) == USE)
8757 insn = next_nonnote_insn (insn);
8766 alphaev4_next_nop (int *pin_use)
8768 int in_use = *pin_use;
8771 if (!(in_use & EV4_IB0))
8776 else if ((in_use & (EV4_IBX|EV4_IB1)) == EV4_IBX)
8781 else if (TARGET_FP && !(in_use & EV4_IB1))
8794 alphaev5_next_nop (int *pin_use)
8796 int in_use = *pin_use;
8799 if (!(in_use & EV5_E1))
8804 else if (TARGET_FP && !(in_use & EV5_FA))
8809 else if (TARGET_FP && !(in_use & EV5_FM))
8821 /* The instruction group alignment main loop. */
8824 alpha_align_insns (unsigned int max_align,
8825 rtx (*next_group) (rtx, int *, int *),
8826 rtx (*next_nop) (int *))
8828 /* ALIGN is the known alignment for the insn group. */
8830 /* OFS is the offset of the current insn in the insn group. */
8832 int prev_in_use, in_use, len, ldgp;
8835 /* Let shorten branches care for assigning alignments to code labels. */
8836 shorten_branches (get_insns ());
8838 if (align_functions < 4)
8840 else if ((unsigned int) align_functions < max_align)
8841 align = align_functions;
8845 ofs = prev_in_use = 0;
8847 if (GET_CODE (i) == NOTE)
8848 i = next_nonnote_insn (i);
8850 ldgp = alpha_function_needs_gp ? 8 : 0;
8854 next = (*next_group) (i, &in_use, &len);
8856 /* When we see a label, resync alignment etc. */
8857 if (GET_CODE (i) == CODE_LABEL)
8859 unsigned int new_align = 1 << label_to_alignment (i);
8861 if (new_align >= align)
8863 align = new_align < max_align ? new_align : max_align;
8867 else if (ofs & (new_align-1))
8868 ofs = (ofs | (new_align-1)) + 1;
8873 /* Handle complex instructions special. */
8874 else if (in_use == 0)
8876 /* Asms will have length < 0. This is a signal that we have
8877 lost alignment knowledge. Assume, however, that the asm
8878 will not mis-align instructions. */
8887 /* If the known alignment is smaller than the recognized insn group,
8888 realign the output. */
8889 else if ((int) align < len)
8891 unsigned int new_log_align = len > 8 ? 4 : 3;
8894 where = prev = prev_nonnote_insn (i);
8895 if (!where || GET_CODE (where) != CODE_LABEL)
8898 /* Can't realign between a call and its gp reload. */
8899 if (! (TARGET_EXPLICIT_RELOCS
8900 && prev && GET_CODE (prev) == CALL_INSN))
8902 emit_insn_before (gen_realign (GEN_INT (new_log_align)), where);
8903 align = 1 << new_log_align;
8908 /* We may not insert padding inside the initial ldgp sequence. */
8912 /* If the group won't fit in the same INT16 as the previous,
8913 we need to add padding to keep the group together. Rather
8914 than simply leaving the insn filling to the assembler, we
8915 can make use of the knowledge of what sorts of instructions
8916 were issued in the previous group to make sure that all of
8917 the added nops are really free. */
8918 else if (ofs + len > (int) align)
8920 int nop_count = (align - ofs) / 4;
8923 /* Insert nops before labels, branches, and calls to truly merge
8924 the execution of the nops with the previous instruction group. */
8925 where = prev_nonnote_insn (i);
8928 if (GET_CODE (where) == CODE_LABEL)
8930 rtx where2 = prev_nonnote_insn (where);
8931 if (where2 && GET_CODE (where2) == JUMP_INSN)
8934 else if (GET_CODE (where) == INSN)
8941 emit_insn_before ((*next_nop)(&prev_in_use), where);
8942 while (--nop_count);
8946 ofs = (ofs + len) & (align - 1);
8947 prev_in_use = in_use;
8952 /* Machine dependent reorg pass. */
8957 if (alpha_tp != ALPHA_TP_PROG || flag_exceptions)
8958 alpha_handle_trap_shadows ();
8960 /* Due to the number of extra trapb insns, don't bother fixing up
8961 alignment when trap precision is instruction. Moreover, we can
8962 only do our job when sched2 is run. */
8963 if (optimize && !optimize_size
8964 && alpha_tp != ALPHA_TP_INSN
8965 && flag_schedule_insns_after_reload)
8967 if (alpha_cpu == PROCESSOR_EV4)
8968 alpha_align_insns (8, alphaev4_next_group, alphaev4_next_nop);
8969 else if (alpha_cpu == PROCESSOR_EV5)
8970 alpha_align_insns (16, alphaev5_next_group, alphaev5_next_nop);
8974 #if !TARGET_ABI_UNICOSMK
8981 alpha_file_start (void)
8983 #ifdef OBJECT_FORMAT_ELF
8984 /* If emitting dwarf2 debug information, we cannot generate a .file
8985 directive to start the file, as it will conflict with dwarf2out
8986 file numbers. So it's only useful when emitting mdebug output. */
8987 targetm.file_start_file_directive = (write_symbols == DBX_DEBUG);
8990 default_file_start ();
8992 fprintf (asm_out_file, "\t.verstamp %d %d\n", MS_STAMP, LS_STAMP);
8995 fputs ("\t.set noreorder\n", asm_out_file);
8996 fputs ("\t.set volatile\n", asm_out_file);
8997 if (!TARGET_ABI_OPEN_VMS)
8998 fputs ("\t.set noat\n", asm_out_file);
8999 if (TARGET_EXPLICIT_RELOCS)
9000 fputs ("\t.set nomacro\n", asm_out_file);
9001 if (TARGET_SUPPORT_ARCH | TARGET_BWX | TARGET_MAX | TARGET_FIX | TARGET_CIX)
9002 fprintf (asm_out_file,
9004 TARGET_CPU_EV6 ? "ev6"
9006 ? (TARGET_MAX ? "pca56" : TARGET_BWX ? "ev56" : "ev5")
9011 #ifdef OBJECT_FORMAT_ELF
9013 /* Switch to the section to which we should output X. The only thing
9014 special we do here is to honor small data. */
9017 alpha_elf_select_rtx_section (enum machine_mode mode, rtx x,
9018 unsigned HOST_WIDE_INT align)
9020 if (TARGET_SMALL_DATA && GET_MODE_SIZE (mode) <= g_switch_value)
9021 /* ??? Consider using mergeable sdata sections. */
9024 default_elf_select_rtx_section (mode, x, align);
9027 #endif /* OBJECT_FORMAT_ELF */
9029 /* Structure to collect function names for final output in link section. */
9030 /* Note that items marked with GTY can't be ifdef'ed out. */
9032 enum links_kind {KIND_UNUSED, KIND_LOCAL, KIND_EXTERN};
9033 enum reloc_kind {KIND_LINKAGE, KIND_CODEADDR};
9035 struct alpha_links GTY(())
9039 enum links_kind lkind;
9040 enum reloc_kind rkind;
9043 struct alpha_funcs GTY(())
9046 splay_tree GTY ((param1_is (char *), param2_is (struct alpha_links *)))
9050 static GTY ((param1_is (char *), param2_is (struct alpha_links *)))
9051 splay_tree alpha_links_tree;
9052 static GTY ((param1_is (tree), param2_is (struct alpha_funcs *)))
9053 splay_tree alpha_funcs_tree;
9055 static GTY(()) int alpha_funcs_num;
9057 #if TARGET_ABI_OPEN_VMS
9059 /* Return the VMS argument type corresponding to MODE. */
9062 alpha_arg_type (enum machine_mode mode)
9067 return TARGET_FLOAT_VAX ? FF : FS;
9069 return TARGET_FLOAT_VAX ? FD : FT;
9075 /* Return an rtx for an integer representing the VMS Argument Information
9079 alpha_arg_info_reg_val (CUMULATIVE_ARGS cum)
9081 unsigned HOST_WIDE_INT regval = cum.num_args;
9084 for (i = 0; i < 6; i++)
9085 regval |= ((int) cum.atypes[i]) << (i * 3 + 8);
9087 return GEN_INT (regval);
9090 /* Make (or fake) .linkage entry for function call.
9092 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
9094 Return an SYMBOL_REF rtx for the linkage. */
9097 alpha_need_linkage (const char *name, int is_local)
9099 splay_tree_node node;
9100 struct alpha_links *al;
9107 struct alpha_funcs *cfaf;
9109 if (!alpha_funcs_tree)
9110 alpha_funcs_tree = splay_tree_new_ggc ((splay_tree_compare_fn)
9111 splay_tree_compare_pointers);
9113 cfaf = (struct alpha_funcs *) ggc_alloc (sizeof (struct alpha_funcs));
9116 cfaf->num = ++alpha_funcs_num;
9118 splay_tree_insert (alpha_funcs_tree,
9119 (splay_tree_key) current_function_decl,
9120 (splay_tree_value) cfaf);
9123 if (alpha_links_tree)
9125 /* Is this name already defined? */
9127 node = splay_tree_lookup (alpha_links_tree, (splay_tree_key) name);
9130 al = (struct alpha_links *) node->value;
9133 /* Defined here but external assumed. */
9134 if (al->lkind == KIND_EXTERN)
9135 al->lkind = KIND_LOCAL;
9139 /* Used here but unused assumed. */
9140 if (al->lkind == KIND_UNUSED)
9141 al->lkind = KIND_LOCAL;
9147 alpha_links_tree = splay_tree_new_ggc ((splay_tree_compare_fn) strcmp);
9149 al = (struct alpha_links *) ggc_alloc (sizeof (struct alpha_links));
9150 name = ggc_strdup (name);
9152 /* Assume external if no definition. */
9153 al->lkind = (is_local ? KIND_UNUSED : KIND_EXTERN);
9155 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
9156 get_identifier (name);
9158 /* Construct a SYMBOL_REF for us to call. */
9160 size_t name_len = strlen (name);
9161 char *linksym = alloca (name_len + 6);
9163 memcpy (linksym + 1, name, name_len);
9164 memcpy (linksym + 1 + name_len, "..lk", 5);
9165 al->linkage = gen_rtx_SYMBOL_REF (Pmode,
9166 ggc_alloc_string (linksym, name_len + 5));
9169 splay_tree_insert (alpha_links_tree, (splay_tree_key) name,
9170 (splay_tree_value) al);
9176 alpha_use_linkage (rtx linkage, tree cfundecl, int lflag, int rflag)
9178 splay_tree_node cfunnode;
9179 struct alpha_funcs *cfaf;
9180 struct alpha_links *al;
9181 const char *name = XSTR (linkage, 0);
9183 cfaf = (struct alpha_funcs *) 0;
9184 al = (struct alpha_links *) 0;
9186 cfunnode = splay_tree_lookup (alpha_funcs_tree, (splay_tree_key) cfundecl);
9187 cfaf = (struct alpha_funcs *) cfunnode->value;
9191 splay_tree_node lnode;
9193 /* Is this name already defined? */
9195 lnode = splay_tree_lookup (cfaf->links, (splay_tree_key) name);
9197 al = (struct alpha_links *) lnode->value;
9200 cfaf->links = splay_tree_new_ggc ((splay_tree_compare_fn) strcmp);
9208 splay_tree_node node = 0;
9209 struct alpha_links *anl;
9214 name_len = strlen (name);
9216 al = (struct alpha_links *) ggc_alloc (sizeof (struct alpha_links));
9217 al->num = cfaf->num;
9219 node = splay_tree_lookup (alpha_links_tree, (splay_tree_key) name);
9222 anl = (struct alpha_links *) node->value;
9223 al->lkind = anl->lkind;
9226 sprintf (buf, "$%d..%s..lk", cfaf->num, name);
9227 buflen = strlen (buf);
9228 linksym = alloca (buflen + 1);
9229 memcpy (linksym, buf, buflen + 1);
9231 al->linkage = gen_rtx_SYMBOL_REF
9232 (Pmode, ggc_alloc_string (linksym, buflen + 1));
9234 splay_tree_insert (cfaf->links, (splay_tree_key) name,
9235 (splay_tree_value) al);
9239 al->rkind = KIND_CODEADDR;
9241 al->rkind = KIND_LINKAGE;
9244 return gen_rtx_MEM (Pmode, plus_constant (al->linkage, 8));
9250 alpha_write_one_linkage (splay_tree_node node, void *data)
9252 const char *const name = (const char *) node->key;
9253 struct alpha_links *link = (struct alpha_links *) node->value;
9254 FILE *stream = (FILE *) data;
9256 fprintf (stream, "$%d..%s..lk:\n", link->num, name);
9257 if (link->rkind == KIND_CODEADDR)
9259 if (link->lkind == KIND_LOCAL)
9261 /* Local and used */
9262 fprintf (stream, "\t.quad %s..en\n", name);
9266 /* External and used, request code address. */
9267 fprintf (stream, "\t.code_address %s\n", name);
9272 if (link->lkind == KIND_LOCAL)
9274 /* Local and used, build linkage pair. */
9275 fprintf (stream, "\t.quad %s..en\n", name);
9276 fprintf (stream, "\t.quad %s\n", name);
9280 /* External and used, request linkage pair. */
9281 fprintf (stream, "\t.linkage %s\n", name);
9289 alpha_write_linkage (FILE *stream, const char *funname, tree fundecl)
9291 splay_tree_node node;
9292 struct alpha_funcs *func;
9295 fprintf (stream, "\t.align 3\n");
9296 node = splay_tree_lookup (alpha_funcs_tree, (splay_tree_key) fundecl);
9297 func = (struct alpha_funcs *) node->value;
9299 fputs ("\t.name ", stream);
9300 assemble_name (stream, funname);
9301 fputs ("..na\n", stream);
9302 ASM_OUTPUT_LABEL (stream, funname);
9303 fprintf (stream, "\t.pdesc ");
9304 assemble_name (stream, funname);
9305 fprintf (stream, "..en,%s\n",
9306 alpha_procedure_type == PT_STACK ? "stack"
9307 : alpha_procedure_type == PT_REGISTER ? "reg" : "null");
9311 splay_tree_foreach (func->links, alpha_write_one_linkage, stream);
9312 /* splay_tree_delete (func->links); */
9316 /* Given a decl, a section name, and whether the decl initializer
9317 has relocs, choose attributes for the section. */
9319 #define SECTION_VMS_OVERLAY SECTION_FORGET
9320 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
9321 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
9324 vms_section_type_flags (tree decl, const char *name, int reloc)
9326 unsigned int flags = default_section_type_flags (decl, name, reloc);
9328 if (decl && DECL_ATTRIBUTES (decl)
9329 && lookup_attribute ("overlaid", DECL_ATTRIBUTES (decl)))
9330 flags |= SECTION_VMS_OVERLAY;
9331 if (decl && DECL_ATTRIBUTES (decl)
9332 && lookup_attribute ("global", DECL_ATTRIBUTES (decl)))
9333 flags |= SECTION_VMS_GLOBAL;
9334 if (decl && DECL_ATTRIBUTES (decl)
9335 && lookup_attribute ("initialize", DECL_ATTRIBUTES (decl)))
9336 flags |= SECTION_VMS_INITIALIZE;
9341 /* Switch to an arbitrary section NAME with attributes as specified
9342 by FLAGS. ALIGN specifies any known alignment requirements for
9343 the section; 0 if the default should be used. */
9346 vms_asm_named_section (const char *name, unsigned int flags)
9348 fputc ('\n', asm_out_file);
9349 fprintf (asm_out_file, ".section\t%s", name);
9351 if (flags & SECTION_VMS_OVERLAY)
9352 fprintf (asm_out_file, ",OVR");
9353 if (flags & SECTION_VMS_GLOBAL)
9354 fprintf (asm_out_file, ",GBL");
9355 if (flags & SECTION_VMS_INITIALIZE)
9356 fprintf (asm_out_file, ",NOMOD");
9357 if (flags & SECTION_DEBUG)
9358 fprintf (asm_out_file, ",NOWRT");
9360 fputc ('\n', asm_out_file);
9363 /* Record an element in the table of global constructors. SYMBOL is
9364 a SYMBOL_REF of the function to be called; PRIORITY is a number
9365 between 0 and MAX_INIT_PRIORITY.
9367 Differs from default_ctors_section_asm_out_constructor in that the
9368 width of the .ctors entry is always 64 bits, rather than the 32 bits
9369 used by a normal pointer. */
9372 vms_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9375 assemble_align (BITS_PER_WORD);
9376 assemble_integer (symbol, UNITS_PER_WORD, BITS_PER_WORD, 1);
9380 vms_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9383 assemble_align (BITS_PER_WORD);
9384 assemble_integer (symbol, UNITS_PER_WORD, BITS_PER_WORD, 1);
9389 alpha_need_linkage (const char *name ATTRIBUTE_UNUSED,
9390 int is_local ATTRIBUTE_UNUSED)
9396 alpha_use_linkage (rtx linkage ATTRIBUTE_UNUSED,
9397 tree cfundecl ATTRIBUTE_UNUSED,
9398 int lflag ATTRIBUTE_UNUSED,
9399 int rflag ATTRIBUTE_UNUSED)
9404 #endif /* TARGET_ABI_OPEN_VMS */
9406 #if TARGET_ABI_UNICOSMK
9408 /* Define the offset between two registers, one to be eliminated, and the
9409 other its replacement, at the start of a routine. */
9412 unicosmk_initial_elimination_offset (int from, int to)
9416 fixed_size = alpha_sa_size();
9417 if (fixed_size != 0)
9420 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
9422 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
9424 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
9425 return (ALPHA_ROUND (current_function_outgoing_args_size)
9426 + ALPHA_ROUND (get_frame_size()));
9427 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
9428 return (ALPHA_ROUND (fixed_size)
9429 + ALPHA_ROUND (get_frame_size()
9430 + current_function_outgoing_args_size));
9435 /* Output the module name for .ident and .end directives. We have to strip
9436 directories and add make sure that the module name starts with a letter
9440 unicosmk_output_module_name (FILE *file)
9442 const char *name = lbasename (main_input_filename);
9443 unsigned len = strlen (name);
9444 char *clean_name = alloca (len + 2);
9445 char *ptr = clean_name;
9447 /* CAM only accepts module names that start with a letter or '$'. We
9448 prefix the module name with a '$' if necessary. */
9450 if (!ISALPHA (*name))
9452 memcpy (ptr, name, len + 1);
9453 clean_symbol_name (clean_name);
9454 fputs (clean_name, file);
9457 /* Output the definition of a common variable. */
9460 unicosmk_output_common (FILE *file, const char *name, int size, int align)
9463 printf ("T3E__: common %s\n", name);
9466 fputs("\t.endp\n\n\t.psect ", file);
9467 assemble_name(file, name);
9468 fprintf(file, ",%d,common\n", floor_log2 (align / BITS_PER_UNIT));
9469 fprintf(file, "\t.byte\t0:%d\n", size);
9471 /* Mark the symbol as defined in this module. */
9472 name_tree = get_identifier (name);
9473 TREE_ASM_WRITTEN (name_tree) = 1;
9476 #define SECTION_PUBLIC SECTION_MACH_DEP
9477 #define SECTION_MAIN (SECTION_PUBLIC << 1)
9478 static int current_section_align;
9481 unicosmk_section_type_flags (tree decl, const char *name,
9482 int reloc ATTRIBUTE_UNUSED)
9484 unsigned int flags = default_section_type_flags (decl, name, reloc);
9489 if (TREE_CODE (decl) == FUNCTION_DECL)
9491 current_section_align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
9492 if (align_functions_log > current_section_align)
9493 current_section_align = align_functions_log;
9495 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)), "main"))
9496 flags |= SECTION_MAIN;
9499 current_section_align = floor_log2 (DECL_ALIGN (decl) / BITS_PER_UNIT);
9501 if (TREE_PUBLIC (decl))
9502 flags |= SECTION_PUBLIC;
9507 /* Generate a section name for decl and associate it with the
9511 unicosmk_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
9519 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
9520 name = default_strip_name_encoding (name);
9521 len = strlen (name);
9523 if (TREE_CODE (decl) == FUNCTION_DECL)
9527 /* It is essential that we prefix the section name here because
9528 otherwise the section names generated for constructors and
9529 destructors confuse collect2. */
9531 string = alloca (len + 6);
9532 sprintf (string, "code@%s", name);
9533 DECL_SECTION_NAME (decl) = build_string (len + 5, string);
9535 else if (TREE_PUBLIC (decl))
9536 DECL_SECTION_NAME (decl) = build_string (len, name);
9541 string = alloca (len + 6);
9542 sprintf (string, "data@%s", name);
9543 DECL_SECTION_NAME (decl) = build_string (len + 5, string);
9547 /* Switch to an arbitrary section NAME with attributes as specified
9548 by FLAGS. ALIGN specifies any known alignment requirements for
9549 the section; 0 if the default should be used. */
9552 unicosmk_asm_named_section (const char *name, unsigned int flags)
9556 /* Close the previous section. */
9558 fputs ("\t.endp\n\n", asm_out_file);
9560 /* Find out what kind of section we are opening. */
9562 if (flags & SECTION_MAIN)
9563 fputs ("\t.start\tmain\n", asm_out_file);
9565 if (flags & SECTION_CODE)
9567 else if (flags & SECTION_PUBLIC)
9572 if (current_section_align != 0)
9573 fprintf (asm_out_file, "\t.psect\t%s,%d,%s\n", name,
9574 current_section_align, kind);
9576 fprintf (asm_out_file, "\t.psect\t%s,%s\n", name, kind);
9580 unicosmk_insert_attributes (tree decl, tree *attr_ptr ATTRIBUTE_UNUSED)
9583 && (TREE_PUBLIC (decl) || TREE_CODE (decl) == FUNCTION_DECL))
9584 unicosmk_unique_section (decl, 0);
9587 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
9588 in code sections because .align fill unused space with zeroes. */
9591 unicosmk_output_align (FILE *file, int align)
9593 if (inside_function)
9594 fprintf (file, "\tgcc@code@align\t%d\n", align);
9596 fprintf (file, "\t.align\t%d\n", align);
9599 /* Add a case vector to the current function's list of deferred case
9600 vectors. Case vectors have to be put into a separate section because CAM
9601 does not allow data definitions in code sections. */
9604 unicosmk_defer_case_vector (rtx lab, rtx vec)
9606 struct machine_function *machine = cfun->machine;
9608 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
9609 machine->addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec,
9610 machine->addr_list);
9613 /* Output a case vector. */
9616 unicosmk_output_addr_vec (FILE *file, rtx vec)
9618 rtx lab = XEXP (vec, 0);
9619 rtx body = XEXP (vec, 1);
9620 int vlen = XVECLEN (body, 0);
9623 (*targetm.asm_out.internal_label) (file, "L", CODE_LABEL_NUMBER (lab));
9625 for (idx = 0; idx < vlen; idx++)
9627 ASM_OUTPUT_ADDR_VEC_ELT
9628 (file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
9632 /* Output current function's deferred case vectors. */
9635 unicosmk_output_deferred_case_vectors (FILE *file)
9637 struct machine_function *machine = cfun->machine;
9640 if (machine->addr_list == NULL_RTX)
9644 for (t = machine->addr_list; t; t = XEXP (t, 1))
9645 unicosmk_output_addr_vec (file, XEXP (t, 0));
9648 /* Generate the name of the SSIB section for the current function. */
9650 #define SSIB_PREFIX "__SSIB_"
9651 #define SSIB_PREFIX_LEN 7
9654 unicosmk_ssib_name (void)
9656 /* This is ok since CAM won't be able to deal with names longer than that
9659 static char name[256];
9665 x = DECL_RTL (cfun->decl);
9666 if (GET_CODE (x) != MEM)
9669 if (GET_CODE (x) != SYMBOL_REF)
9671 fnname = XSTR (x, 0);
9673 len = strlen (fnname);
9674 if (len + SSIB_PREFIX_LEN > 255)
9675 len = 255 - SSIB_PREFIX_LEN;
9677 strcpy (name, SSIB_PREFIX);
9678 strncpy (name + SSIB_PREFIX_LEN, fnname, len);
9679 name[len + SSIB_PREFIX_LEN] = 0;
9684 /* Set up the dynamic subprogram information block (DSIB) and update the
9685 frame pointer register ($15) for subroutines which have a frame. If the
9686 subroutine doesn't have a frame, simply increment $15. */
9689 unicosmk_gen_dsib (unsigned long *imaskP)
9691 if (alpha_procedure_type == PT_STACK)
9693 const char *ssib_name;
9696 /* Allocate 64 bytes for the DSIB. */
9698 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
9700 emit_insn (gen_blockage ());
9702 /* Save the return address. */
9704 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 56));
9705 set_mem_alias_set (mem, alpha_sr_alias_set);
9706 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_RA)));
9707 (*imaskP) &= ~(1UL << REG_RA);
9709 /* Save the old frame pointer. */
9711 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 48));
9712 set_mem_alias_set (mem, alpha_sr_alias_set);
9713 FRP (emit_move_insn (mem, hard_frame_pointer_rtx));
9714 (*imaskP) &= ~(1UL << HARD_FRAME_POINTER_REGNUM);
9716 emit_insn (gen_blockage ());
9718 /* Store the SSIB pointer. */
9720 ssib_name = ggc_strdup (unicosmk_ssib_name ());
9721 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 32));
9722 set_mem_alias_set (mem, alpha_sr_alias_set);
9724 FRP (emit_move_insn (gen_rtx_REG (DImode, 5),
9725 gen_rtx_SYMBOL_REF (Pmode, ssib_name)));
9726 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, 5)));
9728 /* Save the CIW index. */
9730 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 24));
9731 set_mem_alias_set (mem, alpha_sr_alias_set);
9732 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, 25)));
9734 emit_insn (gen_blockage ());
9736 /* Set the new frame pointer. */
9738 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
9739 stack_pointer_rtx, GEN_INT (64))));
9744 /* Increment the frame pointer register to indicate that we do not
9747 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
9748 hard_frame_pointer_rtx, GEN_INT (1))));
9752 /* Output the static subroutine information block for the current
9756 unicosmk_output_ssib (FILE *file, const char *fnname)
9762 struct machine_function *machine = cfun->machine;
9765 fprintf (file, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix,
9766 unicosmk_ssib_name ());
9768 /* Some required stuff and the function name length. */
9770 len = strlen (fnname);
9771 fprintf (file, "\t.quad\t^X20008%2.2X28\n", len);
9774 ??? We don't do that yet. */
9776 fputs ("\t.quad\t0\n", file);
9778 /* Function address. */
9780 fputs ("\t.quad\t", file);
9781 assemble_name (file, fnname);
9784 fputs ("\t.quad\t0\n", file);
9785 fputs ("\t.quad\t0\n", file);
9788 ??? We do it the same way Cray CC does it but this could be
9791 for( i = 0; i < len; i++ )
9792 fprintf (file, "\t.byte\t%d\n", (int)(fnname[i]));
9793 if( (len % 8) == 0 )
9794 fputs ("\t.quad\t0\n", file);
9796 fprintf (file, "\t.bits\t%d : 0\n", (8 - (len % 8))*8);
9798 /* All call information words used in the function. */
9800 for (x = machine->first_ciw; x; x = XEXP (x, 1))
9803 #if HOST_BITS_PER_WIDE_INT == 32
9804 fprintf (file, "\t.quad\t" HOST_WIDE_INT_PRINT_DOUBLE_HEX "\n",
9805 CONST_DOUBLE_HIGH (ciw), CONST_DOUBLE_LOW (ciw));
9807 fprintf (file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n", INTVAL (ciw));
9812 /* Add a call information word (CIW) to the list of the current function's
9813 CIWs and return its index.
9815 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
9818 unicosmk_add_call_info_word (rtx x)
9821 struct machine_function *machine = cfun->machine;
9823 node = gen_rtx_EXPR_LIST (VOIDmode, x, NULL_RTX);
9824 if (machine->first_ciw == NULL_RTX)
9825 machine->first_ciw = node;
9827 XEXP (machine->last_ciw, 1) = node;
9829 machine->last_ciw = node;
9830 ++machine->ciw_count;
9832 return GEN_INT (machine->ciw_count
9833 + strlen (current_function_name ())/8 + 5);
9836 static char unicosmk_section_buf[100];
9839 unicosmk_text_section (void)
9841 static int count = 0;
9842 sprintf (unicosmk_section_buf, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
9844 return unicosmk_section_buf;
9848 unicosmk_data_section (void)
9850 static int count = 1;
9851 sprintf (unicosmk_section_buf, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
9853 return unicosmk_section_buf;
9856 /* The Cray assembler doesn't accept extern declarations for symbols which
9857 are defined in the same file. We have to keep track of all global
9858 symbols which are referenced and/or defined in a source file and output
9859 extern declarations for those which are referenced but not defined at
9862 /* List of identifiers for which an extern declaration might have to be
9864 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9866 struct unicosmk_extern_list
9868 struct unicosmk_extern_list *next;
9872 static struct unicosmk_extern_list *unicosmk_extern_head = 0;
9874 /* Output extern declarations which are required for every asm file. */
9877 unicosmk_output_default_externs (FILE *file)
9879 static const char *const externs[] =
9880 { "__T3E_MISMATCH" };
9885 n = ARRAY_SIZE (externs);
9887 for (i = 0; i < n; i++)
9888 fprintf (file, "\t.extern\t%s\n", externs[i]);
9891 /* Output extern declarations for global symbols which are have been
9892 referenced but not defined. */
9895 unicosmk_output_externs (FILE *file)
9897 struct unicosmk_extern_list *p;
9898 const char *real_name;
9902 len = strlen (user_label_prefix);
9903 for (p = unicosmk_extern_head; p != 0; p = p->next)
9905 /* We have to strip the encoding and possibly remove user_label_prefix
9906 from the identifier in order to handle -fleading-underscore and
9907 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
9908 real_name = default_strip_name_encoding (p->name);
9909 if (len && p->name[0] == '*'
9910 && !memcmp (real_name, user_label_prefix, len))
9913 name_tree = get_identifier (real_name);
9914 if (! TREE_ASM_WRITTEN (name_tree))
9916 TREE_ASM_WRITTEN (name_tree) = 1;
9917 fputs ("\t.extern\t", file);
9918 assemble_name (file, p->name);
9924 /* Record an extern. */
9927 unicosmk_add_extern (const char *name)
9929 struct unicosmk_extern_list *p;
9931 p = (struct unicosmk_extern_list *)
9932 xmalloc (sizeof (struct unicosmk_extern_list));
9933 p->next = unicosmk_extern_head;
9935 unicosmk_extern_head = p;
9938 /* The Cray assembler generates incorrect code if identifiers which
9939 conflict with register names are used as instruction operands. We have
9940 to replace such identifiers with DEX expressions. */
9942 /* Structure to collect identifiers which have been replaced by DEX
9944 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9946 struct unicosmk_dex {
9947 struct unicosmk_dex *next;
9951 /* List of identifiers which have been replaced by DEX expressions. The DEX
9952 number is determined by the position in the list. */
9954 static struct unicosmk_dex *unicosmk_dex_list = NULL;
9956 /* The number of elements in the DEX list. */
9958 static int unicosmk_dex_count = 0;
9960 /* Check if NAME must be replaced by a DEX expression. */
9963 unicosmk_special_name (const char *name)
9971 if (name[0] != 'r' && name[0] != 'f' && name[0] != 'R' && name[0] != 'F')
9977 return (name[2] == '\0' || (ISDIGIT (name[2]) && name[3] == '\0'));
9980 return (name[2] == '\0'
9981 || ((name[2] == '0' || name[2] == '1') && name[3] == '\0'));
9984 return (ISDIGIT (name[1]) && name[2] == '\0');
9988 /* Return the DEX number if X must be replaced by a DEX expression and 0
9992 unicosmk_need_dex (rtx x)
9994 struct unicosmk_dex *dex;
9998 if (GET_CODE (x) != SYMBOL_REF)
10002 if (! unicosmk_special_name (name))
10005 i = unicosmk_dex_count;
10006 for (dex = unicosmk_dex_list; dex; dex = dex->next)
10008 if (! strcmp (name, dex->name))
10013 dex = (struct unicosmk_dex *) xmalloc (sizeof (struct unicosmk_dex));
10015 dex->next = unicosmk_dex_list;
10016 unicosmk_dex_list = dex;
10018 ++unicosmk_dex_count;
10019 return unicosmk_dex_count;
10022 /* Output the DEX definitions for this file. */
10025 unicosmk_output_dex (FILE *file)
10027 struct unicosmk_dex *dex;
10030 if (unicosmk_dex_list == NULL)
10033 fprintf (file, "\t.dexstart\n");
10035 i = unicosmk_dex_count;
10036 for (dex = unicosmk_dex_list; dex; dex = dex->next)
10038 fprintf (file, "\tDEX (%d) = ", i);
10039 assemble_name (file, dex->name);
10044 fprintf (file, "\t.dexend\n");
10047 /* Output text that to appear at the beginning of an assembler file. */
10050 unicosmk_file_start (void)
10054 fputs ("\t.ident\t", asm_out_file);
10055 unicosmk_output_module_name (asm_out_file);
10056 fputs ("\n\n", asm_out_file);
10058 /* The Unicos/Mk assembler uses different register names. Instead of trying
10059 to support them, we simply use micro definitions. */
10061 /* CAM has different register names: rN for the integer register N and fN
10062 for the floating-point register N. Instead of trying to use these in
10063 alpha.md, we define the symbols $N and $fN to refer to the appropriate
10066 for (i = 0; i < 32; ++i)
10067 fprintf (asm_out_file, "$%d <- r%d\n", i, i);
10069 for (i = 0; i < 32; ++i)
10070 fprintf (asm_out_file, "$f%d <- f%d\n", i, i);
10072 putc ('\n', asm_out_file);
10074 /* The .align directive fill unused space with zeroes which does not work
10075 in code sections. We define the macro 'gcc@code@align' which uses nops
10076 instead. Note that it assumes that code sections always have the
10077 biggest possible alignment since . refers to the current offset from
10078 the beginning of the section. */
10080 fputs ("\t.macro gcc@code@align n\n", asm_out_file);
10081 fputs ("gcc@n@bytes = 1 << n\n", asm_out_file);
10082 fputs ("gcc@here = . % gcc@n@bytes\n", asm_out_file);
10083 fputs ("\t.if ne, gcc@here, 0\n", asm_out_file);
10084 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", asm_out_file);
10085 fputs ("\tbis r31,r31,r31\n", asm_out_file);
10086 fputs ("\t.endr\n", asm_out_file);
10087 fputs ("\t.endif\n", asm_out_file);
10088 fputs ("\t.endm gcc@code@align\n\n", asm_out_file);
10090 /* Output extern declarations which should always be visible. */
10091 unicosmk_output_default_externs (asm_out_file);
10093 /* Open a dummy section. We always need to be inside a section for the
10094 section-switching code to work correctly.
10095 ??? This should be a module id or something like that. I still have to
10096 figure out what the rules for those are. */
10097 fputs ("\n\t.psect\t$SG00000,data\n", asm_out_file);
10100 /* Output text to appear at the end of an assembler file. This includes all
10101 pending extern declarations and DEX expressions. */
10104 unicosmk_file_end (void)
10106 fputs ("\t.endp\n\n", asm_out_file);
10108 /* Output all pending externs. */
10110 unicosmk_output_externs (asm_out_file);
10112 /* Output dex definitions used for functions whose names conflict with
10115 unicosmk_output_dex (asm_out_file);
10117 fputs ("\t.end\t", asm_out_file);
10118 unicosmk_output_module_name (asm_out_file);
10119 putc ('\n', asm_out_file);
10125 unicosmk_output_deferred_case_vectors (FILE *file ATTRIBUTE_UNUSED)
10129 unicosmk_gen_dsib (unsigned long *imaskP ATTRIBUTE_UNUSED)
10133 unicosmk_output_ssib (FILE * file ATTRIBUTE_UNUSED,
10134 const char * fnname ATTRIBUTE_UNUSED)
10138 unicosmk_add_call_info_word (rtx x ATTRIBUTE_UNUSED)
10144 unicosmk_need_dex (rtx x ATTRIBUTE_UNUSED)
10149 #endif /* TARGET_ABI_UNICOSMK */
10152 alpha_init_libfuncs (void)
10154 if (TARGET_ABI_UNICOSMK)
10156 /* Prevent gcc from generating calls to __divsi3. */
10157 set_optab_libfunc (sdiv_optab, SImode, 0);
10158 set_optab_libfunc (udiv_optab, SImode, 0);
10160 /* Use the functions provided by the system library
10161 for DImode integer division. */
10162 set_optab_libfunc (sdiv_optab, DImode, "$sldiv");
10163 set_optab_libfunc (udiv_optab, DImode, "$uldiv");
10165 else if (TARGET_ABI_OPEN_VMS)
10167 /* Use the VMS runtime library functions for division and
10169 set_optab_libfunc (sdiv_optab, SImode, "OTS$DIV_I");
10170 set_optab_libfunc (sdiv_optab, DImode, "OTS$DIV_L");
10171 set_optab_libfunc (udiv_optab, SImode, "OTS$DIV_UI");
10172 set_optab_libfunc (udiv_optab, DImode, "OTS$DIV_UL");
10173 set_optab_libfunc (smod_optab, SImode, "OTS$REM_I");
10174 set_optab_libfunc (smod_optab, DImode, "OTS$REM_L");
10175 set_optab_libfunc (umod_optab, SImode, "OTS$REM_UI");
10176 set_optab_libfunc (umod_optab, DImode, "OTS$REM_UL");
10181 /* Initialize the GCC target structure. */
10182 #if TARGET_ABI_OPEN_VMS
10183 # undef TARGET_ATTRIBUTE_TABLE
10184 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
10185 # undef TARGET_SECTION_TYPE_FLAGS
10186 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
10189 #undef TARGET_IN_SMALL_DATA_P
10190 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
10192 #if TARGET_ABI_UNICOSMK
10193 # undef TARGET_INSERT_ATTRIBUTES
10194 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
10195 # undef TARGET_SECTION_TYPE_FLAGS
10196 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
10197 # undef TARGET_ASM_UNIQUE_SECTION
10198 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
10199 # undef TARGET_ASM_GLOBALIZE_LABEL
10200 # define TARGET_ASM_GLOBALIZE_LABEL hook_void_FILEptr_constcharptr
10203 #undef TARGET_ASM_ALIGNED_HI_OP
10204 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10205 #undef TARGET_ASM_ALIGNED_DI_OP
10206 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10208 /* Default unaligned ops are provided for ELF systems. To get unaligned
10209 data for non-ELF systems, we have to turn off auto alignment. */
10210 #ifndef OBJECT_FORMAT_ELF
10211 #undef TARGET_ASM_UNALIGNED_HI_OP
10212 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
10213 #undef TARGET_ASM_UNALIGNED_SI_OP
10214 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
10215 #undef TARGET_ASM_UNALIGNED_DI_OP
10216 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
10219 #ifdef OBJECT_FORMAT_ELF
10220 #undef TARGET_ASM_SELECT_RTX_SECTION
10221 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
10224 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
10225 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
10227 #undef TARGET_INIT_LIBFUNCS
10228 #define TARGET_INIT_LIBFUNCS alpha_init_libfuncs
10230 #if TARGET_ABI_UNICOSMK
10231 #undef TARGET_ASM_FILE_START
10232 #define TARGET_ASM_FILE_START unicosmk_file_start
10233 #undef TARGET_ASM_FILE_END
10234 #define TARGET_ASM_FILE_END unicosmk_file_end
10236 #undef TARGET_ASM_FILE_START
10237 #define TARGET_ASM_FILE_START alpha_file_start
10238 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
10239 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
10242 #undef TARGET_SCHED_ADJUST_COST
10243 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
10244 #undef TARGET_SCHED_ISSUE_RATE
10245 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
10246 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
10247 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
10248 alpha_use_dfa_pipeline_interface
10249 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10250 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
10251 alpha_multipass_dfa_lookahead
10253 #undef TARGET_HAVE_TLS
10254 #define TARGET_HAVE_TLS HAVE_AS_TLS
10256 #undef TARGET_INIT_BUILTINS
10257 #define TARGET_INIT_BUILTINS alpha_init_builtins
10258 #undef TARGET_EXPAND_BUILTIN
10259 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
10261 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10262 #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
10263 #undef TARGET_CANNOT_COPY_INSN_P
10264 #define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p
10265 #undef TARGET_CANNOT_FORCE_CONST_MEM
10266 #define TARGET_CANNOT_FORCE_CONST_MEM alpha_cannot_force_const_mem
10269 #undef TARGET_ASM_OUTPUT_MI_THUNK
10270 #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf
10271 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10272 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
10275 #undef TARGET_RTX_COSTS
10276 #define TARGET_RTX_COSTS alpha_rtx_costs
10277 #undef TARGET_ADDRESS_COST
10278 #define TARGET_ADDRESS_COST hook_int_rtx_0
10280 #undef TARGET_MACHINE_DEPENDENT_REORG
10281 #define TARGET_MACHINE_DEPENDENT_REORG alpha_reorg
10283 #undef TARGET_PROMOTE_FUNCTION_ARGS
10284 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
10285 #undef TARGET_PROMOTE_FUNCTION_RETURN
10286 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
10287 #undef TARGET_PROMOTE_PROTOTYPES
10288 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_false
10289 #undef TARGET_STRUCT_VALUE_RTX
10290 #define TARGET_STRUCT_VALUE_RTX hook_rtx_tree_int_null
10291 #undef TARGET_RETURN_IN_MEMORY
10292 #define TARGET_RETURN_IN_MEMORY alpha_return_in_memory
10293 #undef TARGET_SETUP_INCOMING_VARARGS
10294 #define TARGET_SETUP_INCOMING_VARARGS alpha_setup_incoming_varargs
10295 #undef TARGET_STRICT_ARGUMENT_NAMING
10296 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
10297 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
10298 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
10299 #undef TARGET_SPLIT_COMPLEX_ARG
10300 #define TARGET_SPLIT_COMPLEX_ARG alpha_split_complex_arg
10302 #undef TARGET_BUILD_BUILTIN_VA_LIST
10303 #define TARGET_BUILD_BUILTIN_VA_LIST alpha_build_builtin_va_list
10305 struct gcc_target targetm = TARGET_INITIALIZER;
10308 #include "gt-alpha.h"