1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
37 (UNSPEC_UMK_LOAD_CIW 9)
45 (UNSPEC_TLSGD_CALL 15)
46 (UNSPEC_TLSLDM_CALL 16)
68 (UNSPECV_SETJMPR 2) ; builtin_setjmp_receiver
69 (UNSPECV_LONGJMP 3) ; builtin_longjmp
71 (UNSPECV_PSPL 5) ; prologue_stack_probe_loop
73 (UNSPECV_EHR 7) ; exception_receiver
77 (UNSPECV_PLDGP2 11) ; prologue ldgp
80 (UNSPECV_SETJMPR_ER 14) ; builtin_setjmp_receiver fragment
83 ;; Where necessary, the suffixes _le and _be are used to distinguish between
84 ;; little-endian and big-endian patterns.
86 ;; Note that the Unicos/Mk assembler does not support the following
87 ;; opcodes: mov, fmov, nop, fnop, unop.
89 ;; Processor type -- this attribute must exactly match the processor_type
90 ;; enumeration in alpha.h.
92 (define_attr "cpu" "ev4,ev5,ev6"
93 (const (symbol_ref "alpha_cpu")))
95 ;; Define an insn type attribute. This is used in function unit delay
96 ;; computations, among other purposes. For the most part, we use the names
97 ;; defined in the EV4 documentation, but add a few that we have to know about
101 "ild,fld,ldsym,ist,fst,ibr,callpal,fbr,jsr,iadd,ilog,shift,icmov,fcmov,
102 icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
103 (const_string "iadd"))
105 ;; Describe a user's asm statement.
106 (define_asm_attributes
107 [(set_attr "type" "multi")])
109 ;; Define the operand size an insn operates on. Used primarily by mul
110 ;; and div operations that have size dependent timings.
112 (define_attr "opsize" "si,di,udi"
115 ;; The TRAP attribute marks instructions that may generate traps
116 ;; (which are imprecise and may need a trapb if software completion
119 (define_attr "trap" "no,yes"
122 ;; The ROUND_SUFFIX attribute marks which instructions require a
123 ;; rounding-mode suffix. The value NONE indicates no suffix,
124 ;; the value NORMAL indicates a suffix controlled by alpha_fprm.
126 (define_attr "round_suffix" "none,normal,c"
127 (const_string "none"))
129 ;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix:
131 ;; SU accepts only /su (cmpt et al)
132 ;; SUI accepts only /sui (cvtqt and cvtqs)
133 ;; V_SV accepts /v and /sv (cvtql only)
134 ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only)
135 ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions)
137 ;; The actual suffix emitted is controlled by alpha_fptm.
139 (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
140 (const_string "none"))
142 ;; The length of an instruction sequence in bytes.
144 (define_attr "length" ""
147 ;; The USEGP attribute marks instructions that have relocations that use
150 (define_attr "usegp" "no,yes"
151 (cond [(eq_attr "type" "ldsym,jsr")
153 (eq_attr "type" "ild,fld,ist,fst")
154 (symbol_ref "alpha_find_lo_sum_using_gp(insn)")
156 (const_string "no")))
158 ;; The CANNOT_COPY attribute marks instructions with relocations that
159 ;; cannot easily be duplicated. This includes insns with gpdisp relocs
160 ;; since they have to stay in 1-1 correspondence with one another. This
161 ;; also includes jsr insns, since they must stay in correspondence with
162 ;; the immediately following gpdisp instructions.
164 (define_attr "cannot_copy" "false,true"
165 (const_string "false"))
167 ;; Include scheduling descriptions.
173 ;; First define the arithmetic insns. Note that the 32-bit forms also
176 ;; Handle 32-64 bit extension from memory to a floating point register
177 ;; specially, since this occurs frequently in int->double conversions.
179 ;; Note that while we must retain the =f case in the insn for reload's
180 ;; benefit, it should be eliminated after reload, so we should never emit
181 ;; code for that case. But we don't reject the possibility.
183 (define_expand "extendsidi2"
184 [(set (match_operand:DI 0 "register_operand" "")
185 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
189 (define_insn "*cvtlq"
190 [(set (match_operand:DI 0 "register_operand" "=f")
191 (unspec:DI [(match_operand:SF 1 "reg_or_0_operand" "fG")]
195 [(set_attr "type" "fadd")])
197 (define_insn "*extendsidi2_1"
198 [(set (match_operand:DI 0 "register_operand" "=r,r,!*f")
200 (match_operand:SI 1 "nonimmediate_operand" "r,m,m")))]
205 lds %0,%1\;cvtlq %0,%0"
206 [(set_attr "type" "iadd,ild,fld")
207 (set_attr "length" "*,*,8")])
210 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
211 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
213 [(set (match_dup 2) (match_dup 1))
214 (set (match_dup 0) (unspec:DI [(match_dup 2)] UNSPEC_CVTLQ))]
216 operands[1] = adjust_address (operands[1], SFmode, 0);
217 operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0]));
220 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
221 ;; reload when converting fp->int.
224 [(set (match_operand:SI 0 "hard_int_register_operand" "")
225 (match_operand:SI 1 "memory_operand" ""))
226 (set (match_operand:DI 2 "hard_int_register_operand" "")
227 (sign_extend:DI (match_dup 0)))]
228 "true_regnum (operands[0]) == true_regnum (operands[2])
229 || peep2_reg_dead_p (2, operands[0])"
231 (sign_extend:DI (match_dup 1)))]
234 ;; Don't say we have addsi3 if optimizing. This generates better code. We
235 ;; have the anonymous addsi3 pattern below in case combine wants to make it.
236 (define_expand "addsi3"
237 [(set (match_operand:SI 0 "register_operand" "")
238 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
239 (match_operand:SI 2 "add_operand" "")))]
243 (define_insn "*addsi_internal"
244 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
245 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
246 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
255 [(set (match_operand:SI 0 "register_operand" "")
256 (plus:SI (match_operand:SI 1 "register_operand" "")
257 (match_operand:SI 2 "const_int_operand" "")))]
258 "! add_operand (operands[2], SImode)"
259 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
260 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
262 HOST_WIDE_INT val = INTVAL (operands[2]);
263 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
264 HOST_WIDE_INT rest = val - low;
266 operands[3] = GEN_INT (rest);
267 operands[4] = GEN_INT (low);
270 (define_insn "*addsi_se"
271 [(set (match_operand:DI 0 "register_operand" "=r,r")
273 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
274 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
280 (define_insn "*addsi_se2"
281 [(set (match_operand:DI 0 "register_operand" "=r,r")
283 (subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
284 (match_operand:DI 2 "sext_add_operand" "rI,O"))
292 [(set (match_operand:DI 0 "register_operand" "")
294 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
295 (match_operand:SI 2 "const_int_operand" ""))))
296 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
297 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
298 && INTVAL (operands[2]) % 4 == 0"
299 [(set (match_dup 3) (match_dup 4))
300 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
304 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
310 operands[4] = GEN_INT (val);
311 operands[5] = GEN_INT (mult);
315 [(set (match_operand:DI 0 "register_operand" "")
317 (plus:SI (match_operator:SI 1 "comparison_operator"
318 [(match_operand 2 "" "")
319 (match_operand 3 "" "")])
320 (match_operand:SI 4 "add_operand" ""))))
321 (clobber (match_operand:DI 5 "register_operand" ""))]
323 [(set (match_dup 5) (match_dup 6))
324 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
326 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
327 operands[2], operands[3]);
328 operands[7] = gen_lowpart (SImode, operands[5]);
331 (define_insn "addvsi3"
332 [(set (match_operand:SI 0 "register_operand" "=r,r")
333 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
334 (match_operand:SI 2 "sext_add_operand" "rI,O")))
335 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
336 (sign_extend:DI (match_dup 2)))
337 (sign_extend:DI (plus:SI (match_dup 1)
345 (define_expand "adddi3"
346 [(set (match_operand:DI 0 "register_operand" "")
347 (plus:DI (match_operand:DI 1 "register_operand" "")
348 (match_operand:DI 2 "add_operand" "")))]
352 (define_insn "*adddi_er_lo16_dtp"
353 [(set (match_operand:DI 0 "register_operand" "=r")
354 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
355 (match_operand:DI 2 "dtp16_symbolic_operand" "")))]
357 "lda %0,%2(%1)\t\t!dtprel")
359 (define_insn "*adddi_er_hi32_dtp"
360 [(set (match_operand:DI 0 "register_operand" "=r")
361 (plus:DI (match_operand:DI 1 "register_operand" "r")
362 (high:DI (match_operand:DI 2 "dtp32_symbolic_operand" ""))))]
364 "ldah %0,%2(%1)\t\t!dtprelhi")
366 (define_insn "*adddi_er_lo32_dtp"
367 [(set (match_operand:DI 0 "register_operand" "=r")
368 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
369 (match_operand:DI 2 "dtp32_symbolic_operand" "")))]
371 "lda %0,%2(%1)\t\t!dtprello")
373 (define_insn "*adddi_er_lo16_tp"
374 [(set (match_operand:DI 0 "register_operand" "=r")
375 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
376 (match_operand:DI 2 "tp16_symbolic_operand" "")))]
378 "lda %0,%2(%1)\t\t!tprel")
380 (define_insn "*adddi_er_hi32_tp"
381 [(set (match_operand:DI 0 "register_operand" "=r")
382 (plus:DI (match_operand:DI 1 "register_operand" "r")
383 (high:DI (match_operand:DI 2 "tp32_symbolic_operand" ""))))]
385 "ldah %0,%2(%1)\t\t!tprelhi")
387 (define_insn "*adddi_er_lo32_tp"
388 [(set (match_operand:DI 0 "register_operand" "=r")
389 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
390 (match_operand:DI 2 "tp32_symbolic_operand" "")))]
392 "lda %0,%2(%1)\t\t!tprello")
394 (define_insn "*adddi_er_high_l"
395 [(set (match_operand:DI 0 "register_operand" "=r")
396 (plus:DI (match_operand:DI 1 "register_operand" "r")
397 (high:DI (match_operand:DI 2 "local_symbolic_operand" ""))))]
398 "TARGET_EXPLICIT_RELOCS && reload_completed"
399 "ldah %0,%2(%1)\t\t!gprelhigh"
400 [(set_attr "usegp" "yes")])
403 [(set (match_operand:DI 0 "register_operand" "")
404 (high:DI (match_operand:DI 1 "local_symbolic_operand" "")))]
405 "TARGET_EXPLICIT_RELOCS && reload_completed"
407 (plus:DI (match_dup 2) (high:DI (match_dup 1))))]
408 "operands[2] = pic_offset_table_rtx;")
410 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
411 ;; With complications like
413 ;; The NT stack unwind code can't handle a subq to adjust the stack
414 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
415 ;; the exception handling code will loop if a subq is used and an
418 ;; The 19980616 change to emit prologues as RTL also confused some
419 ;; versions of GDB, which also interprets prologues. This has been
420 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
423 ;; and the fact that the three insns schedule exactly the same, it's
424 ;; just not worth the effort.
426 (define_insn "*adddi_internal"
427 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
428 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
429 (match_operand:DI 2 "add_operand" "r,K,L")))]
436 ;; ??? Allow large constants when basing off the frame pointer or some
437 ;; virtual register that may eliminate to the frame pointer. This is
438 ;; done because register elimination offsets will change the hi/lo split,
439 ;; and if we split before reload, we will require additional instructions.
441 (define_insn "*adddi_fp_hack"
442 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
443 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r,r,r")
444 (match_operand:DI 2 "const_int_operand" "K,L,n")))]
445 "NONSTRICT_REG_OK_FP_BASE_P (operands[1])
446 && INTVAL (operands[2]) >= 0
447 /* This is the largest constant an lda+ldah pair can add, minus
448 an upper bound on the displacement between SP and AP during
449 register elimination. See INITIAL_ELIMINATION_OFFSET. */
450 && INTVAL (operands[2])
452 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
453 - ALPHA_ROUND(current_function_outgoing_args_size)
454 - (ALPHA_ROUND (get_frame_size ()
455 + max_reg_num () * UNITS_PER_WORD
456 + current_function_pretend_args_size)
457 - current_function_pretend_args_size))"
463 ;; Don't do this if we are adjusting SP since we don't want to do it
464 ;; in two steps. Don't split FP sources for the reason listed above.
466 [(set (match_operand:DI 0 "register_operand" "")
467 (plus:DI (match_operand:DI 1 "register_operand" "")
468 (match_operand:DI 2 "const_int_operand" "")))]
469 "! add_operand (operands[2], DImode)
470 && operands[0] != stack_pointer_rtx
471 && operands[1] != frame_pointer_rtx
472 && operands[1] != arg_pointer_rtx"
473 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
474 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
476 HOST_WIDE_INT val = INTVAL (operands[2]);
477 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
478 HOST_WIDE_INT rest = val - low;
480 operands[4] = GEN_INT (low);
481 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
482 operands[3] = GEN_INT (rest);
483 else if (! no_new_pseudos)
485 operands[3] = gen_reg_rtx (DImode);
486 emit_move_insn (operands[3], operands[2]);
487 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
494 (define_insn "*saddl"
495 [(set (match_operand:SI 0 "register_operand" "=r,r")
496 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
497 (match_operand:SI 2 "const48_operand" "I,I"))
498 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
504 (define_insn "*saddl_se"
505 [(set (match_operand:DI 0 "register_operand" "=r,r")
507 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
508 (match_operand:SI 2 "const48_operand" "I,I"))
509 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
516 [(set (match_operand:DI 0 "register_operand" "")
518 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
519 [(match_operand 2 "" "")
520 (match_operand 3 "" "")])
521 (match_operand:SI 4 "const48_operand" ""))
522 (match_operand:SI 5 "sext_add_operand" ""))))
523 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
525 [(set (match_dup 6) (match_dup 7))
527 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
530 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
531 operands[2], operands[3]);
532 operands[8] = gen_lowpart (SImode, operands[6]);
535 (define_insn "*saddq"
536 [(set (match_operand:DI 0 "register_operand" "=r,r")
537 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
538 (match_operand:DI 2 "const48_operand" "I,I"))
539 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
545 (define_insn "addvdi3"
546 [(set (match_operand:DI 0 "register_operand" "=r,r")
547 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
548 (match_operand:DI 2 "sext_add_operand" "rI,O")))
549 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
550 (sign_extend:TI (match_dup 2)))
551 (sign_extend:TI (plus:DI (match_dup 1)
559 (define_insn "negsi2"
560 [(set (match_operand:SI 0 "register_operand" "=r")
561 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
565 (define_insn "*negsi_se"
566 [(set (match_operand:DI 0 "register_operand" "=r")
567 (sign_extend:DI (neg:SI
568 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
572 (define_insn "negvsi2"
573 [(set (match_operand:SI 0 "register_operand" "=r")
574 (neg:SI (match_operand:SI 1 "register_operand" "r")))
575 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
576 (sign_extend:DI (neg:SI (match_dup 1))))
581 (define_insn "negdi2"
582 [(set (match_operand:DI 0 "register_operand" "=r")
583 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
587 (define_insn "negvdi2"
588 [(set (match_operand:DI 0 "register_operand" "=r")
589 (neg:DI (match_operand:DI 1 "register_operand" "r")))
590 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
591 (sign_extend:TI (neg:DI (match_dup 1))))
596 (define_expand "subsi3"
597 [(set (match_operand:SI 0 "register_operand" "")
598 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
599 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
603 (define_insn "*subsi_internal"
604 [(set (match_operand:SI 0 "register_operand" "=r")
605 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
606 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
610 (define_insn "*subsi_se"
611 [(set (match_operand:DI 0 "register_operand" "=r")
612 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
613 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
617 (define_insn "*subsi_se2"
618 [(set (match_operand:DI 0 "register_operand" "=r")
620 (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
621 (match_operand:DI 2 "reg_or_8bit_operand" "rI"))
626 (define_insn "subvsi3"
627 [(set (match_operand:SI 0 "register_operand" "=r")
628 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
629 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
630 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
631 (sign_extend:DI (match_dup 2)))
632 (sign_extend:DI (minus:SI (match_dup 1)
638 (define_insn "subdi3"
639 [(set (match_operand:DI 0 "register_operand" "=r")
640 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
641 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
645 (define_insn "*ssubl"
646 [(set (match_operand:SI 0 "register_operand" "=r")
647 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
648 (match_operand:SI 2 "const48_operand" "I"))
649 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
653 (define_insn "*ssubl_se"
654 [(set (match_operand:DI 0 "register_operand" "=r")
656 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
657 (match_operand:SI 2 "const48_operand" "I"))
658 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
662 (define_insn "*ssubq"
663 [(set (match_operand:DI 0 "register_operand" "=r")
664 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
665 (match_operand:DI 2 "const48_operand" "I"))
666 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
670 (define_insn "subvdi3"
671 [(set (match_operand:DI 0 "register_operand" "=r")
672 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
673 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
674 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
675 (sign_extend:TI (match_dup 2)))
676 (sign_extend:TI (minus:DI (match_dup 1)
682 ;; The Unicos/Mk assembler doesn't support mull.
684 (define_insn "mulsi3"
685 [(set (match_operand:SI 0 "register_operand" "=r")
686 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
687 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
688 "!TARGET_ABI_UNICOSMK"
690 [(set_attr "type" "imul")
691 (set_attr "opsize" "si")])
693 (define_insn "*mulsi_se"
694 [(set (match_operand:DI 0 "register_operand" "=r")
696 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
697 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
698 "!TARGET_ABI_UNICOSMK"
700 [(set_attr "type" "imul")
701 (set_attr "opsize" "si")])
703 (define_insn "mulvsi3"
704 [(set (match_operand:SI 0 "register_operand" "=r")
705 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
706 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
707 (trap_if (ne (mult:DI (sign_extend:DI (match_dup 1))
708 (sign_extend:DI (match_dup 2)))
709 (sign_extend:DI (mult:SI (match_dup 1)
712 "!TARGET_ABI_UNICOSMK"
714 [(set_attr "type" "imul")
715 (set_attr "opsize" "si")])
717 (define_insn "muldi3"
718 [(set (match_operand:DI 0 "register_operand" "=r")
719 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
720 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
723 [(set_attr "type" "imul")])
725 (define_insn "mulvdi3"
726 [(set (match_operand:DI 0 "register_operand" "=r")
727 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
728 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
729 (trap_if (ne (mult:TI (sign_extend:TI (match_dup 1))
730 (sign_extend:TI (match_dup 2)))
731 (sign_extend:TI (mult:DI (match_dup 1)
736 [(set_attr "type" "imul")])
738 (define_expand "umuldi3_highpart"
739 [(set (match_operand:DI 0 "register_operand" "")
742 (mult:TI (zero_extend:TI
743 (match_operand:DI 1 "register_operand" ""))
744 (match_operand:DI 2 "reg_or_8bit_operand" ""))
748 if (REG_P (operands[2]))
749 operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]);
752 (define_insn "*umuldi3_highpart_reg"
753 [(set (match_operand:DI 0 "register_operand" "=r")
756 (mult:TI (zero_extend:TI
757 (match_operand:DI 1 "register_operand" "r"))
759 (match_operand:DI 2 "register_operand" "r")))
763 [(set_attr "type" "imul")
764 (set_attr "opsize" "udi")])
766 (define_insn "*umuldi3_highpart_const"
767 [(set (match_operand:DI 0 "register_operand" "=r")
770 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
771 (match_operand:TI 2 "cint8_operand" "I"))
775 [(set_attr "type" "imul")
776 (set_attr "opsize" "udi")])
778 ;; The divide and remainder operations take their inputs from r24 and
779 ;; r25, put their output in r27, and clobber r23 and r28 on all
780 ;; systems except Unicos/Mk. On Unicos, the standard library provides
781 ;; subroutines which use the standard calling convention and work on
784 ;; ??? Force sign-extension here because some versions of OSF/1 and
785 ;; Interix/NT don't do the right thing if the inputs are not properly
786 ;; sign-extended. But Linux, for instance, does not have this
787 ;; problem. Is it worth the complication here to eliminate the sign
790 (define_expand "divsi3"
792 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
794 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
795 (parallel [(set (match_dup 5)
796 (sign_extend:DI (div:SI (match_dup 3) (match_dup 4))))
797 (clobber (reg:DI 23))
798 (clobber (reg:DI 28))])
799 (set (match_operand:SI 0 "nonimmediate_operand" "")
800 (subreg:SI (match_dup 5) 0))]
801 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
803 operands[3] = gen_reg_rtx (DImode);
804 operands[4] = gen_reg_rtx (DImode);
805 operands[5] = gen_reg_rtx (DImode);
808 (define_expand "udivsi3"
810 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
812 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
813 (parallel [(set (match_dup 5)
814 (sign_extend:DI (udiv:SI (match_dup 3) (match_dup 4))))
815 (clobber (reg:DI 23))
816 (clobber (reg:DI 28))])
817 (set (match_operand:SI 0 "nonimmediate_operand" "")
818 (subreg:SI (match_dup 5) 0))]
819 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
821 operands[3] = gen_reg_rtx (DImode);
822 operands[4] = gen_reg_rtx (DImode);
823 operands[5] = gen_reg_rtx (DImode);
826 (define_expand "modsi3"
828 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
830 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
831 (parallel [(set (match_dup 5)
832 (sign_extend:DI (mod:SI (match_dup 3) (match_dup 4))))
833 (clobber (reg:DI 23))
834 (clobber (reg:DI 28))])
835 (set (match_operand:SI 0 "nonimmediate_operand" "")
836 (subreg:SI (match_dup 5) 0))]
837 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
839 operands[3] = gen_reg_rtx (DImode);
840 operands[4] = gen_reg_rtx (DImode);
841 operands[5] = gen_reg_rtx (DImode);
844 (define_expand "umodsi3"
846 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
848 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
849 (parallel [(set (match_dup 5)
850 (sign_extend:DI (umod:SI (match_dup 3) (match_dup 4))))
851 (clobber (reg:DI 23))
852 (clobber (reg:DI 28))])
853 (set (match_operand:SI 0 "nonimmediate_operand" "")
854 (subreg:SI (match_dup 5) 0))]
855 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
857 operands[3] = gen_reg_rtx (DImode);
858 operands[4] = gen_reg_rtx (DImode);
859 operands[5] = gen_reg_rtx (DImode);
862 (define_expand "divdi3"
863 [(parallel [(set (match_operand:DI 0 "register_operand" "")
864 (div:DI (match_operand:DI 1 "register_operand" "")
865 (match_operand:DI 2 "register_operand" "")))
866 (clobber (reg:DI 23))
867 (clobber (reg:DI 28))])]
868 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
871 (define_expand "udivdi3"
872 [(parallel [(set (match_operand:DI 0 "register_operand" "")
873 (udiv:DI (match_operand:DI 1 "register_operand" "")
874 (match_operand:DI 2 "register_operand" "")))
875 (clobber (reg:DI 23))
876 (clobber (reg:DI 28))])]
877 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
880 (define_expand "moddi3"
881 [(use (match_operand:DI 0 "register_operand" ""))
882 (use (match_operand:DI 1 "register_operand" ""))
883 (use (match_operand:DI 2 "register_operand" ""))]
884 "!TARGET_ABI_OPEN_VMS"
886 if (TARGET_ABI_UNICOSMK)
887 emit_insn (gen_moddi3_umk (operands[0], operands[1], operands[2]));
889 emit_insn (gen_moddi3_dft (operands[0], operands[1], operands[2]));
893 (define_expand "moddi3_dft"
894 [(parallel [(set (match_operand:DI 0 "register_operand" "")
895 (mod:DI (match_operand:DI 1 "register_operand" "")
896 (match_operand:DI 2 "register_operand" "")))
897 (clobber (reg:DI 23))
898 (clobber (reg:DI 28))])]
899 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
902 ;; On Unicos/Mk, we do as the system's C compiler does:
903 ;; compute the quotient, multiply and subtract.
905 (define_expand "moddi3_umk"
906 [(use (match_operand:DI 0 "register_operand" ""))
907 (use (match_operand:DI 1 "register_operand" ""))
908 (use (match_operand:DI 2 "register_operand" ""))]
909 "TARGET_ABI_UNICOSMK"
911 rtx div, mul = gen_reg_rtx (DImode);
913 div = expand_binop (DImode, sdiv_optab, operands[1], operands[2],
914 NULL_RTX, 0, OPTAB_LIB);
915 div = force_reg (DImode, div);
916 emit_insn (gen_muldi3 (mul, operands[2], div));
917 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
921 (define_expand "umoddi3"
922 [(use (match_operand:DI 0 "register_operand" ""))
923 (use (match_operand:DI 1 "register_operand" ""))
924 (use (match_operand:DI 2 "register_operand" ""))]
925 "! TARGET_ABI_OPEN_VMS"
927 if (TARGET_ABI_UNICOSMK)
928 emit_insn (gen_umoddi3_umk (operands[0], operands[1], operands[2]));
930 emit_insn (gen_umoddi3_dft (operands[0], operands[1], operands[2]));
934 (define_expand "umoddi3_dft"
935 [(parallel [(set (match_operand:DI 0 "register_operand" "")
936 (umod:DI (match_operand:DI 1 "register_operand" "")
937 (match_operand:DI 2 "register_operand" "")))
938 (clobber (reg:DI 23))
939 (clobber (reg:DI 28))])]
940 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
943 (define_expand "umoddi3_umk"
944 [(use (match_operand:DI 0 "register_operand" ""))
945 (use (match_operand:DI 1 "register_operand" ""))
946 (use (match_operand:DI 2 "register_operand" ""))]
947 "TARGET_ABI_UNICOSMK"
949 rtx div, mul = gen_reg_rtx (DImode);
951 div = expand_binop (DImode, udiv_optab, operands[1], operands[2],
952 NULL_RTX, 1, OPTAB_LIB);
953 div = force_reg (DImode, div);
954 emit_insn (gen_muldi3 (mul, operands[2], div));
955 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
959 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
960 ;; expanded by the assembler.
962 (define_insn_and_split "*divmodsi_internal_er"
963 [(set (match_operand:DI 0 "register_operand" "=c")
964 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
965 [(match_operand:DI 1 "register_operand" "a")
966 (match_operand:DI 2 "register_operand" "b")])))
967 (clobber (reg:DI 23))
968 (clobber (reg:DI 28))]
969 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
971 "&& reload_completed"
972 [(parallel [(set (match_dup 0)
973 (sign_extend:DI (match_dup 3)))
976 (clobber (reg:DI 23))
977 (clobber (reg:DI 28))])]
980 switch (GET_CODE (operands[3]))
997 operands[4] = GEN_INT (alpha_next_sequence_number++);
998 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
999 gen_rtx_SYMBOL_REF (DImode, str),
1002 [(set_attr "type" "jsr")
1003 (set_attr "length" "8")])
1005 (define_insn "*divmodsi_internal_er_1"
1006 [(set (match_operand:DI 0 "register_operand" "=c")
1007 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1008 [(match_operand:DI 1 "register_operand" "a")
1009 (match_operand:DI 2 "register_operand" "b")])))
1010 (use (match_operand:DI 4 "register_operand" "c"))
1011 (use (match_operand 5 "const_int_operand" ""))
1012 (clobber (reg:DI 23))
1013 (clobber (reg:DI 28))]
1014 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1015 "jsr $23,($27),__%E3%j5"
1016 [(set_attr "type" "jsr")
1017 (set_attr "length" "4")])
1019 (define_insn "*divmodsi_internal"
1020 [(set (match_operand:DI 0 "register_operand" "=c")
1021 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1022 [(match_operand:DI 1 "register_operand" "a")
1023 (match_operand:DI 2 "register_operand" "b")])))
1024 (clobber (reg:DI 23))
1025 (clobber (reg:DI 28))]
1026 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1028 [(set_attr "type" "jsr")
1029 (set_attr "length" "8")])
1031 (define_insn_and_split "*divmoddi_internal_er"
1032 [(set (match_operand:DI 0 "register_operand" "=c")
1033 (match_operator:DI 3 "divmod_operator"
1034 [(match_operand:DI 1 "register_operand" "a")
1035 (match_operand:DI 2 "register_operand" "b")]))
1036 (clobber (reg:DI 23))
1037 (clobber (reg:DI 28))]
1038 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1040 "&& reload_completed"
1041 [(parallel [(set (match_dup 0) (match_dup 3))
1044 (clobber (reg:DI 23))
1045 (clobber (reg:DI 28))])]
1048 switch (GET_CODE (operands[3]))
1065 operands[4] = GEN_INT (alpha_next_sequence_number++);
1066 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1067 gen_rtx_SYMBOL_REF (DImode, str),
1070 [(set_attr "type" "jsr")
1071 (set_attr "length" "8")])
1073 (define_insn "*divmoddi_internal_er_1"
1074 [(set (match_operand:DI 0 "register_operand" "=c")
1075 (match_operator:DI 3 "divmod_operator"
1076 [(match_operand:DI 1 "register_operand" "a")
1077 (match_operand:DI 2 "register_operand" "b")]))
1078 (use (match_operand:DI 4 "register_operand" "c"))
1079 (use (match_operand 5 "const_int_operand" ""))
1080 (clobber (reg:DI 23))
1081 (clobber (reg:DI 28))]
1082 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1083 "jsr $23,($27),__%E3%j5"
1084 [(set_attr "type" "jsr")
1085 (set_attr "length" "4")])
1087 (define_insn "*divmoddi_internal"
1088 [(set (match_operand:DI 0 "register_operand" "=c")
1089 (match_operator:DI 3 "divmod_operator"
1090 [(match_operand:DI 1 "register_operand" "a")
1091 (match_operand:DI 2 "register_operand" "b")]))
1092 (clobber (reg:DI 23))
1093 (clobber (reg:DI 28))]
1094 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1096 [(set_attr "type" "jsr")
1097 (set_attr "length" "8")])
1099 ;; Next are the basic logical operations. These only exist in DImode.
1101 (define_insn "anddi3"
1102 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1103 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1104 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
1110 [(set_attr "type" "ilog,ilog,shift")])
1112 ;; There are times when we can split an AND into two AND insns. This occurs
1113 ;; when we can first clear any bytes and then clear anything else. For
1114 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1115 ;; Only do this when running on 64-bit host since the computations are
1116 ;; too messy otherwise.
1119 [(set (match_operand:DI 0 "register_operand" "")
1120 (and:DI (match_operand:DI 1 "register_operand" "")
1121 (match_operand:DI 2 "const_int_operand" "")))]
1122 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1123 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1124 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1126 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1127 unsigned HOST_WIDE_INT mask2 = mask1;
1130 /* For each byte that isn't all zeros, make it all ones. */
1131 for (i = 0; i < 64; i += 8)
1132 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1133 mask1 |= (HOST_WIDE_INT) 0xff << i;
1135 /* Now turn on any bits we've just turned off. */
1138 operands[3] = GEN_INT (mask1);
1139 operands[4] = GEN_INT (mask2);
1142 (define_expand "zero_extendqihi2"
1143 [(set (match_operand:HI 0 "register_operand" "")
1144 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
1148 operands[1] = force_reg (QImode, operands[1]);
1151 (define_insn "*zero_extendqihi2_bwx"
1152 [(set (match_operand:HI 0 "register_operand" "=r,r")
1153 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1158 [(set_attr "type" "ilog,ild")])
1160 (define_insn "*zero_extendqihi2_nobwx"
1161 [(set (match_operand:HI 0 "register_operand" "=r")
1162 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1165 [(set_attr "type" "ilog")])
1167 (define_expand "zero_extendqisi2"
1168 [(set (match_operand:SI 0 "register_operand" "")
1169 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1173 operands[1] = force_reg (QImode, operands[1]);
1176 (define_insn "*zero_extendqisi2_bwx"
1177 [(set (match_operand:SI 0 "register_operand" "=r,r")
1178 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1183 [(set_attr "type" "ilog,ild")])
1185 (define_insn "*zero_extendqisi2_nobwx"
1186 [(set (match_operand:SI 0 "register_operand" "=r")
1187 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1190 [(set_attr "type" "ilog")])
1192 (define_expand "zero_extendqidi2"
1193 [(set (match_operand:DI 0 "register_operand" "")
1194 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
1198 operands[1] = force_reg (QImode, operands[1]);
1201 (define_insn "*zero_extendqidi2_bwx"
1202 [(set (match_operand:DI 0 "register_operand" "=r,r")
1203 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1208 [(set_attr "type" "ilog,ild")])
1210 (define_insn "*zero_extendqidi2_nobwx"
1211 [(set (match_operand:DI 0 "register_operand" "=r")
1212 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1215 [(set_attr "type" "ilog")])
1217 (define_expand "zero_extendhisi2"
1218 [(set (match_operand:SI 0 "register_operand" "")
1219 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
1223 operands[1] = force_reg (HImode, operands[1]);
1226 (define_insn "*zero_extendhisi2_bwx"
1227 [(set (match_operand:SI 0 "register_operand" "=r,r")
1228 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1233 [(set_attr "type" "shift,ild")])
1235 (define_insn "*zero_extendhisi2_nobwx"
1236 [(set (match_operand:SI 0 "register_operand" "=r")
1237 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1240 [(set_attr "type" "shift")])
1242 (define_expand "zero_extendhidi2"
1243 [(set (match_operand:DI 0 "register_operand" "")
1244 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
1248 operands[1] = force_reg (HImode, operands[1]);
1251 (define_insn "*zero_extendhidi2_bwx"
1252 [(set (match_operand:DI 0 "register_operand" "=r,r")
1253 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1258 [(set_attr "type" "shift,ild")])
1260 (define_insn "*zero_extendhidi2_nobwx"
1261 [(set (match_operand:DI 0 "register_operand" "=r")
1262 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1265 [(set_attr "type" "shift")])
1267 (define_insn "zero_extendsidi2"
1268 [(set (match_operand:DI 0 "register_operand" "=r")
1269 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1272 [(set_attr "type" "shift")])
1274 (define_insn "andnotdi3"
1275 [(set (match_operand:DI 0 "register_operand" "=r")
1276 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1277 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1280 [(set_attr "type" "ilog")])
1282 (define_insn "iordi3"
1283 [(set (match_operand:DI 0 "register_operand" "=r,r")
1284 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1285 (match_operand:DI 2 "or_operand" "rI,N")))]
1290 [(set_attr "type" "ilog")])
1292 (define_insn "one_cmpldi2"
1293 [(set (match_operand:DI 0 "register_operand" "=r")
1294 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1297 [(set_attr "type" "ilog")])
1299 (define_insn "*iornot"
1300 [(set (match_operand:DI 0 "register_operand" "=r")
1301 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1302 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1305 [(set_attr "type" "ilog")])
1307 (define_insn "xordi3"
1308 [(set (match_operand:DI 0 "register_operand" "=r,r")
1309 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1310 (match_operand:DI 2 "or_operand" "rI,N")))]
1315 [(set_attr "type" "ilog")])
1317 (define_insn "*xornot"
1318 [(set (match_operand:DI 0 "register_operand" "=r")
1319 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1320 (match_operand:DI 2 "register_operand" "rI"))))]
1323 [(set_attr "type" "ilog")])
1325 ;; Handle FFS and related insns iff we support CIX.
1327 (define_expand "ffsdi2"
1329 (unspec:DI [(match_operand:DI 1 "register_operand" "")] UNSPEC_CTTZ))
1331 (plus:DI (match_dup 2) (const_int 1)))
1332 (set (match_operand:DI 0 "register_operand" "")
1333 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1334 (const_int 0) (match_dup 3)))]
1337 operands[2] = gen_reg_rtx (DImode);
1338 operands[3] = gen_reg_rtx (DImode);
1341 (define_insn "*cttz"
1342 [(set (match_operand:DI 0 "register_operand" "=r")
1343 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_CTTZ))]
1346 ; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
1347 ; reuse the existing type name.
1348 [(set_attr "type" "mvi")])
1350 (define_insn "clzdi2"
1351 [(set (match_operand:DI 0 "register_operand" "=r")
1352 (clz:DI (match_operand:DI 1 "register_operand" "r")))]
1355 [(set_attr "type" "mvi")])
1357 (define_insn "ctzdi2"
1358 [(set (match_operand:DI 0 "register_operand" "=r")
1359 (ctz:DI (match_operand:DI 1 "register_operand" "r")))]
1362 [(set_attr "type" "mvi")])
1364 (define_insn "popcountdi2"
1365 [(set (match_operand:DI 0 "register_operand" "=r")
1366 (popcount:DI (match_operand:DI 1 "register_operand" "r")))]
1369 [(set_attr "type" "mvi")])
1371 ;; Next come the shifts and the various extract and insert operations.
1373 (define_insn "ashldi3"
1374 [(set (match_operand:DI 0 "register_operand" "=r,r")
1375 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1376 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1379 switch (which_alternative)
1382 if (operands[2] == const1_rtx)
1383 return "addq %r1,%r1,%0";
1385 return "s%P2addq %r1,0,%0";
1387 return "sll %r1,%2,%0";
1392 [(set_attr "type" "iadd,shift")])
1394 (define_insn "*ashldi_se"
1395 [(set (match_operand:DI 0 "register_operand" "=r")
1397 (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1398 (match_operand:DI 2 "const_int_operand" "P"))
1400 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1402 if (operands[2] == const1_rtx)
1403 return "addl %r1,%r1,%0";
1405 return "s%P2addl %r1,0,%0";
1407 [(set_attr "type" "iadd")])
1409 (define_insn "lshrdi3"
1410 [(set (match_operand:DI 0 "register_operand" "=r")
1411 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1412 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1415 [(set_attr "type" "shift")])
1417 (define_insn "ashrdi3"
1418 [(set (match_operand:DI 0 "register_operand" "=r")
1419 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1420 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1423 [(set_attr "type" "shift")])
1425 (define_expand "extendqihi2"
1427 (ashift:DI (match_operand:QI 1 "some_operand" "")
1429 (set (match_operand:HI 0 "register_operand" "")
1430 (ashiftrt:DI (match_dup 2)
1436 emit_insn (gen_extendqihi2x (operands[0],
1437 force_reg (QImode, operands[1])));
1441 /* If we have an unaligned MEM, extend to DImode (which we do
1442 specially) and then copy to the result. */
1443 if (unaligned_memory_operand (operands[1], HImode))
1445 rtx temp = gen_reg_rtx (DImode);
1447 emit_insn (gen_extendqidi2 (temp, operands[1]));
1448 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1452 operands[0] = gen_lowpart (DImode, operands[0]);
1453 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1454 operands[2] = gen_reg_rtx (DImode);
1457 (define_insn "extendqidi2x"
1458 [(set (match_operand:DI 0 "register_operand" "=r")
1459 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1462 [(set_attr "type" "shift")])
1464 (define_insn "extendhidi2x"
1465 [(set (match_operand:DI 0 "register_operand" "=r")
1466 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1469 [(set_attr "type" "shift")])
1471 (define_insn "extendqisi2x"
1472 [(set (match_operand:SI 0 "register_operand" "=r")
1473 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1476 [(set_attr "type" "shift")])
1478 (define_insn "extendhisi2x"
1479 [(set (match_operand:SI 0 "register_operand" "=r")
1480 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1483 [(set_attr "type" "shift")])
1485 (define_insn "extendqihi2x"
1486 [(set (match_operand:HI 0 "register_operand" "=r")
1487 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1490 [(set_attr "type" "shift")])
1492 (define_expand "extendqisi2"
1494 (ashift:DI (match_operand:QI 1 "some_operand" "")
1496 (set (match_operand:SI 0 "register_operand" "")
1497 (ashiftrt:DI (match_dup 2)
1503 emit_insn (gen_extendqisi2x (operands[0],
1504 force_reg (QImode, operands[1])));
1508 /* If we have an unaligned MEM, extend to a DImode form of
1509 the result (which we do specially). */
1510 if (unaligned_memory_operand (operands[1], QImode))
1512 rtx temp = gen_reg_rtx (DImode);
1514 emit_insn (gen_extendqidi2 (temp, operands[1]));
1515 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1519 operands[0] = gen_lowpart (DImode, operands[0]);
1520 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1521 operands[2] = gen_reg_rtx (DImode);
1524 (define_expand "extendqidi2"
1526 (ashift:DI (match_operand:QI 1 "some_operand" "")
1528 (set (match_operand:DI 0 "register_operand" "")
1529 (ashiftrt:DI (match_dup 2)
1535 emit_insn (gen_extendqidi2x (operands[0],
1536 force_reg (QImode, operands[1])));
1540 if (unaligned_memory_operand (operands[1], QImode))
1543 = gen_unaligned_extendqidi (operands[0],
1544 get_unaligned_address (operands[1], 1));
1546 alpha_set_memflags (seq, operands[1]);
1551 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1552 operands[2] = gen_reg_rtx (DImode);
1555 (define_expand "extendhisi2"
1557 (ashift:DI (match_operand:HI 1 "some_operand" "")
1559 (set (match_operand:SI 0 "register_operand" "")
1560 (ashiftrt:DI (match_dup 2)
1566 emit_insn (gen_extendhisi2x (operands[0],
1567 force_reg (HImode, operands[1])));
1571 /* If we have an unaligned MEM, extend to a DImode form of
1572 the result (which we do specially). */
1573 if (unaligned_memory_operand (operands[1], HImode))
1575 rtx temp = gen_reg_rtx (DImode);
1577 emit_insn (gen_extendhidi2 (temp, operands[1]));
1578 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1582 operands[0] = gen_lowpart (DImode, operands[0]);
1583 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1584 operands[2] = gen_reg_rtx (DImode);
1587 (define_expand "extendhidi2"
1589 (ashift:DI (match_operand:HI 1 "some_operand" "")
1591 (set (match_operand:DI 0 "register_operand" "")
1592 (ashiftrt:DI (match_dup 2)
1598 emit_insn (gen_extendhidi2x (operands[0],
1599 force_reg (HImode, operands[1])));
1603 if (unaligned_memory_operand (operands[1], HImode))
1606 = gen_unaligned_extendhidi (operands[0],
1607 get_unaligned_address (operands[1], 2));
1609 alpha_set_memflags (seq, operands[1]);
1614 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1615 operands[2] = gen_reg_rtx (DImode);
1618 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1619 ;; as a pattern saves one instruction. The code is similar to that for
1620 ;; the unaligned loads (see below).
1622 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1623 (define_expand "unaligned_extendqidi"
1624 [(use (match_operand:QI 0 "register_operand" ""))
1625 (use (match_operand:DI 1 "address_operand" ""))]
1628 if (WORDS_BIG_ENDIAN)
1629 emit_insn (gen_unaligned_extendqidi_be (operands[0], operands[1]));
1631 emit_insn (gen_unaligned_extendqidi_le (operands[0], operands[1]));
1635 (define_expand "unaligned_extendqidi_le"
1636 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1638 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1641 (ashift:DI (match_dup 3)
1642 (minus:DI (const_int 64)
1644 (and:DI (match_dup 2) (const_int 7))
1646 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1647 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1648 "! WORDS_BIG_ENDIAN"
1650 operands[2] = gen_reg_rtx (DImode);
1651 operands[3] = gen_reg_rtx (DImode);
1652 operands[4] = gen_reg_rtx (DImode);
1655 (define_expand "unaligned_extendqidi_be"
1656 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1657 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -1)))
1659 (mem:DI (and:DI (match_dup 3)
1661 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -2)))
1663 (ashift:DI (match_dup 4)
1666 (plus:DI (match_dup 5) (const_int 1))
1669 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1670 (ashiftrt:DI (match_dup 6) (const_int 56)))]
1673 operands[2] = gen_reg_rtx (DImode);
1674 operands[3] = gen_reg_rtx (DImode);
1675 operands[4] = gen_reg_rtx (DImode);
1676 operands[5] = gen_reg_rtx (DImode);
1677 operands[6] = gen_reg_rtx (DImode);
1680 (define_expand "unaligned_extendhidi"
1681 [(use (match_operand:QI 0 "register_operand" ""))
1682 (use (match_operand:DI 1 "address_operand" ""))]
1685 operands[0] = gen_lowpart (DImode, operands[0]);
1686 emit_insn ((WORDS_BIG_ENDIAN
1687 ? gen_unaligned_extendhidi_be
1688 : gen_unaligned_extendhidi_le) (operands[0], operands[1]));
1692 (define_expand "unaligned_extendhidi_le"
1693 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1695 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1698 (ashift:DI (match_dup 3)
1699 (minus:DI (const_int 64)
1701 (and:DI (match_dup 2) (const_int 7))
1703 (set (match_operand:DI 0 "register_operand" "")
1704 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1705 "! WORDS_BIG_ENDIAN"
1707 operands[2] = gen_reg_rtx (DImode);
1708 operands[3] = gen_reg_rtx (DImode);
1709 operands[4] = gen_reg_rtx (DImode);
1712 (define_expand "unaligned_extendhidi_be"
1713 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1714 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -2)))
1716 (mem:DI (and:DI (match_dup 3)
1718 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -3)))
1720 (ashift:DI (match_dup 4)
1723 (plus:DI (match_dup 5) (const_int 1))
1726 (set (match_operand:DI 0 "register_operand" "")
1727 (ashiftrt:DI (match_dup 6) (const_int 48)))]
1730 operands[2] = gen_reg_rtx (DImode);
1731 operands[3] = gen_reg_rtx (DImode);
1732 operands[4] = gen_reg_rtx (DImode);
1733 operands[5] = gen_reg_rtx (DImode);
1734 operands[6] = gen_reg_rtx (DImode);
1737 (define_insn "*extxl_const"
1738 [(set (match_operand:DI 0 "register_operand" "=r")
1739 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1740 (match_operand:DI 2 "mode_width_operand" "n")
1741 (match_operand:DI 3 "mul8_operand" "I")))]
1743 "ext%M2l %r1,%s3,%0"
1744 [(set_attr "type" "shift")])
1746 (define_insn "extxl_le"
1747 [(set (match_operand:DI 0 "register_operand" "=r")
1748 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1749 (match_operand:DI 2 "mode_width_operand" "n")
1750 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1752 "! WORDS_BIG_ENDIAN"
1754 [(set_attr "type" "shift")])
1756 (define_insn "extxl_be"
1757 [(set (match_operand:DI 0 "register_operand" "=r")
1758 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1759 (match_operand:DI 2 "mode_width_operand" "n")
1763 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1767 [(set_attr "type" "shift")])
1769 ;; Combine has some strange notion of preserving existing undefined behavior
1770 ;; in shifts larger than a word size. So capture these patterns that it
1771 ;; should have turned into zero_extracts.
1773 (define_insn "*extxl_1_le"
1774 [(set (match_operand:DI 0 "register_operand" "=r")
1775 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1776 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1778 (match_operand:DI 3 "mode_mask_operand" "n")))]
1779 "! WORDS_BIG_ENDIAN"
1781 [(set_attr "type" "shift")])
1783 (define_insn "*extxl_1_be"
1784 [(set (match_operand:DI 0 "register_operand" "=r")
1785 (and:DI (lshiftrt:DI
1786 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1787 (minus:DI (const_int 56)
1788 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1790 (match_operand:DI 3 "mode_mask_operand" "n")))]
1793 [(set_attr "type" "shift")])
1795 (define_insn "*extql_2_le"
1796 [(set (match_operand:DI 0 "register_operand" "=r")
1797 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1798 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1800 "! WORDS_BIG_ENDIAN"
1802 [(set_attr "type" "shift")])
1804 (define_insn "*extql_2_be"
1805 [(set (match_operand:DI 0 "register_operand" "=r")
1807 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1808 (minus:DI (const_int 56)
1810 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1814 [(set_attr "type" "shift")])
1816 (define_insn "extqh_le"
1817 [(set (match_operand:DI 0 "register_operand" "=r")
1819 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1820 (minus:DI (const_int 64)
1823 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1826 "! WORDS_BIG_ENDIAN"
1828 [(set_attr "type" "shift")])
1830 (define_insn "extqh_be"
1831 [(set (match_operand:DI 0 "register_operand" "=r")
1833 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1836 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1842 [(set_attr "type" "shift")])
1844 (define_insn "extlh_le"
1845 [(set (match_operand:DI 0 "register_operand" "=r")
1847 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1848 (const_int 2147483647))
1849 (minus:DI (const_int 64)
1852 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1855 "! WORDS_BIG_ENDIAN"
1857 [(set_attr "type" "shift")])
1859 (define_insn "extlh_be"
1860 [(set (match_operand:DI 0 "register_operand" "=r")
1863 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1867 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1871 (const_int 2147483647)))]
1874 [(set_attr "type" "shift")])
1876 (define_insn "extwh_le"
1877 [(set (match_operand:DI 0 "register_operand" "=r")
1879 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1881 (minus:DI (const_int 64)
1884 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1887 "! WORDS_BIG_ENDIAN"
1889 [(set_attr "type" "shift")])
1891 (define_insn "extwh_be"
1892 [(set (match_operand:DI 0 "register_operand" "=r")
1894 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1898 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1902 (const_int 65535)))]
1905 [(set_attr "type" "shift")])
1907 ;; This converts an extXl into an extXh with an appropriate adjustment
1908 ;; to the address calculation.
1911 ;; [(set (match_operand:DI 0 "register_operand" "")
1912 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
1913 ;; (match_operand:DI 2 "mode_width_operand" "")
1914 ;; (ashift:DI (match_operand:DI 3 "" "")
1916 ;; (match_operand:DI 4 "const_int_operand" "")))
1917 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
1918 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
1919 ;; [(set (match_dup 5) (match_dup 6))
1920 ;; (set (match_dup 0)
1921 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
1922 ;; (ashift:DI (plus:DI (match_dup 5)
1928 ;; operands[6] = plus_constant (operands[3],
1929 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
1930 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
1933 (define_insn "*insbl_const"
1934 [(set (match_operand:DI 0 "register_operand" "=r")
1935 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1936 (match_operand:DI 2 "mul8_operand" "I")))]
1939 [(set_attr "type" "shift")])
1941 (define_insn "*inswl_const"
1942 [(set (match_operand:DI 0 "register_operand" "=r")
1943 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1944 (match_operand:DI 2 "mul8_operand" "I")))]
1947 [(set_attr "type" "shift")])
1949 (define_insn "*insll_const"
1950 [(set (match_operand:DI 0 "register_operand" "=r")
1951 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1952 (match_operand:DI 2 "mul8_operand" "I")))]
1955 [(set_attr "type" "shift")])
1957 (define_insn "insbl_le"
1958 [(set (match_operand:DI 0 "register_operand" "=r")
1959 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1960 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1962 "! WORDS_BIG_ENDIAN"
1964 [(set_attr "type" "shift")])
1966 (define_insn "insbl_be"
1967 [(set (match_operand:DI 0 "register_operand" "=r")
1968 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1969 (minus:DI (const_int 56)
1970 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1974 [(set_attr "type" "shift")])
1976 (define_insn "inswl_le"
1977 [(set (match_operand:DI 0 "register_operand" "=r")
1978 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1979 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1981 "! WORDS_BIG_ENDIAN"
1983 [(set_attr "type" "shift")])
1985 (define_insn "inswl_be"
1986 [(set (match_operand:DI 0 "register_operand" "=r")
1987 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1988 (minus:DI (const_int 56)
1989 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1993 [(set_attr "type" "shift")])
1995 (define_insn "insll_le"
1996 [(set (match_operand:DI 0 "register_operand" "=r")
1997 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1998 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2000 "! WORDS_BIG_ENDIAN"
2002 [(set_attr "type" "shift")])
2004 (define_insn "insll_be"
2005 [(set (match_operand:DI 0 "register_operand" "=r")
2006 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2007 (minus:DI (const_int 56)
2008 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2012 [(set_attr "type" "shift")])
2014 (define_insn "insql_le"
2015 [(set (match_operand:DI 0 "register_operand" "=r")
2016 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2017 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2019 "! WORDS_BIG_ENDIAN"
2021 [(set_attr "type" "shift")])
2023 (define_insn "insql_be"
2024 [(set (match_operand:DI 0 "register_operand" "=r")
2025 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2026 (minus:DI (const_int 56)
2027 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2031 [(set_attr "type" "shift")])
2033 ;; Combine has this sometimes habit of moving the and outside of the
2034 ;; shift, making life more interesting.
2036 (define_insn "*insxl"
2037 [(set (match_operand:DI 0 "register_operand" "=r")
2038 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
2039 (match_operand:DI 2 "mul8_operand" "I"))
2040 (match_operand:DI 3 "immediate_operand" "i")))]
2041 "HOST_BITS_PER_WIDE_INT == 64
2042 && GET_CODE (operands[3]) == CONST_INT
2043 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2044 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2045 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2046 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2047 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2048 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
2050 #if HOST_BITS_PER_WIDE_INT == 64
2051 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2052 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2053 return "insbl %1,%s2,%0";
2054 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2055 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2056 return "inswl %1,%s2,%0";
2057 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2058 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2059 return "insll %1,%s2,%0";
2063 [(set_attr "type" "shift")])
2065 ;; We do not include the insXh insns because they are complex to express
2066 ;; and it does not appear that we would ever want to generate them.
2068 ;; Since we need them for block moves, though, cop out and use unspec.
2070 (define_insn "insxh"
2071 [(set (match_operand:DI 0 "register_operand" "=r")
2072 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2073 (match_operand:DI 2 "mode_width_operand" "n")
2074 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2078 [(set_attr "type" "shift")])
2080 (define_insn "mskxl_le"
2081 [(set (match_operand:DI 0 "register_operand" "=r")
2082 (and:DI (not:DI (ashift:DI
2083 (match_operand:DI 2 "mode_mask_operand" "n")
2085 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2087 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2088 "! WORDS_BIG_ENDIAN"
2090 [(set_attr "type" "shift")])
2092 (define_insn "mskxl_be"
2093 [(set (match_operand:DI 0 "register_operand" "=r")
2094 (and:DI (not:DI (ashift:DI
2095 (match_operand:DI 2 "mode_mask_operand" "n")
2096 (minus:DI (const_int 56)
2098 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2100 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2103 [(set_attr "type" "shift")])
2105 ;; We do not include the mskXh insns because it does not appear we would
2106 ;; ever generate one.
2108 ;; Again, we do for block moves and we use unspec again.
2110 (define_insn "mskxh"
2111 [(set (match_operand:DI 0 "register_operand" "=r")
2112 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2113 (match_operand:DI 2 "mode_width_operand" "n")
2114 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2118 [(set_attr "type" "shift")])
2120 ;; Prefer AND + NE over LSHIFTRT + AND.
2122 (define_insn_and_split "*ze_and_ne"
2123 [(set (match_operand:DI 0 "register_operand" "=r")
2124 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2126 (match_operand 2 "const_int_operand" "I")))]
2127 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2129 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2131 (and:DI (match_dup 1) (match_dup 3)))
2133 (ne:DI (match_dup 0) (const_int 0)))]
2134 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
2136 ;; Floating-point operations. All the double-precision insns can extend
2137 ;; from single, so indicate that. The exception are the ones that simply
2138 ;; play with the sign bits; it's not clear what to do there.
2140 (define_insn "abssf2"
2141 [(set (match_operand:SF 0 "register_operand" "=f")
2142 (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2145 [(set_attr "type" "fcpys")])
2147 (define_insn "*nabssf2"
2148 [(set (match_operand:SF 0 "register_operand" "=f")
2149 (neg:SF (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
2152 [(set_attr "type" "fadd")])
2154 (define_insn "absdf2"
2155 [(set (match_operand:DF 0 "register_operand" "=f")
2156 (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2159 [(set_attr "type" "fcpys")])
2161 (define_insn "*nabsdf2"
2162 [(set (match_operand:DF 0 "register_operand" "=f")
2163 (neg:DF (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG"))))]
2166 [(set_attr "type" "fadd")])
2168 (define_expand "abstf2"
2169 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2170 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2171 (use (match_dup 2))])]
2172 "TARGET_HAS_XFLOATING_LIBS"
2174 #if HOST_BITS_PER_WIDE_INT >= 64
2175 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2177 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2181 (define_insn_and_split "*abstf_internal"
2182 [(set (match_operand:TF 0 "register_operand" "=r")
2183 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2184 (use (match_operand:DI 2 "register_operand" "r"))]
2185 "TARGET_HAS_XFLOATING_LIBS"
2187 "&& reload_completed"
2189 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;")
2191 (define_insn "negsf2"
2192 [(set (match_operand:SF 0 "register_operand" "=f")
2193 (neg:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2196 [(set_attr "type" "fadd")])
2198 (define_insn "negdf2"
2199 [(set (match_operand:DF 0 "register_operand" "=f")
2200 (neg:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2203 [(set_attr "type" "fadd")])
2205 (define_expand "negtf2"
2206 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2207 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2208 (use (match_dup 2))])]
2209 "TARGET_HAS_XFLOATING_LIBS"
2211 #if HOST_BITS_PER_WIDE_INT >= 64
2212 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2214 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2218 (define_insn_and_split "*negtf_internal"
2219 [(set (match_operand:TF 0 "register_operand" "=r")
2220 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2221 (use (match_operand:DI 2 "register_operand" "r"))]
2222 "TARGET_HAS_XFLOATING_LIBS"
2224 "&& reload_completed"
2226 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;")
2228 (define_insn "*addsf_ieee"
2229 [(set (match_operand:SF 0 "register_operand" "=&f")
2230 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2231 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2232 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2233 "add%,%/ %R1,%R2,%0"
2234 [(set_attr "type" "fadd")
2235 (set_attr "trap" "yes")
2236 (set_attr "round_suffix" "normal")
2237 (set_attr "trap_suffix" "u_su_sui")])
2239 (define_insn "addsf3"
2240 [(set (match_operand:SF 0 "register_operand" "=f")
2241 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2242 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2244 "add%,%/ %R1,%R2,%0"
2245 [(set_attr "type" "fadd")
2246 (set_attr "trap" "yes")
2247 (set_attr "round_suffix" "normal")
2248 (set_attr "trap_suffix" "u_su_sui")])
2250 (define_insn "*adddf_ieee"
2251 [(set (match_operand:DF 0 "register_operand" "=&f")
2252 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2253 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2254 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2255 "add%-%/ %R1,%R2,%0"
2256 [(set_attr "type" "fadd")
2257 (set_attr "trap" "yes")
2258 (set_attr "round_suffix" "normal")
2259 (set_attr "trap_suffix" "u_su_sui")])
2261 (define_insn "adddf3"
2262 [(set (match_operand:DF 0 "register_operand" "=f")
2263 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2264 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2266 "add%-%/ %R1,%R2,%0"
2267 [(set_attr "type" "fadd")
2268 (set_attr "trap" "yes")
2269 (set_attr "round_suffix" "normal")
2270 (set_attr "trap_suffix" "u_su_sui")])
2272 (define_insn "*adddf_ext1"
2273 [(set (match_operand:DF 0 "register_operand" "=f")
2274 (plus:DF (float_extend:DF
2275 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2276 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2277 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2278 "add%-%/ %R1,%R2,%0"
2279 [(set_attr "type" "fadd")
2280 (set_attr "trap" "yes")
2281 (set_attr "round_suffix" "normal")
2282 (set_attr "trap_suffix" "u_su_sui")])
2284 (define_insn "*adddf_ext2"
2285 [(set (match_operand:DF 0 "register_operand" "=f")
2286 (plus:DF (float_extend:DF
2287 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
2289 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2290 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2291 "add%-%/ %R1,%R2,%0"
2292 [(set_attr "type" "fadd")
2293 (set_attr "trap" "yes")
2294 (set_attr "round_suffix" "normal")
2295 (set_attr "trap_suffix" "u_su_sui")])
2297 (define_expand "addtf3"
2298 [(use (match_operand 0 "register_operand" ""))
2299 (use (match_operand 1 "general_operand" ""))
2300 (use (match_operand 2 "general_operand" ""))]
2301 "TARGET_HAS_XFLOATING_LIBS"
2302 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
2304 ;; Define conversion operators between DFmode and SImode, using the cvtql
2305 ;; instruction. To allow combine et al to do useful things, we keep the
2306 ;; operation as a unit until after reload, at which point we split the
2309 ;; Note that we (attempt to) only consider this optimization when the
2310 ;; ultimate destination is memory. If we will be doing further integer
2311 ;; processing, it is cheaper to do the truncation in the int regs.
2313 (define_insn "*cvtql"
2314 [(set (match_operand:SF 0 "register_operand" "=f")
2315 (unspec:SF [(match_operand:DI 1 "reg_or_0_operand" "fG")]
2319 [(set_attr "type" "fadd")
2320 (set_attr "trap" "yes")
2321 (set_attr "trap_suffix" "v_sv")])
2323 (define_insn_and_split "*fix_truncdfsi_ieee"
2324 [(set (match_operand:SI 0 "memory_operand" "=m")
2326 (match_operator:DI 4 "fix_operator"
2327 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
2328 (clobber (match_scratch:DI 2 "=&f"))
2329 (clobber (match_scratch:SF 3 "=&f"))]
2330 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2332 "&& reload_completed"
2333 [(set (match_dup 2) (match_op_dup 4 [(match_dup 1)]))
2334 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2335 (set (match_dup 5) (match_dup 3))]
2337 operands[5] = adjust_address (operands[0], SFmode, 0);
2339 [(set_attr "type" "fadd")
2340 (set_attr "trap" "yes")])
2342 (define_insn_and_split "*fix_truncdfsi_internal"
2343 [(set (match_operand:SI 0 "memory_operand" "=m")
2345 (match_operator:DI 3 "fix_operator"
2346 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
2347 (clobber (match_scratch:DI 2 "=f"))]
2348 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2350 "&& reload_completed"
2351 [(set (match_dup 2) (match_op_dup 3 [(match_dup 1)]))
2352 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2353 (set (match_dup 5) (match_dup 4))]
2355 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2]));
2356 operands[5] = adjust_address (operands[0], SFmode, 0);
2358 [(set_attr "type" "fadd")
2359 (set_attr "trap" "yes")])
2361 (define_insn "*fix_truncdfdi_ieee"
2362 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2363 (match_operator:DI 2 "fix_operator"
2364 [(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
2365 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2367 [(set_attr "type" "fadd")
2368 (set_attr "trap" "yes")
2369 (set_attr "round_suffix" "c")
2370 (set_attr "trap_suffix" "v_sv_svi")])
2372 (define_insn "*fix_truncdfdi2"
2373 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2374 (match_operator:DI 2 "fix_operator"
2375 [(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
2378 [(set_attr "type" "fadd")
2379 (set_attr "trap" "yes")
2380 (set_attr "round_suffix" "c")
2381 (set_attr "trap_suffix" "v_sv_svi")])
2383 (define_expand "fix_truncdfdi2"
2384 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2385 (fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))]
2389 (define_expand "fixuns_truncdfdi2"
2390 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2391 (unsigned_fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))]
2395 ;; Likewise between SFmode and SImode.
2397 (define_insn_and_split "*fix_truncsfsi_ieee"
2398 [(set (match_operand:SI 0 "memory_operand" "=m")
2400 (match_operator:DI 4 "fix_operator"
2402 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
2403 (clobber (match_scratch:DI 2 "=&f"))
2404 (clobber (match_scratch:SF 3 "=&f"))]
2405 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2407 "&& reload_completed"
2408 [(set (match_dup 2) (match_op_dup 4 [(float_extend:DF (match_dup 1))]))
2409 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2410 (set (match_dup 5) (match_dup 3))]
2412 operands[5] = adjust_address (operands[0], SFmode, 0);
2414 [(set_attr "type" "fadd")
2415 (set_attr "trap" "yes")])
2417 (define_insn_and_split "*fix_truncsfsi_internal"
2418 [(set (match_operand:SI 0 "memory_operand" "=m")
2420 (match_operator:DI 3 "fix_operator"
2422 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
2423 (clobber (match_scratch:DI 2 "=f"))]
2424 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2426 "&& reload_completed"
2427 [(set (match_dup 2) (match_op_dup 3 [(float_extend:DF (match_dup 1))]))
2428 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2429 (set (match_dup 5) (match_dup 4))]
2431 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2]));
2432 operands[5] = adjust_address (operands[0], SFmode, 0);
2434 [(set_attr "type" "fadd")
2435 (set_attr "trap" "yes")])
2437 (define_insn "*fix_truncsfdi_ieee"
2438 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2439 (match_operator:DI 2 "fix_operator"
2440 [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
2441 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2443 [(set_attr "type" "fadd")
2444 (set_attr "trap" "yes")
2445 (set_attr "round_suffix" "c")
2446 (set_attr "trap_suffix" "v_sv_svi")])
2448 (define_insn "*fix_truncsfdi2"
2449 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2450 (match_operator:DI 2 "fix_operator"
2451 [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
2454 [(set_attr "type" "fadd")
2455 (set_attr "trap" "yes")
2456 (set_attr "round_suffix" "c")
2457 (set_attr "trap_suffix" "v_sv_svi")])
2459 (define_expand "fix_truncsfdi2"
2460 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2461 (fix:DI (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))]
2465 (define_expand "fixuns_truncsfdi2"
2466 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2468 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))]
2472 (define_expand "fix_trunctfdi2"
2473 [(use (match_operand:DI 0 "register_operand" ""))
2474 (use (match_operand:TF 1 "general_operand" ""))]
2475 "TARGET_HAS_XFLOATING_LIBS"
2476 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2478 (define_expand "fixuns_trunctfdi2"
2479 [(use (match_operand:DI 0 "register_operand" ""))
2480 (use (match_operand:TF 1 "general_operand" ""))]
2481 "TARGET_HAS_XFLOATING_LIBS"
2482 "alpha_emit_xfloating_cvt (UNSIGNED_FIX, operands); DONE;")
2484 (define_insn "*floatdisf_ieee"
2485 [(set (match_operand:SF 0 "register_operand" "=&f")
2486 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2487 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2489 [(set_attr "type" "fadd")
2490 (set_attr "trap" "yes")
2491 (set_attr "round_suffix" "normal")
2492 (set_attr "trap_suffix" "sui")])
2494 (define_insn "floatdisf2"
2495 [(set (match_operand:SF 0 "register_operand" "=f")
2496 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2499 [(set_attr "type" "fadd")
2500 (set_attr "trap" "yes")
2501 (set_attr "round_suffix" "normal")
2502 (set_attr "trap_suffix" "sui")])
2504 (define_insn_and_split "*floatsisf2_ieee"
2505 [(set (match_operand:SF 0 "register_operand" "=&f")
2506 (float:SF (match_operand:SI 1 "memory_operand" "m")))
2507 (clobber (match_scratch:DI 2 "=&f"))
2508 (clobber (match_scratch:SF 3 "=&f"))]
2509 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2511 "&& reload_completed"
2512 [(set (match_dup 3) (match_dup 1))
2513 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2514 (set (match_dup 0) (float:SF (match_dup 2)))]
2516 operands[1] = adjust_address (operands[1], SFmode, 0);
2519 (define_insn_and_split "*floatsisf2"
2520 [(set (match_operand:SF 0 "register_operand" "=f")
2521 (float:SF (match_operand:SI 1 "memory_operand" "m")))]
2524 "&& reload_completed"
2525 [(set (match_dup 0) (match_dup 1))
2526 (set (match_dup 2) (unspec:DI [(match_dup 0)] UNSPEC_CVTLQ))
2527 (set (match_dup 0) (float:SF (match_dup 2)))]
2529 operands[1] = adjust_address (operands[1], SFmode, 0);
2530 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));
2533 (define_insn "*floatdidf_ieee"
2534 [(set (match_operand:DF 0 "register_operand" "=&f")
2535 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2536 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2538 [(set_attr "type" "fadd")
2539 (set_attr "trap" "yes")
2540 (set_attr "round_suffix" "normal")
2541 (set_attr "trap_suffix" "sui")])
2543 (define_insn "floatdidf2"
2544 [(set (match_operand:DF 0 "register_operand" "=f")
2545 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2548 [(set_attr "type" "fadd")
2549 (set_attr "trap" "yes")
2550 (set_attr "round_suffix" "normal")
2551 (set_attr "trap_suffix" "sui")])
2553 (define_insn_and_split "*floatsidf2_ieee"
2554 [(set (match_operand:DF 0 "register_operand" "=&f")
2555 (float:DF (match_operand:SI 1 "memory_operand" "m")))
2556 (clobber (match_scratch:DI 2 "=&f"))
2557 (clobber (match_scratch:SF 3 "=&f"))]
2558 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2560 "&& reload_completed"
2561 [(set (match_dup 3) (match_dup 1))
2562 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2563 (set (match_dup 0) (float:DF (match_dup 2)))]
2565 operands[1] = adjust_address (operands[1], SFmode, 0);
2568 (define_insn_and_split "*floatsidf2"
2569 [(set (match_operand:DF 0 "register_operand" "=f")
2570 (float:DF (match_operand:SI 1 "memory_operand" "m")))]
2573 "&& reload_completed"
2574 [(set (match_dup 3) (match_dup 1))
2575 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2576 (set (match_dup 0) (float:DF (match_dup 2)))]
2578 operands[1] = adjust_address (operands[1], SFmode, 0);
2579 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));
2580 operands[3] = gen_rtx_REG (SFmode, REGNO (operands[0]));
2583 (define_expand "floatditf2"
2584 [(use (match_operand:TF 0 "register_operand" ""))
2585 (use (match_operand:DI 1 "general_operand" ""))]
2586 "TARGET_HAS_XFLOATING_LIBS"
2587 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2589 (define_expand "floatunsdisf2"
2590 [(use (match_operand:SF 0 "register_operand" ""))
2591 (use (match_operand:DI 1 "register_operand" ""))]
2593 "alpha_emit_floatuns (operands); DONE;")
2595 (define_expand "floatunsdidf2"
2596 [(use (match_operand:DF 0 "register_operand" ""))
2597 (use (match_operand:DI 1 "register_operand" ""))]
2599 "alpha_emit_floatuns (operands); DONE;")
2601 (define_expand "floatunsditf2"
2602 [(use (match_operand:TF 0 "register_operand" ""))
2603 (use (match_operand:DI 1 "general_operand" ""))]
2604 "TARGET_HAS_XFLOATING_LIBS"
2605 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2607 (define_expand "extendsfdf2"
2608 [(set (match_operand:DF 0 "register_operand" "")
2609 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2612 if (alpha_fptm >= ALPHA_FPTM_SU)
2613 operands[1] = force_reg (SFmode, operands[1]);
2616 ;; The Unicos/Mk assembler doesn't support cvtst, but we've already
2617 ;; asserted that alpha_fptm == ALPHA_FPTM_N.
2619 (define_insn "*extendsfdf2_ieee"
2620 [(set (match_operand:DF 0 "register_operand" "=&f")
2621 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2622 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2624 [(set_attr "type" "fadd")
2625 (set_attr "trap" "yes")])
2627 (define_insn "*extendsfdf2_internal"
2628 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2629 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2630 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2635 [(set_attr "type" "fcpys,fld,fst")])
2637 (define_expand "extendsftf2"
2638 [(use (match_operand:TF 0 "register_operand" ""))
2639 (use (match_operand:SF 1 "general_operand" ""))]
2640 "TARGET_HAS_XFLOATING_LIBS"
2642 rtx tmp = gen_reg_rtx (DFmode);
2643 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2644 emit_insn (gen_extenddftf2 (operands[0], tmp));
2648 (define_expand "extenddftf2"
2649 [(use (match_operand:TF 0 "register_operand" ""))
2650 (use (match_operand:DF 1 "general_operand" ""))]
2651 "TARGET_HAS_XFLOATING_LIBS"
2652 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2654 (define_insn "*truncdfsf2_ieee"
2655 [(set (match_operand:SF 0 "register_operand" "=&f")
2656 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2657 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2659 [(set_attr "type" "fadd")
2660 (set_attr "trap" "yes")
2661 (set_attr "round_suffix" "normal")
2662 (set_attr "trap_suffix" "u_su_sui")])
2664 (define_insn "truncdfsf2"
2665 [(set (match_operand:SF 0 "register_operand" "=f")
2666 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2669 [(set_attr "type" "fadd")
2670 (set_attr "trap" "yes")
2671 (set_attr "round_suffix" "normal")
2672 (set_attr "trap_suffix" "u_su_sui")])
2674 (define_expand "trunctfdf2"
2675 [(use (match_operand:DF 0 "register_operand" ""))
2676 (use (match_operand:TF 1 "general_operand" ""))]
2677 "TARGET_HAS_XFLOATING_LIBS"
2678 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2680 (define_expand "trunctfsf2"
2681 [(use (match_operand:SF 0 "register_operand" ""))
2682 (use (match_operand:TF 1 "general_operand" ""))]
2683 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2685 rtx tmpf, sticky, arg, lo, hi;
2687 tmpf = gen_reg_rtx (DFmode);
2688 sticky = gen_reg_rtx (DImode);
2689 arg = copy_to_mode_reg (TFmode, operands[1]);
2690 lo = gen_lowpart (DImode, arg);
2691 hi = gen_highpart (DImode, arg);
2693 /* Convert the low word of the TFmode value into a sticky rounding bit,
2694 then or it into the low bit of the high word. This leaves the sticky
2695 bit at bit 48 of the fraction, which is representable in DFmode,
2696 which prevents rounding error in the final conversion to SFmode. */
2698 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2699 gen_rtx_NE (DImode, lo, const0_rtx)));
2700 emit_insn (gen_iordi3 (hi, hi, sticky));
2701 emit_insn (gen_trunctfdf2 (tmpf, arg));
2702 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2706 (define_insn "*divsf3_ieee"
2707 [(set (match_operand:SF 0 "register_operand" "=&f")
2708 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2709 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2710 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2711 "div%,%/ %R1,%R2,%0"
2712 [(set_attr "type" "fdiv")
2713 (set_attr "opsize" "si")
2714 (set_attr "trap" "yes")
2715 (set_attr "round_suffix" "normal")
2716 (set_attr "trap_suffix" "u_su_sui")])
2718 (define_insn "divsf3"
2719 [(set (match_operand:SF 0 "register_operand" "=f")
2720 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2721 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2723 "div%,%/ %R1,%R2,%0"
2724 [(set_attr "type" "fdiv")
2725 (set_attr "opsize" "si")
2726 (set_attr "trap" "yes")
2727 (set_attr "round_suffix" "normal")
2728 (set_attr "trap_suffix" "u_su_sui")])
2730 (define_insn "*divdf3_ieee"
2731 [(set (match_operand:DF 0 "register_operand" "=&f")
2732 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2733 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2734 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2735 "div%-%/ %R1,%R2,%0"
2736 [(set_attr "type" "fdiv")
2737 (set_attr "trap" "yes")
2738 (set_attr "round_suffix" "normal")
2739 (set_attr "trap_suffix" "u_su_sui")])
2741 (define_insn "divdf3"
2742 [(set (match_operand:DF 0 "register_operand" "=f")
2743 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2744 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2746 "div%-%/ %R1,%R2,%0"
2747 [(set_attr "type" "fdiv")
2748 (set_attr "trap" "yes")
2749 (set_attr "round_suffix" "normal")
2750 (set_attr "trap_suffix" "u_su_sui")])
2752 (define_insn "*divdf_ext1"
2753 [(set (match_operand:DF 0 "register_operand" "=f")
2754 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2755 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2756 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2757 "div%-%/ %R1,%R2,%0"
2758 [(set_attr "type" "fdiv")
2759 (set_attr "trap" "yes")
2760 (set_attr "round_suffix" "normal")
2761 (set_attr "trap_suffix" "u_su_sui")])
2763 (define_insn "*divdf_ext2"
2764 [(set (match_operand:DF 0 "register_operand" "=f")
2765 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2767 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2768 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2769 "div%-%/ %R1,%R2,%0"
2770 [(set_attr "type" "fdiv")
2771 (set_attr "trap" "yes")
2772 (set_attr "round_suffix" "normal")
2773 (set_attr "trap_suffix" "u_su_sui")])
2775 (define_insn "*divdf_ext3"
2776 [(set (match_operand:DF 0 "register_operand" "=f")
2777 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2778 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2779 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2780 "div%-%/ %R1,%R2,%0"
2781 [(set_attr "type" "fdiv")
2782 (set_attr "trap" "yes")
2783 (set_attr "round_suffix" "normal")
2784 (set_attr "trap_suffix" "u_su_sui")])
2786 (define_expand "divtf3"
2787 [(use (match_operand 0 "register_operand" ""))
2788 (use (match_operand 1 "general_operand" ""))
2789 (use (match_operand 2 "general_operand" ""))]
2790 "TARGET_HAS_XFLOATING_LIBS"
2791 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2793 (define_insn "*mulsf3_ieee"
2794 [(set (match_operand:SF 0 "register_operand" "=&f")
2795 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2796 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2797 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2798 "mul%,%/ %R1,%R2,%0"
2799 [(set_attr "type" "fmul")
2800 (set_attr "trap" "yes")
2801 (set_attr "round_suffix" "normal")
2802 (set_attr "trap_suffix" "u_su_sui")])
2804 (define_insn "mulsf3"
2805 [(set (match_operand:SF 0 "register_operand" "=f")
2806 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2807 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2809 "mul%,%/ %R1,%R2,%0"
2810 [(set_attr "type" "fmul")
2811 (set_attr "trap" "yes")
2812 (set_attr "round_suffix" "normal")
2813 (set_attr "trap_suffix" "u_su_sui")])
2815 (define_insn "*muldf3_ieee"
2816 [(set (match_operand:DF 0 "register_operand" "=&f")
2817 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2818 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2819 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2820 "mul%-%/ %R1,%R2,%0"
2821 [(set_attr "type" "fmul")
2822 (set_attr "trap" "yes")
2823 (set_attr "round_suffix" "normal")
2824 (set_attr "trap_suffix" "u_su_sui")])
2826 (define_insn "muldf3"
2827 [(set (match_operand:DF 0 "register_operand" "=f")
2828 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2829 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2831 "mul%-%/ %R1,%R2,%0"
2832 [(set_attr "type" "fmul")
2833 (set_attr "trap" "yes")
2834 (set_attr "round_suffix" "normal")
2835 (set_attr "trap_suffix" "u_su_sui")])
2837 (define_insn "*muldf_ext1"
2838 [(set (match_operand:DF 0 "register_operand" "=f")
2839 (mult:DF (float_extend:DF
2840 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2841 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2842 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2843 "mul%-%/ %R1,%R2,%0"
2844 [(set_attr "type" "fmul")
2845 (set_attr "trap" "yes")
2846 (set_attr "round_suffix" "normal")
2847 (set_attr "trap_suffix" "u_su_sui")])
2849 (define_insn "*muldf_ext2"
2850 [(set (match_operand:DF 0 "register_operand" "=f")
2851 (mult:DF (float_extend:DF
2852 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
2854 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2855 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2856 "mul%-%/ %R1,%R2,%0"
2857 [(set_attr "type" "fmul")
2858 (set_attr "trap" "yes")
2859 (set_attr "round_suffix" "normal")
2860 (set_attr "trap_suffix" "u_su_sui")])
2862 (define_expand "multf3"
2863 [(use (match_operand 0 "register_operand" ""))
2864 (use (match_operand 1 "general_operand" ""))
2865 (use (match_operand 2 "general_operand" ""))]
2866 "TARGET_HAS_XFLOATING_LIBS"
2867 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
2869 (define_insn "*subsf3_ieee"
2870 [(set (match_operand:SF 0 "register_operand" "=&f")
2871 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2872 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2873 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2874 "sub%,%/ %R1,%R2,%0"
2875 [(set_attr "type" "fadd")
2876 (set_attr "trap" "yes")
2877 (set_attr "round_suffix" "normal")
2878 (set_attr "trap_suffix" "u_su_sui")])
2880 (define_insn "subsf3"
2881 [(set (match_operand:SF 0 "register_operand" "=f")
2882 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2883 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2885 "sub%,%/ %R1,%R2,%0"
2886 [(set_attr "type" "fadd")
2887 (set_attr "trap" "yes")
2888 (set_attr "round_suffix" "normal")
2889 (set_attr "trap_suffix" "u_su_sui")])
2891 (define_insn "*subdf3_ieee"
2892 [(set (match_operand:DF 0 "register_operand" "=&f")
2893 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2894 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2895 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2896 "sub%-%/ %R1,%R2,%0"
2897 [(set_attr "type" "fadd")
2898 (set_attr "trap" "yes")
2899 (set_attr "round_suffix" "normal")
2900 (set_attr "trap_suffix" "u_su_sui")])
2902 (define_insn "subdf3"
2903 [(set (match_operand:DF 0 "register_operand" "=f")
2904 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2905 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2907 "sub%-%/ %R1,%R2,%0"
2908 [(set_attr "type" "fadd")
2909 (set_attr "trap" "yes")
2910 (set_attr "round_suffix" "normal")
2911 (set_attr "trap_suffix" "u_su_sui")])
2913 (define_insn "*subdf_ext1"
2914 [(set (match_operand:DF 0 "register_operand" "=f")
2915 (minus:DF (float_extend:DF
2916 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2917 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2918 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2919 "sub%-%/ %R1,%R2,%0"
2920 [(set_attr "type" "fadd")
2921 (set_attr "trap" "yes")
2922 (set_attr "round_suffix" "normal")
2923 (set_attr "trap_suffix" "u_su_sui")])
2925 (define_insn "*subdf_ext2"
2926 [(set (match_operand:DF 0 "register_operand" "=f")
2927 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2929 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2930 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2931 "sub%-%/ %R1,%R2,%0"
2932 [(set_attr "type" "fadd")
2933 (set_attr "trap" "yes")
2934 (set_attr "round_suffix" "normal")
2935 (set_attr "trap_suffix" "u_su_sui")])
2937 (define_insn "*subdf_ext3"
2938 [(set (match_operand:DF 0 "register_operand" "=f")
2939 (minus:DF (float_extend:DF
2940 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2942 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2943 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2944 "sub%-%/ %R1,%R2,%0"
2945 [(set_attr "type" "fadd")
2946 (set_attr "trap" "yes")
2947 (set_attr "round_suffix" "normal")
2948 (set_attr "trap_suffix" "u_su_sui")])
2950 (define_expand "subtf3"
2951 [(use (match_operand 0 "register_operand" ""))
2952 (use (match_operand 1 "general_operand" ""))
2953 (use (match_operand 2 "general_operand" ""))]
2954 "TARGET_HAS_XFLOATING_LIBS"
2955 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
2957 (define_insn "*sqrtsf2_ieee"
2958 [(set (match_operand:SF 0 "register_operand" "=&f")
2959 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2960 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2962 [(set_attr "type" "fsqrt")
2963 (set_attr "opsize" "si")
2964 (set_attr "trap" "yes")
2965 (set_attr "round_suffix" "normal")
2966 (set_attr "trap_suffix" "u_su_sui")])
2968 (define_insn "sqrtsf2"
2969 [(set (match_operand:SF 0 "register_operand" "=f")
2970 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2971 "TARGET_FP && TARGET_FIX"
2973 [(set_attr "type" "fsqrt")
2974 (set_attr "opsize" "si")
2975 (set_attr "trap" "yes")
2976 (set_attr "round_suffix" "normal")
2977 (set_attr "trap_suffix" "u_su_sui")])
2979 (define_insn "*sqrtdf2_ieee"
2980 [(set (match_operand:DF 0 "register_operand" "=&f")
2981 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2982 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2984 [(set_attr "type" "fsqrt")
2985 (set_attr "trap" "yes")
2986 (set_attr "round_suffix" "normal")
2987 (set_attr "trap_suffix" "u_su_sui")])
2989 (define_insn "sqrtdf2"
2990 [(set (match_operand:DF 0 "register_operand" "=f")
2991 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2992 "TARGET_FP && TARGET_FIX"
2994 [(set_attr "type" "fsqrt")
2995 (set_attr "trap" "yes")
2996 (set_attr "round_suffix" "normal")
2997 (set_attr "trap_suffix" "u_su_sui")])
2999 ;; Next are all the integer comparisons, and conditional moves and branches
3000 ;; and some of the related define_expand's and define_split's.
3002 (define_insn "*setcc_internal"
3003 [(set (match_operand 0 "register_operand" "=r")
3004 (match_operator 1 "alpha_comparison_operator"
3005 [(match_operand:DI 2 "register_operand" "r")
3006 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
3007 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3008 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3009 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3011 [(set_attr "type" "icmp")])
3013 ;; Yes, we can technically support reg_or_8bit_operand in operand 2,
3014 ;; but that's non-canonical rtl and allowing that causes inefficiencies
3016 (define_insn "*setcc_swapped_internal"
3017 [(set (match_operand 0 "register_operand" "=r")
3018 (match_operator 1 "alpha_swapped_comparison_operator"
3019 [(match_operand:DI 2 "register_operand" "r")
3020 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
3021 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3022 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3023 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3025 [(set_attr "type" "icmp")])
3027 ;; Use match_operator rather than ne directly so that we can match
3028 ;; multiple integer modes.
3029 (define_insn "*setne_internal"
3030 [(set (match_operand 0 "register_operand" "=r")
3031 (match_operator 1 "signed_comparison_operator"
3032 [(match_operand:DI 2 "register_operand" "r")
3034 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3035 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3036 && GET_CODE (operands[1]) == NE
3037 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3039 [(set_attr "type" "icmp")])
3041 ;; The mode folding trick can't be used with const_int operands, since
3042 ;; reload needs to know the proper mode.
3044 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
3045 ;; in order to create more pairs of constants. As long as we're allowing
3046 ;; two constants at the same time, and will have to reload one of them...
3048 (define_insn "*movqicc_internal"
3049 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
3051 (match_operator 2 "signed_comparison_operator"
3052 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3053 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3054 (match_operand:QI 1 "add_operand" "rI,0,rI,0")
3055 (match_operand:QI 5 "add_operand" "0,rI,0,rI")))]
3056 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3062 [(set_attr "type" "icmov")])
3064 (define_insn "*movhicc_internal"
3065 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
3067 (match_operator 2 "signed_comparison_operator"
3068 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3069 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3070 (match_operand:HI 1 "add_operand" "rI,0,rI,0")
3071 (match_operand:HI 5 "add_operand" "0,rI,0,rI")))]
3072 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3078 [(set_attr "type" "icmov")])
3080 (define_insn "*movsicc_internal"
3081 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
3083 (match_operator 2 "signed_comparison_operator"
3084 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3085 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3086 (match_operand:SI 1 "add_operand" "rI,0,rI,0")
3087 (match_operand:SI 5 "add_operand" "0,rI,0,rI")))]
3088 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3094 [(set_attr "type" "icmov")])
3096 (define_insn "*movdicc_internal"
3097 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
3099 (match_operator 2 "signed_comparison_operator"
3100 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3101 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3102 (match_operand:DI 1 "add_operand" "rI,0,rI,0")
3103 (match_operand:DI 5 "add_operand" "0,rI,0,rI")))]
3104 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3110 [(set_attr "type" "icmov")])
3112 (define_insn "*movqicc_lbc"
3113 [(set (match_operand:QI 0 "register_operand" "=r,r")
3115 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3119 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3120 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3125 [(set_attr "type" "icmov")])
3127 (define_insn "*movhicc_lbc"
3128 [(set (match_operand:HI 0 "register_operand" "=r,r")
3130 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3134 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3135 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3140 [(set_attr "type" "icmov")])
3142 (define_insn "*movsicc_lbc"
3143 [(set (match_operand:SI 0 "register_operand" "=r,r")
3145 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3149 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3150 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3155 [(set_attr "type" "icmov")])
3157 (define_insn "*movdicc_lbc"
3158 [(set (match_operand:DI 0 "register_operand" "=r,r")
3160 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3164 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3165 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3170 [(set_attr "type" "icmov")])
3172 (define_insn "*movqicc_lbs"
3173 [(set (match_operand:QI 0 "register_operand" "=r,r")
3175 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3179 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3180 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3185 [(set_attr "type" "icmov")])
3187 (define_insn "*movhicc_lbs"
3188 [(set (match_operand:HI 0 "register_operand" "=r,r")
3190 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3194 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3195 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3200 [(set_attr "type" "icmov")])
3202 (define_insn "*movsicc_lbs"
3203 [(set (match_operand:SI 0 "register_operand" "=r,r")
3205 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3209 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3210 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3215 [(set_attr "type" "icmov")])
3217 (define_insn "*movdicc_lbs"
3218 [(set (match_operand:DI 0 "register_operand" "=r,r")
3220 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3224 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3225 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3230 [(set_attr "type" "icmov")])
3232 ;; For ABS, we have two choices, depending on whether the input and output
3233 ;; registers are the same or not.
3234 (define_expand "absdi2"
3235 [(set (match_operand:DI 0 "register_operand" "")
3236 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3239 if (rtx_equal_p (operands[0], operands[1]))
3240 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
3242 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
3246 (define_expand "absdi2_same"
3247 [(set (match_operand:DI 1 "register_operand" "")
3248 (neg:DI (match_operand:DI 0 "register_operand" "")))
3250 (if_then_else:DI (ge (match_dup 0) (const_int 0))
3256 (define_expand "absdi2_diff"
3257 [(set (match_operand:DI 0 "register_operand" "")
3258 (neg:DI (match_operand:DI 1 "register_operand" "")))
3260 (if_then_else:DI (lt (match_dup 1) (const_int 0))
3267 [(set (match_operand:DI 0 "register_operand" "")
3268 (abs:DI (match_dup 0)))
3269 (clobber (match_operand:DI 1 "register_operand" ""))]
3271 [(set (match_dup 1) (neg:DI (match_dup 0)))
3272 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
3273 (match_dup 0) (match_dup 1)))]
3277 [(set (match_operand:DI 0 "register_operand" "")
3278 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3279 "! rtx_equal_p (operands[0], operands[1])"
3280 [(set (match_dup 0) (neg:DI (match_dup 1)))
3281 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
3282 (match_dup 0) (match_dup 1)))]
3286 [(set (match_operand:DI 0 "register_operand" "")
3287 (neg:DI (abs:DI (match_dup 0))))
3288 (clobber (match_operand:DI 1 "register_operand" ""))]
3290 [(set (match_dup 1) (neg:DI (match_dup 0)))
3291 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
3292 (match_dup 0) (match_dup 1)))]
3296 [(set (match_operand:DI 0 "register_operand" "")
3297 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
3298 "! rtx_equal_p (operands[0], operands[1])"
3299 [(set (match_dup 0) (neg:DI (match_dup 1)))
3300 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
3301 (match_dup 0) (match_dup 1)))]
3304 (define_insn "sminqi3"
3305 [(set (match_operand:QI 0 "register_operand" "=r")
3306 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3307 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3310 [(set_attr "type" "mvi")])
3312 (define_insn "uminqi3"
3313 [(set (match_operand:QI 0 "register_operand" "=r")
3314 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3315 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3318 [(set_attr "type" "mvi")])
3320 (define_insn "smaxqi3"
3321 [(set (match_operand:QI 0 "register_operand" "=r")
3322 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3323 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3326 [(set_attr "type" "mvi")])
3328 (define_insn "umaxqi3"
3329 [(set (match_operand:QI 0 "register_operand" "=r")
3330 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3331 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3334 [(set_attr "type" "mvi")])
3336 (define_insn "sminhi3"
3337 [(set (match_operand:HI 0 "register_operand" "=r")
3338 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3339 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3342 [(set_attr "type" "mvi")])
3344 (define_insn "uminhi3"
3345 [(set (match_operand:HI 0 "register_operand" "=r")
3346 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3347 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3350 [(set_attr "type" "mvi")])
3352 (define_insn "smaxhi3"
3353 [(set (match_operand:HI 0 "register_operand" "=r")
3354 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3355 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3358 [(set_attr "type" "mvi")])
3360 (define_insn "umaxhi3"
3361 [(set (match_operand:HI 0 "register_operand" "=r")
3362 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3363 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3366 [(set_attr "type" "mvi")])
3368 (define_expand "smaxdi3"
3370 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
3371 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3372 (set (match_operand:DI 0 "register_operand" "")
3373 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3374 (match_dup 1) (match_dup 2)))]
3376 { operands[3] = gen_reg_rtx (DImode); })
3379 [(set (match_operand:DI 0 "register_operand" "")
3380 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3381 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3382 (clobber (match_operand:DI 3 "register_operand" ""))]
3383 "operands[2] != const0_rtx"
3384 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
3385 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3386 (match_dup 1) (match_dup 2)))]
3389 (define_insn "*smax_const0"
3390 [(set (match_operand:DI 0 "register_operand" "=r")
3391 (smax:DI (match_operand:DI 1 "register_operand" "0")
3395 [(set_attr "type" "icmov")])
3397 (define_expand "smindi3"
3399 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
3400 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3401 (set (match_operand:DI 0 "register_operand" "")
3402 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3403 (match_dup 1) (match_dup 2)))]
3405 { operands[3] = gen_reg_rtx (DImode); })
3408 [(set (match_operand:DI 0 "register_operand" "")
3409 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3410 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3411 (clobber (match_operand:DI 3 "register_operand" ""))]
3412 "operands[2] != const0_rtx"
3413 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
3414 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3415 (match_dup 1) (match_dup 2)))]
3418 (define_insn "*smin_const0"
3419 [(set (match_operand:DI 0 "register_operand" "=r")
3420 (smin:DI (match_operand:DI 1 "register_operand" "0")
3424 [(set_attr "type" "icmov")])
3426 (define_expand "umaxdi3"
3428 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3429 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3430 (set (match_operand:DI 0 "register_operand" "")
3431 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3432 (match_dup 1) (match_dup 2)))]
3434 "operands[3] = gen_reg_rtx (DImode);")
3437 [(set (match_operand:DI 0 "register_operand" "")
3438 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3439 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3440 (clobber (match_operand:DI 3 "register_operand" ""))]
3441 "operands[2] != const0_rtx"
3442 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
3443 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3444 (match_dup 1) (match_dup 2)))]
3447 (define_expand "umindi3"
3449 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3450 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3451 (set (match_operand:DI 0 "register_operand" "")
3452 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3453 (match_dup 1) (match_dup 2)))]
3455 "operands[3] = gen_reg_rtx (DImode);")
3458 [(set (match_operand:DI 0 "register_operand" "")
3459 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3460 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3461 (clobber (match_operand:DI 3 "register_operand" ""))]
3462 "operands[2] != const0_rtx"
3463 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
3464 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3465 (match_dup 1) (match_dup 2)))]
3468 (define_insn "*bcc_normal"
3471 (match_operator 1 "signed_comparison_operator"
3472 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3474 (label_ref (match_operand 0 "" ""))
3478 [(set_attr "type" "ibr")])
3480 (define_insn "*bcc_reverse"
3483 (match_operator 1 "signed_comparison_operator"
3484 [(match_operand:DI 2 "register_operand" "r")
3488 (label_ref (match_operand 0 "" ""))))]
3491 [(set_attr "type" "ibr")])
3493 (define_insn "*blbs_normal"
3496 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3500 (label_ref (match_operand 0 "" ""))
3504 [(set_attr "type" "ibr")])
3506 (define_insn "*blbc_normal"
3509 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3513 (label_ref (match_operand 0 "" ""))
3517 [(set_attr "type" "ibr")])
3523 (match_operator 1 "comparison_operator"
3524 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
3526 (match_operand:DI 3 "const_int_operand" ""))
3528 (label_ref (match_operand 0 "" ""))
3530 (clobber (match_operand:DI 4 "register_operand" ""))])]
3531 "INTVAL (operands[3]) != 0"
3533 (lshiftrt:DI (match_dup 2) (match_dup 3)))
3535 (if_then_else (match_op_dup 1
3536 [(zero_extract:DI (match_dup 4)
3540 (label_ref (match_dup 0))
3544 ;; The following are the corresponding floating-point insns. Recall
3545 ;; we need to have variants that expand the arguments from SFmode
3548 (define_insn "*cmpdf_ieee"
3549 [(set (match_operand:DF 0 "register_operand" "=&f")
3550 (match_operator:DF 1 "alpha_fp_comparison_operator"
3551 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3552 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3553 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3554 "cmp%-%C1%/ %R2,%R3,%0"
3555 [(set_attr "type" "fadd")
3556 (set_attr "trap" "yes")
3557 (set_attr "trap_suffix" "su")])
3559 (define_insn "*cmpdf_internal"
3560 [(set (match_operand:DF 0 "register_operand" "=f")
3561 (match_operator:DF 1 "alpha_fp_comparison_operator"
3562 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3563 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3564 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3565 "cmp%-%C1%/ %R2,%R3,%0"
3566 [(set_attr "type" "fadd")
3567 (set_attr "trap" "yes")
3568 (set_attr "trap_suffix" "su")])
3570 (define_insn "*cmpdf_ieee_ext1"
3571 [(set (match_operand:DF 0 "register_operand" "=&f")
3572 (match_operator:DF 1 "alpha_fp_comparison_operator"
3574 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3575 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3576 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3577 "cmp%-%C1%/ %R2,%R3,%0"
3578 [(set_attr "type" "fadd")
3579 (set_attr "trap" "yes")
3580 (set_attr "trap_suffix" "su")])
3582 (define_insn "*cmpdf_ext1"
3583 [(set (match_operand:DF 0 "register_operand" "=f")
3584 (match_operator:DF 1 "alpha_fp_comparison_operator"
3586 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3587 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3588 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3589 "cmp%-%C1%/ %R2,%R3,%0"
3590 [(set_attr "type" "fadd")
3591 (set_attr "trap" "yes")
3592 (set_attr "trap_suffix" "su")])
3594 (define_insn "*cmpdf_ieee_ext2"
3595 [(set (match_operand:DF 0 "register_operand" "=&f")
3596 (match_operator:DF 1 "alpha_fp_comparison_operator"
3597 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3599 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3600 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3601 "cmp%-%C1%/ %R2,%R3,%0"
3602 [(set_attr "type" "fadd")
3603 (set_attr "trap" "yes")
3604 (set_attr "trap_suffix" "su")])
3606 (define_insn "*cmpdf_ext2"
3607 [(set (match_operand:DF 0 "register_operand" "=f")
3608 (match_operator:DF 1 "alpha_fp_comparison_operator"
3609 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3611 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3612 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3613 "cmp%-%C1%/ %R2,%R3,%0"
3614 [(set_attr "type" "fadd")
3615 (set_attr "trap" "yes")
3616 (set_attr "trap_suffix" "su")])
3618 (define_insn "*cmpdf_ieee_ext3"
3619 [(set (match_operand:DF 0 "register_operand" "=&f")
3620 (match_operator:DF 1 "alpha_fp_comparison_operator"
3622 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3624 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3625 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3626 "cmp%-%C1%/ %R2,%R3,%0"
3627 [(set_attr "type" "fadd")
3628 (set_attr "trap" "yes")
3629 (set_attr "trap_suffix" "su")])
3631 (define_insn "*cmpdf_ext3"
3632 [(set (match_operand:DF 0 "register_operand" "=f")
3633 (match_operator:DF 1 "alpha_fp_comparison_operator"
3635 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3637 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3638 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3639 "cmp%-%C1%/ %R2,%R3,%0"
3640 [(set_attr "type" "fadd")
3641 (set_attr "trap" "yes")
3642 (set_attr "trap_suffix" "su")])
3644 (define_insn "*movdfcc_internal"
3645 [(set (match_operand:DF 0 "register_operand" "=f,f")
3647 (match_operator 3 "signed_comparison_operator"
3648 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3649 (match_operand:DF 2 "const0_operand" "G,G")])
3650 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3651 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3655 fcmov%D3 %R4,%R5,%0"
3656 [(set_attr "type" "fcmov")])
3658 (define_insn "*movsfcc_internal"
3659 [(set (match_operand:SF 0 "register_operand" "=f,f")
3661 (match_operator 3 "signed_comparison_operator"
3662 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3663 (match_operand:DF 2 "const0_operand" "G,G")])
3664 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3665 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3669 fcmov%D3 %R4,%R5,%0"
3670 [(set_attr "type" "fcmov")])
3672 (define_insn "*movdfcc_ext1"
3673 [(set (match_operand:DF 0 "register_operand" "=f,f")
3675 (match_operator 3 "signed_comparison_operator"
3676 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3677 (match_operand:DF 2 "const0_operand" "G,G")])
3678 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3679 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3683 fcmov%D3 %R4,%R5,%0"
3684 [(set_attr "type" "fcmov")])
3686 (define_insn "*movdfcc_ext2"
3687 [(set (match_operand:DF 0 "register_operand" "=f,f")
3689 (match_operator 3 "signed_comparison_operator"
3691 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3692 (match_operand:DF 2 "const0_operand" "G,G")])
3693 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3694 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3698 fcmov%D3 %R4,%R5,%0"
3699 [(set_attr "type" "fcmov")])
3701 (define_insn "*movdfcc_ext3"
3702 [(set (match_operand:SF 0 "register_operand" "=f,f")
3704 (match_operator 3 "signed_comparison_operator"
3706 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3707 (match_operand:DF 2 "const0_operand" "G,G")])
3708 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3709 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3713 fcmov%D3 %R4,%R5,%0"
3714 [(set_attr "type" "fcmov")])
3716 (define_insn "*movdfcc_ext4"
3717 [(set (match_operand:DF 0 "register_operand" "=f,f")
3719 (match_operator 3 "signed_comparison_operator"
3721 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3722 (match_operand:DF 2 "const0_operand" "G,G")])
3723 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3724 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3728 fcmov%D3 %R4,%R5,%0"
3729 [(set_attr "type" "fcmov")])
3731 (define_expand "maxdf3"
3733 (le:DF (match_operand:DF 1 "reg_or_0_operand" "")
3734 (match_operand:DF 2 "reg_or_0_operand" "")))
3735 (set (match_operand:DF 0 "register_operand" "")
3736 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3737 (match_dup 1) (match_dup 2)))]
3740 operands[3] = gen_reg_rtx (DFmode);
3741 operands[4] = CONST0_RTX (DFmode);
3744 (define_expand "mindf3"
3746 (lt:DF (match_operand:DF 1 "reg_or_0_operand" "")
3747 (match_operand:DF 2 "reg_or_0_operand" "")))
3748 (set (match_operand:DF 0 "register_operand" "")
3749 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3750 (match_dup 1) (match_dup 2)))]
3753 operands[3] = gen_reg_rtx (DFmode);
3754 operands[4] = CONST0_RTX (DFmode);
3757 (define_expand "maxsf3"
3759 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3760 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3761 (set (match_operand:SF 0 "register_operand" "")
3762 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3763 (match_dup 1) (match_dup 2)))]
3766 operands[3] = gen_reg_rtx (DFmode);
3767 operands[4] = CONST0_RTX (DFmode);
3770 (define_expand "minsf3"
3772 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3773 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3774 (set (match_operand:SF 0 "register_operand" "")
3775 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3776 (match_dup 1) (match_dup 2)))]
3779 operands[3] = gen_reg_rtx (DFmode);
3780 operands[4] = CONST0_RTX (DFmode);
3783 (define_insn "*fbcc_normal"
3786 (match_operator 1 "signed_comparison_operator"
3787 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3788 (match_operand:DF 3 "const0_operand" "G")])
3789 (label_ref (match_operand 0 "" ""))
3793 [(set_attr "type" "fbr")])
3795 (define_insn "*fbcc_ext_normal"
3798 (match_operator 1 "signed_comparison_operator"
3800 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3801 (match_operand:DF 3 "const0_operand" "G")])
3802 (label_ref (match_operand 0 "" ""))
3806 [(set_attr "type" "fbr")])
3808 ;; These are the main define_expand's used to make conditional branches
3811 (define_expand "cmpdf"
3812 [(set (cc0) (compare (match_operand:DF 0 "reg_or_0_operand" "")
3813 (match_operand:DF 1 "reg_or_0_operand" "")))]
3816 alpha_compare.op0 = operands[0];
3817 alpha_compare.op1 = operands[1];
3818 alpha_compare.fp_p = 1;
3822 (define_expand "cmptf"
3823 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3824 (match_operand:TF 1 "general_operand" "")))]
3825 "TARGET_HAS_XFLOATING_LIBS"
3827 alpha_compare.op0 = operands[0];
3828 alpha_compare.op1 = operands[1];
3829 alpha_compare.fp_p = 1;
3833 (define_expand "cmpdi"
3834 [(set (cc0) (compare (match_operand:DI 0 "general_operand" "")
3835 (match_operand:DI 1 "general_operand" "")))]
3838 alpha_compare.op0 = operands[0];
3839 alpha_compare.op1 = operands[1];
3840 alpha_compare.fp_p = 0;
3844 (define_expand "beq"
3846 (if_then_else (match_dup 1)
3847 (label_ref (match_operand 0 "" ""))
3850 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3852 (define_expand "bne"
3854 (if_then_else (match_dup 1)
3855 (label_ref (match_operand 0 "" ""))
3858 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3860 (define_expand "blt"
3862 (if_then_else (match_dup 1)
3863 (label_ref (match_operand 0 "" ""))
3866 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3868 (define_expand "ble"
3870 (if_then_else (match_dup 1)
3871 (label_ref (match_operand 0 "" ""))
3874 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3876 (define_expand "bgt"
3878 (if_then_else (match_dup 1)
3879 (label_ref (match_operand 0 "" ""))
3882 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3884 (define_expand "bge"
3886 (if_then_else (match_dup 1)
3887 (label_ref (match_operand 0 "" ""))
3890 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3892 (define_expand "bltu"
3894 (if_then_else (match_dup 1)
3895 (label_ref (match_operand 0 "" ""))
3898 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
3900 (define_expand "bleu"
3902 (if_then_else (match_dup 1)
3903 (label_ref (match_operand 0 "" ""))
3906 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
3908 (define_expand "bgtu"
3910 (if_then_else (match_dup 1)
3911 (label_ref (match_operand 0 "" ""))
3914 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
3916 (define_expand "bgeu"
3918 (if_then_else (match_dup 1)
3919 (label_ref (match_operand 0 "" ""))
3922 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
3924 (define_expand "bunordered"
3926 (if_then_else (match_dup 1)
3927 (label_ref (match_operand 0 "" ""))
3930 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
3932 (define_expand "bordered"
3934 (if_then_else (match_dup 1)
3935 (label_ref (match_operand 0 "" ""))
3938 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
3940 (define_expand "seq"
3941 [(set (match_operand:DI 0 "register_operand" "")
3944 "{ if ((operands[1] = alpha_emit_setcc (EQ)) == NULL_RTX) FAIL; }")
3946 (define_expand "sne"
3947 [(set (match_operand:DI 0 "register_operand" "")
3950 "{ if ((operands[1] = alpha_emit_setcc (NE)) == NULL_RTX) FAIL; }")
3952 (define_expand "slt"
3953 [(set (match_operand:DI 0 "register_operand" "")
3956 "{ if ((operands[1] = alpha_emit_setcc (LT)) == NULL_RTX) FAIL; }")
3958 (define_expand "sle"
3959 [(set (match_operand:DI 0 "register_operand" "")
3962 "{ if ((operands[1] = alpha_emit_setcc (LE)) == NULL_RTX) FAIL; }")
3964 (define_expand "sgt"
3965 [(set (match_operand:DI 0 "register_operand" "")
3968 "{ if ((operands[1] = alpha_emit_setcc (GT)) == NULL_RTX) FAIL; }")
3970 (define_expand "sge"
3971 [(set (match_operand:DI 0 "register_operand" "")
3974 "{ if ((operands[1] = alpha_emit_setcc (GE)) == NULL_RTX) FAIL; }")
3976 (define_expand "sltu"
3977 [(set (match_operand:DI 0 "register_operand" "")
3980 "{ if ((operands[1] = alpha_emit_setcc (LTU)) == NULL_RTX) FAIL; }")
3982 (define_expand "sleu"
3983 [(set (match_operand:DI 0 "register_operand" "")
3986 "{ if ((operands[1] = alpha_emit_setcc (LEU)) == NULL_RTX) FAIL; }")
3988 (define_expand "sgtu"
3989 [(set (match_operand:DI 0 "register_operand" "")
3992 "{ if ((operands[1] = alpha_emit_setcc (GTU)) == NULL_RTX) FAIL; }")
3994 (define_expand "sgeu"
3995 [(set (match_operand:DI 0 "register_operand" "")
3998 "{ if ((operands[1] = alpha_emit_setcc (GEU)) == NULL_RTX) FAIL; }")
4000 (define_expand "sunordered"
4001 [(set (match_operand:DI 0 "register_operand" "")
4004 "{ if ((operands[1] = alpha_emit_setcc (UNORDERED)) == NULL_RTX) FAIL; }")
4006 (define_expand "sordered"
4007 [(set (match_operand:DI 0 "register_operand" "")
4010 "{ if ((operands[1] = alpha_emit_setcc (ORDERED)) == NULL_RTX) FAIL; }")
4012 ;; These are the main define_expand's used to make conditional moves.
4014 (define_expand "movsicc"
4015 [(set (match_operand:SI 0 "register_operand" "")
4016 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4017 (match_operand:SI 2 "reg_or_8bit_operand" "")
4018 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
4021 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
4025 (define_expand "movdicc"
4026 [(set (match_operand:DI 0 "register_operand" "")
4027 (if_then_else:DI (match_operand 1 "comparison_operator" "")
4028 (match_operand:DI 2 "reg_or_8bit_operand" "")
4029 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
4032 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
4036 (define_expand "movsfcc"
4037 [(set (match_operand:SF 0 "register_operand" "")
4038 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4039 (match_operand:SF 2 "reg_or_8bit_operand" "")
4040 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
4043 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
4047 (define_expand "movdfcc"
4048 [(set (match_operand:DF 0 "register_operand" "")
4049 (if_then_else:DF (match_operand 1 "comparison_operator" "")
4050 (match_operand:DF 2 "reg_or_8bit_operand" "")
4051 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
4054 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
4058 ;; These define_split definitions are used in cases when comparisons have
4059 ;; not be stated in the correct way and we need to reverse the second
4060 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
4061 ;; comparison that tests the result being reversed. We have one define_split
4062 ;; for each use of a comparison. They do not match valid insns and need
4063 ;; not generate valid insns.
4065 ;; We can also handle equality comparisons (and inequality comparisons in
4066 ;; cases where the resulting add cannot overflow) by doing an add followed by
4067 ;; a comparison with zero. This is faster since the addition takes one
4068 ;; less cycle than a compare when feeding into a conditional move.
4069 ;; For this case, we also have an SImode pattern since we can merge the add
4070 ;; and sign extend and the order doesn't matter.
4072 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
4073 ;; operation could have been generated.
4076 [(set (match_operand:DI 0 "register_operand" "")
4078 (match_operator 1 "comparison_operator"
4079 [(match_operand:DI 2 "reg_or_0_operand" "")
4080 (match_operand:DI 3 "reg_or_cint_operand" "")])
4081 (match_operand:DI 4 "reg_or_cint_operand" "")
4082 (match_operand:DI 5 "reg_or_cint_operand" "")))
4083 (clobber (match_operand:DI 6 "register_operand" ""))]
4084 "operands[3] != const0_rtx"
4085 [(set (match_dup 6) (match_dup 7))
4087 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4089 enum rtx_code code = GET_CODE (operands[1]);
4090 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4092 /* If we are comparing for equality with a constant and that constant
4093 appears in the arm when the register equals the constant, use the
4094 register since that is more likely to match (and to produce better code
4097 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
4098 && rtx_equal_p (operands[4], operands[3]))
4099 operands[4] = operands[2];
4101 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
4102 && rtx_equal_p (operands[5], operands[3]))
4103 operands[5] = operands[2];
4105 if (code == NE || code == EQ
4106 || (extended_count (operands[2], DImode, unsignedp) >= 1
4107 && extended_count (operands[3], DImode, unsignedp) >= 1))
4109 if (GET_CODE (operands[3]) == CONST_INT)
4110 operands[7] = gen_rtx_PLUS (DImode, operands[2],
4111 GEN_INT (- INTVAL (operands[3])));
4113 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4115 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
4118 else if (code == EQ || code == LE || code == LT
4119 || code == LEU || code == LTU)
4121 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4122 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
4126 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4127 operands[2], operands[3]);
4128 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
4133 [(set (match_operand:DI 0 "register_operand" "")
4135 (match_operator 1 "comparison_operator"
4136 [(match_operand:SI 2 "reg_or_0_operand" "")
4137 (match_operand:SI 3 "reg_or_cint_operand" "")])
4138 (match_operand:DI 4 "reg_or_8bit_operand" "")
4139 (match_operand:DI 5 "reg_or_8bit_operand" "")))
4140 (clobber (match_operand:DI 6 "register_operand" ""))]
4141 "operands[3] != const0_rtx
4142 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4143 [(set (match_dup 6) (match_dup 7))
4145 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4147 enum rtx_code code = GET_CODE (operands[1]);
4148 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4151 if ((code != NE && code != EQ
4152 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
4153 && extended_count (operands[3], DImode, unsignedp) >= 1)))
4156 if (GET_CODE (operands[3]) == CONST_INT)
4157 tem = gen_rtx_PLUS (SImode, operands[2],
4158 GEN_INT (- INTVAL (operands[3])));
4160 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4162 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
4163 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4164 operands[6], const0_rtx);
4170 (match_operator 1 "comparison_operator"
4171 [(match_operand:DI 2 "reg_or_0_operand" "")
4172 (match_operand:DI 3 "reg_or_cint_operand" "")])
4173 (label_ref (match_operand 0 "" ""))
4175 (clobber (match_operand:DI 4 "register_operand" ""))]
4176 "operands[3] != const0_rtx"
4177 [(set (match_dup 4) (match_dup 5))
4178 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
4180 enum rtx_code code = GET_CODE (operands[1]);
4181 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4183 if (code == NE || code == EQ
4184 || (extended_count (operands[2], DImode, unsignedp) >= 1
4185 && extended_count (operands[3], DImode, unsignedp) >= 1))
4187 if (GET_CODE (operands[3]) == CONST_INT)
4188 operands[5] = gen_rtx_PLUS (DImode, operands[2],
4189 GEN_INT (- INTVAL (operands[3])));
4191 operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4193 operands[6] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
4196 else if (code == EQ || code == LE || code == LT
4197 || code == LEU || code == LTU)
4199 operands[5] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4200 operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx);
4204 operands[5] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4205 operands[2], operands[3]);
4206 operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
4213 (match_operator 1 "comparison_operator"
4214 [(match_operand:SI 2 "reg_or_0_operand" "")
4215 (match_operand:SI 3 "const_int_operand" "")])
4216 (label_ref (match_operand 0 "" ""))
4218 (clobber (match_operand:DI 4 "register_operand" ""))]
4219 "operands[3] != const0_rtx
4220 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4221 [(set (match_dup 4) (match_dup 5))
4222 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
4226 if (GET_CODE (operands[3]) == CONST_INT)
4227 tem = gen_rtx_PLUS (SImode, operands[2],
4228 GEN_INT (- INTVAL (operands[3])));
4230 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4232 operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem);
4233 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4234 operands[4], const0_rtx);
4237 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
4238 ;; This eliminates one, and sometimes two, insns when the AND can be done
4241 [(set (match_operand:DI 0 "register_operand" "")
4242 (match_operator:DI 1 "comparison_operator"
4243 [(match_operand:DI 2 "register_operand" "")
4244 (match_operand:DI 3 "const_int_operand" "")]))
4245 (clobber (match_operand:DI 4 "register_operand" ""))]
4246 "exact_log2 (INTVAL (operands[3]) + 1) >= 0
4247 && (GET_CODE (operands[1]) == GTU
4248 || GET_CODE (operands[1]) == LEU
4249 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
4250 && extended_count (operands[2], DImode, 1) > 0))"
4251 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
4252 (set (match_dup 0) (match_dup 6))]
4254 operands[5] = GEN_INT (~ INTVAL (operands[3]));
4255 operands[6] = gen_rtx_fmt_ee (((GET_CODE (operands[1]) == GTU
4256 || GET_CODE (operands[1]) == GT)
4258 DImode, operands[4], const0_rtx);
4261 ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
4264 [(set (match_operand 0 "register_operand" "")
4265 (if_then_else (match_operator 1 "signed_comparison_operator"
4266 [(match_operand:DI 2 "reg_or_0_operand" "")
4268 (match_operand 3 "const_int_operand" "")
4269 (match_operand 4 "const_int_operand" "")))]
4273 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
4274 operands[2], operands[3], operands[4]))
4280 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
4281 ;; Oh well, we match it in movcc, so it must be partially our fault.
4283 [(set (match_operand 0 "register_operand" "")
4284 (if_then_else (match_operator 1 "signed_comparison_operator"
4286 (match_operand:DI 2 "reg_or_0_operand" "")])
4287 (match_operand 3 "const_int_operand" "")
4288 (match_operand 4 "const_int_operand" "")))]
4292 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
4293 operands[0], operands[2], operands[3],
4300 (define_insn_and_split "*cmp_sadd_di"
4301 [(set (match_operand:DI 0 "register_operand" "=r")
4302 (plus:DI (if_then_else:DI
4303 (match_operator 1 "alpha_zero_comparison_operator"
4304 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4306 (match_operand:DI 3 "const48_operand" "I")
4308 (match_operand:DI 4 "sext_add_operand" "rIO")))
4309 (clobber (match_scratch:DI 5 "=r"))]
4312 "! no_new_pseudos || reload_completed"
4314 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4316 (plus:DI (mult:DI (match_dup 5) (match_dup 3))
4319 if (! no_new_pseudos)
4320 operands[5] = gen_reg_rtx (DImode);
4321 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4322 operands[5] = operands[0];
4325 (define_insn_and_split "*cmp_sadd_si"
4326 [(set (match_operand:SI 0 "register_operand" "=r")
4327 (plus:SI (if_then_else:SI
4328 (match_operator 1 "alpha_zero_comparison_operator"
4329 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4331 (match_operand:SI 3 "const48_operand" "I")
4333 (match_operand:SI 4 "sext_add_operand" "rIO")))
4334 (clobber (match_scratch:SI 5 "=r"))]
4337 "! no_new_pseudos || reload_completed"
4339 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4341 (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4344 if (! no_new_pseudos)
4345 operands[5] = gen_reg_rtx (DImode);
4346 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4347 operands[5] = operands[0];
4350 (define_insn_and_split "*cmp_sadd_sidi"
4351 [(set (match_operand:DI 0 "register_operand" "=r")
4353 (plus:SI (if_then_else:SI
4354 (match_operator 1 "alpha_zero_comparison_operator"
4355 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4357 (match_operand:SI 3 "const48_operand" "I")
4359 (match_operand:SI 4 "sext_add_operand" "rIO"))))
4360 (clobber (match_scratch:SI 5 "=r"))]
4363 "! no_new_pseudos || reload_completed"
4365 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4367 (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4370 if (! no_new_pseudos)
4371 operands[5] = gen_reg_rtx (DImode);
4372 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4373 operands[5] = operands[0];
4376 (define_insn_and_split "*cmp_ssub_di"
4377 [(set (match_operand:DI 0 "register_operand" "=r")
4378 (minus:DI (if_then_else:DI
4379 (match_operator 1 "alpha_zero_comparison_operator"
4380 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4382 (match_operand:DI 3 "const48_operand" "I")
4384 (match_operand:DI 4 "reg_or_8bit_operand" "rI")))
4385 (clobber (match_scratch:DI 5 "=r"))]
4388 "! no_new_pseudos || reload_completed"
4390 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4392 (minus:DI (mult:DI (match_dup 5) (match_dup 3))
4395 if (! no_new_pseudos)
4396 operands[5] = gen_reg_rtx (DImode);
4397 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4398 operands[5] = operands[0];
4401 (define_insn_and_split "*cmp_ssub_si"
4402 [(set (match_operand:SI 0 "register_operand" "=r")
4403 (minus:SI (if_then_else:SI
4404 (match_operator 1 "alpha_zero_comparison_operator"
4405 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4407 (match_operand:SI 3 "const48_operand" "I")
4409 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))
4410 (clobber (match_scratch:SI 5 "=r"))]
4413 "! no_new_pseudos || reload_completed"
4415 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4417 (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4420 if (! no_new_pseudos)
4421 operands[5] = gen_reg_rtx (DImode);
4422 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4423 operands[5] = operands[0];
4426 (define_insn_and_split "*cmp_ssub_sidi"
4427 [(set (match_operand:DI 0 "register_operand" "=r")
4429 (minus:SI (if_then_else:SI
4430 (match_operator 1 "alpha_zero_comparison_operator"
4431 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4433 (match_operand:SI 3 "const48_operand" "I")
4435 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
4436 (clobber (match_scratch:SI 5 "=r"))]
4439 "! no_new_pseudos || reload_completed"
4441 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4443 (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4446 if (! no_new_pseudos)
4447 operands[5] = gen_reg_rtx (DImode);
4448 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4449 operands[5] = operands[0];
4452 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
4453 ;; work differently, so we have different patterns for each.
4455 ;; On Unicos/Mk a call information word (CIW) must be generated for each
4456 ;; call. The CIW contains information about arguments passed in registers
4457 ;; and is stored in the caller's SSIB. Its offset relative to the beginning
4458 ;; of the SSIB is passed in $25. Handling this properly is quite complicated
4459 ;; in the presence of inlining since the CIWs for calls performed by the
4460 ;; inlined function must be stored in the SSIB of the function it is inlined
4461 ;; into as well. We encode the CIW in an unspec and append it to the list
4462 ;; of the CIWs for the current function only when the instruction for loading
4463 ;; $25 is generated.
4465 (define_expand "call"
4466 [(use (match_operand:DI 0 "" ""))
4467 (use (match_operand 1 "" ""))
4468 (use (match_operand 2 "" ""))
4469 (use (match_operand 3 "" ""))]
4472 if (TARGET_ABI_WINDOWS_NT)
4473 emit_call_insn (gen_call_nt (operands[0], operands[1]));
4474 else if (TARGET_ABI_OPEN_VMS)
4475 emit_call_insn (gen_call_vms (operands[0], operands[2]));
4476 else if (TARGET_ABI_UNICOSMK)
4477 emit_call_insn (gen_call_umk (operands[0], operands[2]));
4479 emit_call_insn (gen_call_osf (operands[0], operands[1]));
4483 (define_expand "sibcall"
4484 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4485 (match_operand 1 "" ""))
4486 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4489 if (GET_CODE (operands[0]) != MEM)
4491 operands[0] = XEXP (operands[0], 0);
4494 (define_expand "call_osf"
4495 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4496 (match_operand 1 "" ""))
4498 (clobber (reg:DI 26))])]
4501 if (GET_CODE (operands[0]) != MEM)
4504 operands[0] = XEXP (operands[0], 0);
4505 if (! call_operand (operands[0], Pmode))
4506 operands[0] = copy_to_mode_reg (Pmode, operands[0]);
4509 (define_expand "call_nt"
4510 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4511 (match_operand 1 "" ""))
4512 (clobber (reg:DI 26))])]
4515 if (GET_CODE (operands[0]) != MEM)
4518 operands[0] = XEXP (operands[0], 0);
4519 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
4520 operands[0] = force_reg (DImode, operands[0]);
4523 ;; Calls on Unicos/Mk are always indirect.
4524 ;; op 0: symbol ref for called function
4525 ;; op 1: CIW for $25 represented by an unspec
4527 (define_expand "call_umk"
4528 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4529 (match_operand 1 "" ""))
4531 (clobber (reg:DI 26))])]
4534 if (GET_CODE (operands[0]) != MEM)
4537 /* Always load the address of the called function into a register;
4538 load the CIW in $25. */
4540 operands[0] = XEXP (operands[0], 0);
4541 if (GET_CODE (operands[0]) != REG)
4542 operands[0] = force_reg (DImode, operands[0]);
4544 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4548 ;; call openvms/alpha
4549 ;; op 0: symbol ref for called function
4550 ;; op 1: next_arg_reg (argument information value for R25)
4552 (define_expand "call_vms"
4553 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4554 (match_operand 1 "" ""))
4558 (clobber (reg:DI 27))])]
4561 if (GET_CODE (operands[0]) != MEM)
4564 operands[0] = XEXP (operands[0], 0);
4566 /* Always load AI with argument information, then handle symbolic and
4567 indirect call differently. Load RA and set operands[2] to PV in
4570 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4571 if (GET_CODE (operands[0]) == SYMBOL_REF)
4573 alpha_need_linkage (XSTR (operands[0], 0), 0);
4575 operands[2] = const0_rtx;
4579 emit_move_insn (gen_rtx_REG (Pmode, 26),
4580 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
4581 operands[2] = operands[0];
4586 (define_expand "call_value"
4587 [(use (match_operand 0 "" ""))
4588 (use (match_operand:DI 1 "" ""))
4589 (use (match_operand 2 "" ""))
4590 (use (match_operand 3 "" ""))
4591 (use (match_operand 4 "" ""))]
4594 if (TARGET_ABI_WINDOWS_NT)
4595 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
4596 else if (TARGET_ABI_OPEN_VMS)
4597 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
4599 else if (TARGET_ABI_UNICOSMK)
4600 emit_call_insn (gen_call_value_umk (operands[0], operands[1],
4603 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
4608 (define_expand "sibcall_value"
4609 [(parallel [(set (match_operand 0 "" "")
4610 (call (mem:DI (match_operand 1 "" ""))
4611 (match_operand 2 "" "")))
4612 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4615 if (GET_CODE (operands[1]) != MEM)
4617 operands[1] = XEXP (operands[1], 0);
4620 (define_expand "call_value_osf"
4621 [(parallel [(set (match_operand 0 "" "")
4622 (call (mem:DI (match_operand 1 "" ""))
4623 (match_operand 2 "" "")))
4625 (clobber (reg:DI 26))])]
4628 if (GET_CODE (operands[1]) != MEM)
4631 operands[1] = XEXP (operands[1], 0);
4632 if (! call_operand (operands[1], Pmode))
4633 operands[1] = copy_to_mode_reg (Pmode, operands[1]);
4636 (define_expand "call_value_nt"
4637 [(parallel [(set (match_operand 0 "" "")
4638 (call (mem:DI (match_operand 1 "" ""))
4639 (match_operand 2 "" "")))
4640 (clobber (reg:DI 26))])]
4643 if (GET_CODE (operands[1]) != MEM)
4646 operands[1] = XEXP (operands[1], 0);
4647 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
4648 operands[1] = force_reg (DImode, operands[1]);
4651 (define_expand "call_value_vms"
4652 [(parallel [(set (match_operand 0 "" "")
4653 (call (mem:DI (match_operand:DI 1 "" ""))
4654 (match_operand 2 "" "")))
4658 (clobber (reg:DI 27))])]
4661 if (GET_CODE (operands[1]) != MEM)
4664 operands[1] = XEXP (operands[1], 0);
4666 /* Always load AI with argument information, then handle symbolic and
4667 indirect call differently. Load RA and set operands[3] to PV in
4670 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4671 if (GET_CODE (operands[1]) == SYMBOL_REF)
4673 alpha_need_linkage (XSTR (operands[1], 0), 0);
4675 operands[3] = const0_rtx;
4679 emit_move_insn (gen_rtx_REG (Pmode, 26),
4680 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
4681 operands[3] = operands[1];
4685 (define_expand "call_value_umk"
4686 [(parallel [(set (match_operand 0 "" "")
4687 (call (mem:DI (match_operand 1 "" ""))
4688 (match_operand 2 "" "")))
4690 (clobber (reg:DI 26))])]
4693 if (GET_CODE (operands[1]) != MEM)
4696 operands[1] = XEXP (operands[1], 0);
4697 if (GET_CODE (operands[1]) != REG)
4698 operands[1] = force_reg (DImode, operands[1]);
4700 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4703 (define_insn "*call_osf_1_er"
4704 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4705 (match_operand 1 "" ""))
4707 (clobber (reg:DI 26))]
4708 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4710 jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
4711 bsr $26,%0\t\t!samegp
4712 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
4713 [(set_attr "type" "jsr")
4714 (set_attr "length" "12,*,16")])
4716 ;; We must use peep2 instead of a split because we need accurate life
4717 ;; information for $gp. Consider the case of { bar(); while (1); }.
4719 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4720 (match_operand 1 "" ""))
4722 (clobber (reg:DI 26))])]
4723 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4724 && ! samegp_function_operand (operands[0], Pmode)
4725 && (peep2_regno_dead_p (1, 29)
4726 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
4727 [(parallel [(call (mem:DI (match_dup 2))
4729 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4730 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4732 (use (match_dup 3))])]
4734 if (CONSTANT_P (operands[0]))
4736 operands[2] = gen_rtx_REG (Pmode, 27);
4737 operands[3] = GEN_INT (alpha_next_sequence_number++);
4738 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4739 operands[0], operands[3]));
4743 operands[2] = operands[0];
4744 operands[0] = const0_rtx;
4745 operands[3] = const0_rtx;
4750 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4751 (match_operand 1 "" ""))
4753 (clobber (reg:DI 26))])]
4754 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4755 && ! samegp_function_operand (operands[0], Pmode)
4756 && ! (peep2_regno_dead_p (1, 29)
4757 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
4758 [(parallel [(call (mem:DI (match_dup 2))
4760 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4761 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4763 (use (match_dup 4))])
4765 (unspec_volatile:DI [(reg:DI 26) (match_dup 3)] UNSPECV_LDGP1))
4767 (unspec:DI [(reg:DI 29) (match_dup 3)] UNSPEC_LDGP2))]
4769 if (CONSTANT_P (operands[0]))
4771 operands[2] = gen_rtx_REG (Pmode, 27);
4772 operands[4] = GEN_INT (alpha_next_sequence_number++);
4773 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4774 operands[0], operands[4]));
4778 operands[2] = operands[0];
4779 operands[0] = const0_rtx;
4780 operands[4] = const0_rtx;
4782 operands[3] = GEN_INT (alpha_next_sequence_number++);
4785 ;; We add a blockage unspec_volatile to prevent insns from moving down
4786 ;; from above the call to in between the call and the ldah gpdisp.
4788 (define_insn "*call_osf_2_er"
4789 [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
4790 (match_operand 1 "" ""))
4791 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4792 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4793 (use (match_operand 2 "" ""))
4794 (use (match_operand 3 "const_int_operand" ""))]
4795 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4796 "jsr $26,(%0),%2%J3"
4797 [(set_attr "type" "jsr")
4798 (set_attr "cannot_copy" "true")])
4800 ;; We output a nop after noreturn calls at the very end of the function to
4801 ;; ensure that the return address always remains in the caller's code range,
4802 ;; as not doing so might confuse unwinding engines.
4804 ;; The potential change in insn length is not reflected in the length
4805 ;; attributes at this stage. Since the extra space is only actually added at
4806 ;; the very end of the compilation process (via final/print_operand), it
4807 ;; really seems harmless and not worth the trouble of some extra computation
4808 ;; cost and complexity.
4810 (define_insn "*call_osf_1_noreturn"
4811 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4812 (match_operand 1 "" ""))
4814 (clobber (reg:DI 26))]
4815 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
4816 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4821 [(set_attr "type" "jsr")
4822 (set_attr "length" "*,*,8")])
4824 (define_insn "*call_osf_1"
4825 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4826 (match_operand 1 "" ""))
4828 (clobber (reg:DI 26))]
4829 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4831 jsr $26,($27),0\;ldgp $29,0($26)
4833 jsr $26,%0\;ldgp $29,0($26)"
4834 [(set_attr "type" "jsr")
4835 (set_attr "length" "12,*,16")])
4837 ;; Note that the DEC assembler expands "jmp foo" with $at, which
4838 ;; doesn't do what we want.
4839 (define_insn "*sibcall_osf_1_er"
4840 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4841 (match_operand 1 "" ""))
4842 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4843 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4845 br $31,%0\t\t!samegp
4846 ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#"
4847 [(set_attr "type" "jsr")
4848 (set_attr "length" "*,8")])
4850 (define_insn "*sibcall_osf_1"
4851 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4852 (match_operand 1 "" ""))
4853 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4854 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4857 lda $27,%0\;jmp $31,($27),%0"
4858 [(set_attr "type" "jsr")
4859 (set_attr "length" "*,8")])
4861 (define_insn "*call_nt_1"
4862 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,s"))
4863 (match_operand 1 "" ""))
4864 (clobber (reg:DI 26))]
4865 "TARGET_ABI_WINDOWS_NT"
4870 [(set_attr "type" "jsr")
4871 (set_attr "length" "*,*,12")])
4873 ; GAS relies on the order and position of instructions output below in order
4874 ; to generate relocs for VMS link to potentially optimize the call.
4875 ; Please do not molest.
4876 (define_insn "*call_vms_1"
4877 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s"))
4878 (match_operand 1 "" ""))
4879 (use (match_operand:DI 2 "nonmemory_operand" "r,n"))
4882 (clobber (reg:DI 27))]
4883 "TARGET_ABI_OPEN_VMS"
4885 switch (which_alternative)
4888 return "mov %2,$27\;jsr $26,0\;ldq $27,0($29)";
4890 operands [2] = alpha_use_linkage (operands [0], cfun->decl, 1, 0);
4891 operands [3] = alpha_use_linkage (operands [0], cfun->decl, 0, 0);
4892 return "ldq $26,%3\;ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)";
4897 [(set_attr "type" "jsr")
4898 (set_attr "length" "12,16")])
4900 (define_insn "*call_umk_1"
4901 [(call (mem:DI (match_operand:DI 0 "call_operand" "r"))
4902 (match_operand 1 "" ""))
4904 (clobber (reg:DI 26))]
4905 "TARGET_ABI_UNICOSMK"
4907 [(set_attr "type" "jsr")])
4909 ;; Call subroutine returning any type.
4911 (define_expand "untyped_call"
4912 [(parallel [(call (match_operand 0 "" "")
4914 (match_operand 1 "" "")
4915 (match_operand 2 "" "")])]
4920 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
4922 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4924 rtx set = XVECEXP (operands[2], 0, i);
4925 emit_move_insn (SET_DEST (set), SET_SRC (set));
4928 /* The optimizer does not know that the call sets the function value
4929 registers we stored in the result block. We avoid problems by
4930 claiming that all hard registers are used and clobbered at this
4932 emit_insn (gen_blockage ());
4937 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
4938 ;; all of memory. This blocks insns from being moved across this point.
4940 (define_insn "blockage"
4941 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
4944 [(set_attr "length" "0")
4945 (set_attr "type" "none")])
4949 (label_ref (match_operand 0 "" "")))]
4952 [(set_attr "type" "ibr")])
4954 (define_expand "return"
4959 (define_insn "*return_internal"
4963 [(set_attr "type" "ibr")])
4965 (define_insn "indirect_jump"
4966 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
4969 [(set_attr "type" "ibr")])
4971 (define_expand "tablejump"
4972 [(parallel [(set (pc)
4973 (match_operand 0 "register_operand" ""))
4974 (use (label_ref:DI (match_operand 1 "" "")))])]
4977 if (TARGET_ABI_WINDOWS_NT)
4979 rtx dest = gen_reg_rtx (DImode);
4980 emit_insn (gen_extendsidi2 (dest, operands[0]));
4983 else if (TARGET_ABI_OSF)
4985 rtx dest = gen_reg_rtx (DImode);
4986 emit_insn (gen_extendsidi2 (dest, operands[0]));
4987 emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest));
4992 (define_insn "*tablejump_osf_nt_internal"
4994 (match_operand:DI 0 "register_operand" "r"))
4995 (use (label_ref:DI (match_operand 1 "" "")))]
4996 "(TARGET_ABI_OSF || TARGET_ABI_WINDOWS_NT)
4997 && alpha_tablejump_addr_vec (insn)"
4999 operands[2] = alpha_tablejump_best_label (insn);
5000 return "jmp $31,(%0),%2";
5002 [(set_attr "type" "ibr")])
5004 (define_insn "*tablejump_internal"
5006 (match_operand:DI 0 "register_operand" "r"))
5007 (use (label_ref (match_operand 1 "" "")))]
5010 [(set_attr "type" "ibr")])
5012 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
5013 ;; want to have to include pal.h in our .s file.
5015 ;; Technically the type for call_pal is jsr, but we use that for determining
5016 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
5019 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
5022 [(set_attr "type" "callpal")])
5024 ;; BUGCHK is documented common to OSF/1 and VMS PALcode.
5025 ;; NT does not document anything at 0x81 -- presumably it would generate
5026 ;; the equivalent of SIGILL, but this isn't that important.
5027 ;; ??? Presuming unicosmk uses either OSF/1 or VMS PALcode.
5029 [(trap_if (const_int 1) (const_int 0))]
5030 "!TARGET_ABI_WINDOWS_NT"
5032 [(set_attr "type" "callpal")])
5034 ;; For userland, we load the thread pointer from the TCB.
5035 ;; For the kernel, we load the per-cpu private value.
5037 (define_insn "load_tp"
5038 [(set (match_operand:DI 0 "register_operand" "=v")
5039 (unspec:DI [(const_int 0)] UNSPEC_TP))]
5042 if (TARGET_TLS_KERNEL)
5043 return "call_pal 0x32";
5045 return "call_pal 0x9e";
5047 [(set_attr "type" "callpal")])
5049 ;; For completeness, and possibly a __builtin function, here's how to
5050 ;; set the thread pointer. Since we don't describe enough of this
5051 ;; quantity for CSE, we have to use a volatile unspec, and then there's
5052 ;; not much point in creating an R16_REG register class.
5054 (define_expand "set_tp"
5055 [(set (reg:DI 16) (match_operand:DI 0 "input_operand" ""))
5056 (unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
5060 (define_insn "*set_tp"
5061 [(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
5064 if (TARGET_TLS_KERNEL)
5065 return "call_pal 0x31";
5067 return "call_pal 0x9f";
5069 [(set_attr "type" "callpal")])
5071 ;; Finally, we have the basic data motion insns. The byte and word insns
5072 ;; are done via define_expand. Start with the floating-point insns, since
5073 ;; they are simpler.
5075 (define_insn "*movsf_nofix"
5076 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5077 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5078 "TARGET_FPREGS && ! TARGET_FIX
5079 && (register_operand (operands[0], SFmode)
5080 || reg_or_0_operand (operands[1], SFmode))"
5088 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5090 (define_insn "*movsf_fix"
5091 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5092 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5093 "TARGET_FPREGS && TARGET_FIX
5094 && (register_operand (operands[0], SFmode)
5095 || reg_or_0_operand (operands[1], SFmode))"
5105 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5107 (define_insn "*movsf_nofp"
5108 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
5109 (match_operand:SF 1 "input_operand" "rG,m,r"))]
5111 && (register_operand (operands[0], SFmode)
5112 || reg_or_0_operand (operands[1], SFmode))"
5117 [(set_attr "type" "ilog,ild,ist")])
5119 (define_insn "*movdf_nofix"
5120 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5121 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5122 "TARGET_FPREGS && ! TARGET_FIX
5123 && (register_operand (operands[0], DFmode)
5124 || reg_or_0_operand (operands[1], DFmode))"
5132 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5134 (define_insn "*movdf_fix"
5135 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5136 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5137 "TARGET_FPREGS && TARGET_FIX
5138 && (register_operand (operands[0], DFmode)
5139 || reg_or_0_operand (operands[1], DFmode))"
5149 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5151 (define_insn "*movdf_nofp"
5152 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
5153 (match_operand:DF 1 "input_operand" "rG,m,r"))]
5155 && (register_operand (operands[0], DFmode)
5156 || reg_or_0_operand (operands[1], DFmode))"
5161 [(set_attr "type" "ilog,ild,ist")])
5163 ;; Subregs suck for register allocation. Pretend we can move TFmode
5164 ;; data between general registers until after reload.
5166 (define_insn_and_split "*movtf_internal"
5167 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
5168 (match_operand:TF 1 "input_operand" "roG,rG"))]
5169 "register_operand (operands[0], TFmode)
5170 || reg_or_0_operand (operands[1], TFmode)"
5173 [(set (match_dup 0) (match_dup 2))
5174 (set (match_dup 1) (match_dup 3))]
5176 alpha_split_tfmode_pair (operands);
5177 if (reg_overlap_mentioned_p (operands[0], operands[3]))
5180 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
5181 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
5185 (define_expand "movsf"
5186 [(set (match_operand:SF 0 "nonimmediate_operand" "")
5187 (match_operand:SF 1 "general_operand" ""))]
5190 if (GET_CODE (operands[0]) == MEM
5191 && ! reg_or_0_operand (operands[1], SFmode))
5192 operands[1] = force_reg (SFmode, operands[1]);
5195 (define_expand "movdf"
5196 [(set (match_operand:DF 0 "nonimmediate_operand" "")
5197 (match_operand:DF 1 "general_operand" ""))]
5200 if (GET_CODE (operands[0]) == MEM
5201 && ! reg_or_0_operand (operands[1], DFmode))
5202 operands[1] = force_reg (DFmode, operands[1]);
5205 (define_expand "movtf"
5206 [(set (match_operand:TF 0 "nonimmediate_operand" "")
5207 (match_operand:TF 1 "general_operand" ""))]
5210 if (GET_CODE (operands[0]) == MEM
5211 && ! reg_or_0_operand (operands[1], TFmode))
5212 operands[1] = force_reg (TFmode, operands[1]);
5215 (define_insn "*movsi"
5216 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m")
5217 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ"))]
5218 "(TARGET_ABI_OSF || TARGET_ABI_UNICOSMK)
5219 && (register_operand (operands[0], SImode)
5220 || reg_or_0_operand (operands[1], SImode))"
5227 [(set_attr "type" "ilog,iadd,iadd,ild,ist")])
5229 (define_insn "*movsi_nt_vms"
5230 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m")
5231 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ"))]
5232 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5233 && (register_operand (operands[0], SImode)
5234 || reg_or_0_operand (operands[1], SImode))"
5242 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist")])
5244 (define_insn "*movhi_nobwx"
5245 [(set (match_operand:HI 0 "register_operand" "=r,r")
5246 (match_operand:HI 1 "input_operand" "rJ,n"))]
5248 && (register_operand (operands[0], HImode)
5249 || register_operand (operands[1], HImode))"
5253 [(set_attr "type" "ilog,iadd")])
5255 (define_insn "*movhi_bwx"
5256 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
5257 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
5259 && (register_operand (operands[0], HImode)
5260 || reg_or_0_operand (operands[1], HImode))"
5266 [(set_attr "type" "ilog,iadd,ild,ist")])
5268 (define_insn "*movqi_nobwx"
5269 [(set (match_operand:QI 0 "register_operand" "=r,r")
5270 (match_operand:QI 1 "input_operand" "rJ,n"))]
5272 && (register_operand (operands[0], QImode)
5273 || register_operand (operands[1], QImode))"
5277 [(set_attr "type" "ilog,iadd")])
5279 (define_insn "*movqi_bwx"
5280 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
5281 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
5283 && (register_operand (operands[0], QImode)
5284 || reg_or_0_operand (operands[1], QImode))"
5290 [(set_attr "type" "ilog,iadd,ild,ist")])
5292 ;; We do two major things here: handle mem->mem and construct long
5295 (define_expand "movsi"
5296 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5297 (match_operand:SI 1 "general_operand" ""))]
5300 if (alpha_expand_mov (SImode, operands))
5304 ;; Split a load of a large constant into the appropriate two-insn
5308 [(set (match_operand:SI 0 "register_operand" "")
5309 (match_operand:SI 1 "const_int_operand" ""))]
5310 "! add_operand (operands[1], SImode)"
5311 [(set (match_dup 0) (match_dup 2))
5312 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
5315 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
5317 if (tem == operands[0])
5323 ;; Split the load of an address into a four-insn sequence on Unicos/Mk.
5324 ;; Always generate a REG_EQUAL note for the last instruction to facilitate
5325 ;; optimizations. If the symbolic operand is a label_ref, generate REG_LABEL
5326 ;; notes and update LABEL_NUSES because this is not done automatically.
5327 ;; Labels may be incorrectly deleted if we don't do this.
5329 ;; Describing what the individual instructions do correctly is too complicated
5330 ;; so use UNSPECs for each of the three parts of an address.
5333 [(set (match_operand:DI 0 "register_operand" "")
5334 (match_operand:DI 1 "symbolic_operand" ""))]
5335 "TARGET_ABI_UNICOSMK && reload_completed"
5338 rtx insn1, insn2, insn3;
5340 insn1 = emit_insn (gen_umk_laum (operands[0], operands[1]));
5341 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
5342 insn2 = emit_insn (gen_umk_lalm (operands[0], operands[0], operands[1]));
5343 insn3 = emit_insn (gen_umk_lal (operands[0], operands[0], operands[1]));
5344 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
5346 if (GET_CODE (operands[1]) == LABEL_REF)
5350 label = XEXP (operands[1], 0);
5351 REG_NOTES (insn1) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5353 REG_NOTES (insn2) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5355 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5357 LABEL_NUSES (label) += 3;
5362 ;; Instructions for loading the three parts of an address on Unicos/Mk.
5364 (define_insn "umk_laum"
5365 [(set (match_operand:DI 0 "register_operand" "=r")
5366 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5368 "TARGET_ABI_UNICOSMK"
5370 [(set_attr "type" "iadd")])
5372 (define_insn "umk_lalm"
5373 [(set (match_operand:DI 0 "register_operand" "=r")
5374 (plus:DI (match_operand:DI 1 "register_operand" "r")
5375 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5377 "TARGET_ABI_UNICOSMK"
5379 [(set_attr "type" "iadd")])
5381 (define_insn "umk_lal"
5382 [(set (match_operand:DI 0 "register_operand" "=r")
5383 (plus:DI (match_operand:DI 1 "register_operand" "r")
5384 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5386 "TARGET_ABI_UNICOSMK"
5388 [(set_attr "type" "iadd")])
5390 ;; Add a new call information word to the current function's list of CIWs
5391 ;; and load its index into $25. Doing it here ensures that the CIW will be
5392 ;; associated with the correct function even in the presence of inlining.
5394 (define_insn "*umk_load_ciw"
5396 (unspec:DI [(match_operand 0 "" "")] UNSPEC_UMK_LOAD_CIW))]
5397 "TARGET_ABI_UNICOSMK"
5399 operands[0] = unicosmk_add_call_info_word (operands[0]);
5400 return "lda $25,%0";
5402 [(set_attr "type" "iadd")])
5404 (define_insn "*movdi_er_low_l"
5405 [(set (match_operand:DI 0 "register_operand" "=r")
5406 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
5407 (match_operand:DI 2 "local_symbolic_operand" "")))]
5408 "TARGET_EXPLICIT_RELOCS"
5410 if (true_regnum (operands[1]) == 29)
5411 return "lda %0,%2(%1)\t\t!gprel";
5413 return "lda %0,%2(%1)\t\t!gprellow";
5415 [(set_attr "usegp" "yes")])
5418 [(set (match_operand:DI 0 "register_operand" "")
5419 (match_operand:DI 1 "small_symbolic_operand" ""))]
5420 "TARGET_EXPLICIT_RELOCS && reload_completed"
5422 (lo_sum:DI (match_dup 2) (match_dup 1)))]
5423 "operands[2] = pic_offset_table_rtx;")
5426 [(set (match_operand:DI 0 "register_operand" "")
5427 (match_operand:DI 1 "local_symbolic_operand" ""))]
5428 "TARGET_EXPLICIT_RELOCS && reload_completed"
5430 (plus:DI (match_dup 2) (high:DI (match_dup 1))))
5432 (lo_sum:DI (match_dup 0) (match_dup 1)))]
5433 "operands[2] = pic_offset_table_rtx;")
5436 [(match_operand 0 "some_small_symbolic_operand" "")]
5437 "TARGET_EXPLICIT_RELOCS && reload_completed"
5439 "operands[0] = split_small_symbolic_operand (operands[0]);")
5441 ;; Accepts any symbolic, not just global, since function calls that
5442 ;; don't go via bsr still use !literal in hopes of linker relaxation.
5443 (define_insn "movdi_er_high_g"
5444 [(set (match_operand:DI 0 "register_operand" "=r")
5445 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5446 (match_operand:DI 2 "symbolic_operand" "")
5447 (match_operand 3 "const_int_operand" "")]
5449 "TARGET_EXPLICIT_RELOCS"
5451 if (INTVAL (operands[3]) == 0)
5452 return "ldq %0,%2(%1)\t\t!literal";
5454 return "ldq %0,%2(%1)\t\t!literal!%3";
5456 [(set_attr "type" "ldsym")])
5459 [(set (match_operand:DI 0 "register_operand" "")
5460 (match_operand:DI 1 "global_symbolic_operand" ""))]
5461 "TARGET_EXPLICIT_RELOCS && reload_completed"
5463 (unspec:DI [(match_dup 2)
5465 (const_int 0)] UNSPEC_LITERAL))]
5466 "operands[2] = pic_offset_table_rtx;")
5468 ;; With RTL inlining, at -O3, rtl is generated, stored, then actually
5469 ;; compiled at the end of compilation. In the meantime, someone can
5470 ;; re-encode-section-info on some symbol changing it e.g. from global
5471 ;; to local-not-small. If this happens, we'd have emitted a plain
5472 ;; load rather than a high+losum load and not recognize the insn.
5474 ;; So if rtl inlining is in effect, we delay the global/not-global
5475 ;; decision until rest_of_compilation by wrapping it in an UNSPEC_SYMBOL.
5477 (define_insn_and_split "movdi_er_maybe_g"
5478 [(set (match_operand:DI 0 "register_operand" "=r")
5479 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5481 "TARGET_EXPLICIT_RELOCS && flag_inline_functions"
5484 [(set (match_dup 0) (match_dup 1))]
5486 if (local_symbolic_operand (operands[1], Pmode)
5487 && !small_symbolic_operand (operands[1], Pmode))
5489 rtx subtarget = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
5492 tmp = gen_rtx_HIGH (Pmode, operands[1]);
5493 if (reload_completed)
5494 tmp = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmp);
5495 emit_insn (gen_rtx_SET (VOIDmode, subtarget, tmp));
5497 tmp = gen_rtx_LO_SUM (Pmode, subtarget, operands[1]);
5498 emit_insn (gen_rtx_SET (VOIDmode, operands[0], tmp));
5503 (define_insn "movdi_er_tlsgd"
5504 [(set (match_operand:DI 0 "register_operand" "=r")
5505 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5506 (match_operand:DI 2 "symbolic_operand" "")
5507 (match_operand 3 "const_int_operand" "")]
5511 if (INTVAL (operands[3]) == 0)
5512 return "lda %0,%2(%1)\t\t!tlsgd";
5514 return "lda %0,%2(%1)\t\t!tlsgd!%3";
5517 (define_insn "movdi_er_tlsldm"
5518 [(set (match_operand:DI 0 "register_operand" "=r")
5519 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5520 (match_operand 2 "const_int_operand" "")]
5524 if (INTVAL (operands[2]) == 0)
5525 return "lda %0,%&(%1)\t\t!tlsldm";
5527 return "lda %0,%&(%1)\t\t!tlsldm!%2";
5530 (define_insn "*movdi_er_gotdtp"
5531 [(set (match_operand:DI 0 "register_operand" "=r")
5532 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5533 (match_operand:DI 2 "symbolic_operand" "")]
5536 "ldq %0,%2(%1)\t\t!gotdtprel"
5537 [(set_attr "type" "ild")
5538 (set_attr "usegp" "yes")])
5541 [(set (match_operand:DI 0 "register_operand" "")
5542 (match_operand:DI 1 "gotdtp_symbolic_operand" ""))]
5543 "HAVE_AS_TLS && reload_completed"
5545 (unspec:DI [(match_dup 2)
5546 (match_dup 1)] UNSPEC_DTPREL))]
5548 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5549 operands[2] = pic_offset_table_rtx;
5552 (define_insn "*movdi_er_gottp"
5553 [(set (match_operand:DI 0 "register_operand" "=r")
5554 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5555 (match_operand:DI 2 "symbolic_operand" "")]
5558 "ldq %0,%2(%1)\t\t!gottprel"
5559 [(set_attr "type" "ild")
5560 (set_attr "usegp" "yes")])
5563 [(set (match_operand:DI 0 "register_operand" "")
5564 (match_operand:DI 1 "gottp_symbolic_operand" ""))]
5565 "HAVE_AS_TLS && reload_completed"
5567 (unspec:DI [(match_dup 2)
5568 (match_dup 1)] UNSPEC_TPREL))]
5570 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5571 operands[2] = pic_offset_table_rtx;
5574 (define_insn "*movdi_er_nofix"
5575 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
5576 (match_operand:DI 1 "input_operand" "rJ,K,L,T,s,m,rJ,*fJ,Q,*f"))]
5577 "TARGET_EXPLICIT_RELOCS && ! TARGET_FIX
5578 && (register_operand (operands[0], DImode)
5579 || reg_or_0_operand (operands[1], DImode))"
5591 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")
5592 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*")])
5594 ;; The 'U' constraint matches symbolic operands on Unicos/Mk. Those should
5595 ;; have been split up by the rules above but we shouldn't reject the
5596 ;; possibility of them getting through.
5598 (define_insn "*movdi_nofix"
5599 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
5600 (match_operand:DI 1 "input_operand" "rJ,K,L,U,s,m,rJ,*fJ,Q,*f"))]
5602 && (register_operand (operands[0], DImode)
5603 || reg_or_0_operand (operands[1], DImode))"
5608 laum %0,%t1($31)\;sll %0,32,%0\;lalm %0,%t1(%0)\;lal %0,%t1(%0)
5615 [(set_attr "type" "ilog,iadd,iadd,ldsym,ldsym,ild,ist,fcpys,fld,fst")
5616 (set_attr "length" "*,*,*,16,*,*,*,*,*,*")])
5618 (define_insn "*movdi_er_fix"
5619 [(set (match_operand:DI 0 "nonimmediate_operand"
5620 "=r,r,r,r,r,r, m, *f,*f, Q, r,*f")
5621 (match_operand:DI 1 "input_operand"
5622 "rJ,K,L,T,s,m,rJ,*fJ, Q,*f,*f, r"))]
5623 "TARGET_EXPLICIT_RELOCS && TARGET_FIX
5624 && (register_operand (operands[0], DImode)
5625 || reg_or_0_operand (operands[1], DImode))"
5639 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")
5640 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*,*")])
5642 (define_insn "*movdi_fix"
5643 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f")
5644 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f,*f,r"))]
5645 "! TARGET_EXPLICIT_RELOCS && TARGET_FIX
5646 && (register_operand (operands[0], DImode)
5647 || reg_or_0_operand (operands[1], DImode))"
5660 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5662 ;; VMS needs to set up "vms_base_regno" for unwinding. This move
5663 ;; often appears dead to the life analysis code, at which point we
5664 ;; abort for emitting dead prologue instructions. Force this live.
5666 (define_insn "force_movdi"
5667 [(set (match_operand:DI 0 "register_operand" "=r")
5668 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")]
5669 UNSPECV_FORCE_MOV))]
5672 [(set_attr "type" "ilog")])
5674 ;; We do three major things here: handle mem->mem, put 64-bit constants in
5675 ;; memory, and construct long 32-bit constants.
5677 (define_expand "movdi"
5678 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5679 (match_operand:DI 1 "general_operand" ""))]
5682 if (alpha_expand_mov (DImode, operands))
5686 ;; Split a load of a large constant into the appropriate two-insn
5690 [(set (match_operand:DI 0 "register_operand" "")
5691 (match_operand:DI 1 "const_int_operand" ""))]
5692 "! add_operand (operands[1], DImode)"
5693 [(set (match_dup 0) (match_dup 2))
5694 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
5697 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
5699 if (tem == operands[0])
5705 ;; These are the partial-word cases.
5707 ;; First we have the code to load an aligned word. Operand 0 is the register
5708 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
5709 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
5710 ;; number of bits within the word that the value is. Operand 3 is an SImode
5711 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
5712 ;; same register. It is allowed to conflict with operand 1 as well.
5714 (define_expand "aligned_loadqi"
5715 [(set (match_operand:SI 3 "register_operand" "")
5716 (match_operand:SI 1 "memory_operand" ""))
5717 (set (match_operand:DI 0 "register_operand" "")
5718 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5720 (match_operand:DI 2 "const_int_operand" "")))]
5725 (define_expand "aligned_loadhi"
5726 [(set (match_operand:SI 3 "register_operand" "")
5727 (match_operand:SI 1 "memory_operand" ""))
5728 (set (match_operand:DI 0 "register_operand" "")
5729 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5731 (match_operand:DI 2 "const_int_operand" "")))]
5736 ;; Similar for unaligned loads, where we use the sequence from the
5737 ;; Alpha Architecture manual. We have to distinguish between little-endian
5738 ;; and big-endian systems as the sequences are different.
5740 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
5741 ;; operand 3 can overlap the input and output registers.
5743 (define_expand "unaligned_loadqi"
5744 [(use (match_operand:DI 0 "register_operand" ""))
5745 (use (match_operand:DI 1 "address_operand" ""))
5746 (use (match_operand:DI 2 "register_operand" ""))
5747 (use (match_operand:DI 3 "register_operand" ""))]
5750 if (WORDS_BIG_ENDIAN)
5751 emit_insn (gen_unaligned_loadqi_be (operands[0], operands[1],
5752 operands[2], operands[3]));
5754 emit_insn (gen_unaligned_loadqi_le (operands[0], operands[1],
5755 operands[2], operands[3]));
5759 (define_expand "unaligned_loadqi_le"
5760 [(set (match_operand:DI 2 "register_operand" "")
5761 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5763 (set (match_operand:DI 3 "register_operand" "")
5765 (set (match_operand:DI 0 "register_operand" "")
5766 (zero_extract:DI (match_dup 2)
5768 (ashift:DI (match_dup 3) (const_int 3))))]
5769 "! WORDS_BIG_ENDIAN"
5772 (define_expand "unaligned_loadqi_be"
5773 [(set (match_operand:DI 2 "register_operand" "")
5774 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5776 (set (match_operand:DI 3 "register_operand" "")
5778 (set (match_operand:DI 0 "register_operand" "")
5779 (zero_extract:DI (match_dup 2)
5783 (ashift:DI (match_dup 3) (const_int 3)))))]
5787 (define_expand "unaligned_loadhi"
5788 [(use (match_operand:DI 0 "register_operand" ""))
5789 (use (match_operand:DI 1 "address_operand" ""))
5790 (use (match_operand:DI 2 "register_operand" ""))
5791 (use (match_operand:DI 3 "register_operand" ""))]
5794 if (WORDS_BIG_ENDIAN)
5795 emit_insn (gen_unaligned_loadhi_be (operands[0], operands[1],
5796 operands[2], operands[3]));
5798 emit_insn (gen_unaligned_loadhi_le (operands[0], operands[1],
5799 operands[2], operands[3]));
5803 (define_expand "unaligned_loadhi_le"
5804 [(set (match_operand:DI 2 "register_operand" "")
5805 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5807 (set (match_operand:DI 3 "register_operand" "")
5809 (set (match_operand:DI 0 "register_operand" "")
5810 (zero_extract:DI (match_dup 2)
5812 (ashift:DI (match_dup 3) (const_int 3))))]
5813 "! WORDS_BIG_ENDIAN"
5816 (define_expand "unaligned_loadhi_be"
5817 [(set (match_operand:DI 2 "register_operand" "")
5818 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5820 (set (match_operand:DI 3 "register_operand" "")
5821 (plus:DI (match_dup 1) (const_int 1)))
5822 (set (match_operand:DI 0 "register_operand" "")
5823 (zero_extract:DI (match_dup 2)
5827 (ashift:DI (match_dup 3) (const_int 3)))))]
5831 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
5832 ;; aligned SImode MEM. Operand 1 is the register containing the
5833 ;; byte or word to store. Operand 2 is the number of bits within the word that
5834 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
5836 (define_expand "aligned_store"
5837 [(set (match_operand:SI 3 "register_operand" "")
5838 (match_operand:SI 0 "memory_operand" ""))
5839 (set (subreg:DI (match_dup 3) 0)
5840 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
5841 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
5842 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
5843 (match_operand:DI 2 "const_int_operand" "")))
5844 (set (subreg:DI (match_dup 4) 0)
5845 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
5846 (set (match_dup 0) (match_dup 4))]
5849 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
5850 << INTVAL (operands[2])));
5853 ;; For the unaligned byte and halfword cases, we use code similar to that
5854 ;; in the ;; Architecture book, but reordered to lower the number of registers
5855 ;; required. Operand 0 is the address. Operand 1 is the data to store.
5856 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
5857 ;; be the same temporary, if desired. If the address is in a register,
5858 ;; operand 2 can be that register.
5860 (define_expand "unaligned_storeqi"
5861 [(use (match_operand:DI 0 "address_operand" ""))
5862 (use (match_operand:QI 1 "register_operand" ""))
5863 (use (match_operand:DI 2 "register_operand" ""))
5864 (use (match_operand:DI 3 "register_operand" ""))
5865 (use (match_operand:DI 4 "register_operand" ""))]
5868 if (WORDS_BIG_ENDIAN)
5869 emit_insn (gen_unaligned_storeqi_be (operands[0], operands[1],
5870 operands[2], operands[3],
5873 emit_insn (gen_unaligned_storeqi_le (operands[0], operands[1],
5874 operands[2], operands[3],
5879 (define_expand "unaligned_storeqi_le"
5880 [(set (match_operand:DI 3 "register_operand" "")
5881 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5883 (set (match_operand:DI 2 "register_operand" "")
5886 (and:DI (not:DI (ashift:DI (const_int 255)
5887 (ashift:DI (match_dup 2) (const_int 3))))
5889 (set (match_operand:DI 4 "register_operand" "")
5890 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5891 (ashift:DI (match_dup 2) (const_int 3))))
5892 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5893 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5895 "! WORDS_BIG_ENDIAN"
5898 (define_expand "unaligned_storeqi_be"
5899 [(set (match_operand:DI 3 "register_operand" "")
5900 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5902 (set (match_operand:DI 2 "register_operand" "")
5905 (and:DI (not:DI (ashift:DI (const_int 255)
5906 (minus:DI (const_int 56)
5907 (ashift:DI (match_dup 2) (const_int 3)))))
5909 (set (match_operand:DI 4 "register_operand" "")
5910 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5911 (minus:DI (const_int 56)
5912 (ashift:DI (match_dup 2) (const_int 3)))))
5913 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5914 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5919 (define_expand "unaligned_storehi"
5920 [(use (match_operand:DI 0 "address_operand" ""))
5921 (use (match_operand:HI 1 "register_operand" ""))
5922 (use (match_operand:DI 2 "register_operand" ""))
5923 (use (match_operand:DI 3 "register_operand" ""))
5924 (use (match_operand:DI 4 "register_operand" ""))]
5927 if (WORDS_BIG_ENDIAN)
5928 emit_insn (gen_unaligned_storehi_be (operands[0], operands[1],
5929 operands[2], operands[3],
5932 emit_insn (gen_unaligned_storehi_le (operands[0], operands[1],
5933 operands[2], operands[3],
5938 (define_expand "unaligned_storehi_le"
5939 [(set (match_operand:DI 3 "register_operand" "")
5940 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5942 (set (match_operand:DI 2 "register_operand" "")
5945 (and:DI (not:DI (ashift:DI (const_int 65535)
5946 (ashift:DI (match_dup 2) (const_int 3))))
5948 (set (match_operand:DI 4 "register_operand" "")
5949 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5950 (ashift:DI (match_dup 2) (const_int 3))))
5951 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5952 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5954 "! WORDS_BIG_ENDIAN"
5957 (define_expand "unaligned_storehi_be"
5958 [(set (match_operand:DI 3 "register_operand" "")
5959 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5961 (set (match_operand:DI 2 "register_operand" "")
5962 (plus:DI (match_dup 0) (const_int 1)))
5964 (and:DI (not:DI (ashift:DI
5966 (minus:DI (const_int 56)
5967 (ashift:DI (match_dup 2) (const_int 3)))))
5969 (set (match_operand:DI 4 "register_operand" "")
5970 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5971 (minus:DI (const_int 56)
5972 (ashift:DI (match_dup 2) (const_int 3)))))
5973 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5974 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5979 ;; Here are the define_expand's for QI and HI moves that use the above
5980 ;; patterns. We have the normal sets, plus the ones that need scratch
5981 ;; registers for reload.
5983 (define_expand "movqi"
5984 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5985 (match_operand:QI 1 "general_operand" ""))]
5989 ? alpha_expand_mov (QImode, operands)
5990 : alpha_expand_mov_nobwx (QImode, operands))
5994 (define_expand "movhi"
5995 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5996 (match_operand:HI 1 "general_operand" ""))]
6000 ? alpha_expand_mov (HImode, operands)
6001 : alpha_expand_mov_nobwx (HImode, operands))
6005 ;; Here are the versions for reload. Note that in the unaligned cases
6006 ;; we know that the operand must not be a pseudo-register because stack
6007 ;; slots are always aligned references.
6009 (define_expand "reload_inqi"
6010 [(parallel [(match_operand:QI 0 "register_operand" "=r")
6011 (match_operand:QI 1 "any_memory_operand" "m")
6012 (match_operand:TI 2 "register_operand" "=&r")])]
6017 if (aligned_memory_operand (operands[1], QImode))
6019 seq = gen_reload_inqi_help (operands[0], operands[1],
6020 gen_rtx_REG (SImode, REGNO (operands[2])));
6026 /* It is possible that one of the registers we got for operands[2]
6027 might coincide with that of operands[0] (which is why we made
6028 it TImode). Pick the other one to use as our scratch. */
6029 if (REGNO (operands[0]) == REGNO (operands[2]))
6030 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6032 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
6034 addr = get_unaligned_address (operands[1], 0);
6035 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
6036 seq = gen_unaligned_loadqi (operands[0], addr, scratch, operands[0]);
6037 alpha_set_memflags (seq, operands[1]);
6043 (define_expand "reload_inhi"
6044 [(parallel [(match_operand:HI 0 "register_operand" "=r")
6045 (match_operand:HI 1 "any_memory_operand" "m")
6046 (match_operand:TI 2 "register_operand" "=&r")])]
6051 if (aligned_memory_operand (operands[1], HImode))
6053 seq = gen_reload_inhi_help (operands[0], operands[1],
6054 gen_rtx_REG (SImode, REGNO (operands[2])));
6060 /* It is possible that one of the registers we got for operands[2]
6061 might coincide with that of operands[0] (which is why we made
6062 it TImode). Pick the other one to use as our scratch. */
6063 if (REGNO (operands[0]) == REGNO (operands[2]))
6064 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6066 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
6068 addr = get_unaligned_address (operands[1], 0);
6069 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
6070 seq = gen_unaligned_loadhi (operands[0], addr, scratch, operands[0]);
6071 alpha_set_memflags (seq, operands[1]);
6077 (define_expand "reload_outqi"
6078 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
6079 (match_operand:QI 1 "register_operand" "r")
6080 (match_operand:TI 2 "register_operand" "=&r")])]
6083 if (aligned_memory_operand (operands[0], QImode))
6085 emit_insn (gen_reload_outqi_help
6086 (operands[0], operands[1],
6087 gen_rtx_REG (SImode, REGNO (operands[2])),
6088 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6092 rtx addr = get_unaligned_address (operands[0], 0);
6093 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6094 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6095 rtx scratch3 = scratch1;
6098 if (GET_CODE (addr) == REG)
6101 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
6102 scratch2, scratch3);
6103 alpha_set_memflags (seq, operands[0]);
6109 (define_expand "reload_outhi"
6110 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
6111 (match_operand:HI 1 "register_operand" "r")
6112 (match_operand:TI 2 "register_operand" "=&r")])]
6115 if (aligned_memory_operand (operands[0], HImode))
6117 emit_insn (gen_reload_outhi_help
6118 (operands[0], operands[1],
6119 gen_rtx_REG (SImode, REGNO (operands[2])),
6120 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6124 rtx addr = get_unaligned_address (operands[0], 0);
6125 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6126 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6127 rtx scratch3 = scratch1;
6130 if (GET_CODE (addr) == REG)
6133 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
6134 scratch2, scratch3);
6135 alpha_set_memflags (seq, operands[0]);
6141 ;; Helpers for the above. The way reload is structured, we can't
6142 ;; always get a proper address for a stack slot during reload_foo
6143 ;; expansion, so we must delay our address manipulations until after.
6145 (define_insn_and_split "reload_inqi_help"
6146 [(set (match_operand:QI 0 "register_operand" "=r")
6147 (match_operand:QI 1 "memory_operand" "m"))
6148 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6149 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6151 "! TARGET_BWX && reload_completed"
6154 rtx aligned_mem, bitnum;
6155 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6156 operands[0] = gen_lowpart (DImode, operands[0]);
6157 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
6162 (define_insn_and_split "reload_inhi_help"
6163 [(set (match_operand:HI 0 "register_operand" "=r")
6164 (match_operand:HI 1 "memory_operand" "m"))
6165 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6166 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6168 "! TARGET_BWX && reload_completed"
6171 rtx aligned_mem, bitnum;
6172 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6173 operands[0] = gen_lowpart (DImode, operands[0]);
6174 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
6179 (define_insn_and_split "reload_outqi_help"
6180 [(set (match_operand:QI 0 "memory_operand" "=m")
6181 (match_operand:QI 1 "register_operand" "r"))
6182 (clobber (match_operand:SI 2 "register_operand" "=r"))
6183 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6184 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6186 "! TARGET_BWX && reload_completed"
6189 rtx aligned_mem, bitnum;
6190 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6191 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6192 operands[2], operands[3]));
6196 (define_insn_and_split "reload_outhi_help"
6197 [(set (match_operand:HI 0 "memory_operand" "=m")
6198 (match_operand:HI 1 "register_operand" "r"))
6199 (clobber (match_operand:SI 2 "register_operand" "=r"))
6200 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6201 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6203 "! TARGET_BWX && reload_completed"
6206 rtx aligned_mem, bitnum;
6207 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6208 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6209 operands[2], operands[3]));
6213 ;; Vector operations
6215 (define_expand "movv8qi"
6216 [(set (match_operand:V8QI 0 "nonimmediate_operand" "")
6217 (match_operand:V8QI 1 "general_operand" ""))]
6220 if (alpha_expand_mov (V8QImode, operands))
6224 (define_insn "*movv8qi_fix"
6225 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f")
6226 (match_operand:V8QI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))]
6228 && (register_operand (operands[0], V8QImode)
6229 || reg_or_0_operand (operands[1], V8QImode))"
6239 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")])
6241 (define_insn "*movv8qi_nofix"
6242 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m")
6243 (match_operand:V8QI 1 "input_operand" "rW,m,rW,*fW,m,*f"))]
6245 && (register_operand (operands[0], V8QImode)
6246 || reg_or_0_operand (operands[1], V8QImode))"
6254 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")])
6256 (define_expand "movv4hi"
6257 [(set (match_operand:V4HI 0 "nonimmediate_operand" "")
6258 (match_operand:V4HI 1 "general_operand" ""))]
6261 if (alpha_expand_mov (V4HImode, operands))
6265 (define_insn "*movv4hi_fix"
6266 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f")
6267 (match_operand:V4HI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))]
6269 && (register_operand (operands[0], V4HImode)
6270 || reg_or_0_operand (operands[1], V4HImode))"
6280 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")])
6282 (define_insn "*movv4hi_nofix"
6283 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m")
6284 (match_operand:V4HI 1 "input_operand" "rW,m,rW,*fW,m,*f"))]
6286 && (register_operand (operands[0], V4HImode)
6287 || reg_or_0_operand (operands[1], V4HImode))"
6295 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")])
6297 (define_expand "movv2si"
6298 [(set (match_operand:V2SI 0 "nonimmediate_operand" "")
6299 (match_operand:V2SI 1 "general_operand" ""))]
6302 if (alpha_expand_mov (V2SImode, operands))
6306 (define_insn "*movv2si_fix"
6307 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f")
6308 (match_operand:V2SI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))]
6310 && (register_operand (operands[0], V2SImode)
6311 || reg_or_0_operand (operands[1], V2SImode))"
6321 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")])
6323 (define_insn "*movv2si_nofix"
6324 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m")
6325 (match_operand:V2SI 1 "input_operand" "rW,m,rW,*fW,m,*f"))]
6327 && (register_operand (operands[0], V2SImode)
6328 || reg_or_0_operand (operands[1], V2SImode))"
6336 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")])
6338 (define_insn "uminv8qi3"
6339 [(set (match_operand:V8QI 0 "register_operand" "=r")
6340 (umin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6341 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6344 [(set_attr "type" "mvi")])
6346 (define_insn "sminv8qi3"
6347 [(set (match_operand:V8QI 0 "register_operand" "=r")
6348 (smin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6349 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6352 [(set_attr "type" "mvi")])
6354 (define_insn "uminv4hi3"
6355 [(set (match_operand:V4HI 0 "register_operand" "=r")
6356 (umin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6357 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6360 [(set_attr "type" "mvi")])
6362 (define_insn "sminv4hi3"
6363 [(set (match_operand:V4HI 0 "register_operand" "=r")
6364 (smin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6365 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6368 [(set_attr "type" "mvi")])
6370 (define_insn "umaxv8qi3"
6371 [(set (match_operand:V8QI 0 "register_operand" "=r")
6372 (umax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6373 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6376 [(set_attr "type" "mvi")])
6378 (define_insn "smaxv8qi3"
6379 [(set (match_operand:V8QI 0 "register_operand" "=r")
6380 (smax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6381 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6384 [(set_attr "type" "mvi")])
6386 (define_insn "umaxv4hi3"
6387 [(set (match_operand:V4HI 0 "register_operand" "=r")
6388 (umax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6389 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6392 [(set_attr "type" "mvi")])
6394 (define_insn "smaxv4hi3"
6395 [(set (match_operand:V4HI 0 "register_operand" "=r")
6396 (smax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6397 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6400 [(set_attr "type" "mvi")])
6402 ;; Bit field extract patterns which use ext[wlq][lh]
6404 (define_expand "extv"
6405 [(set (match_operand:DI 0 "register_operand" "")
6406 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
6407 (match_operand:DI 2 "immediate_operand" "")
6408 (match_operand:DI 3 "immediate_operand" "")))]
6413 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6414 if (INTVAL (operands[3]) % 8 != 0
6415 || (INTVAL (operands[2]) != 16
6416 && INTVAL (operands[2]) != 32
6417 && INTVAL (operands[2]) != 64))
6420 /* From mips.md: extract_bit_field doesn't verify that our source
6421 matches the predicate, so we force it to be a MEM here. */
6422 if (GET_CODE (operands[1]) != MEM)
6425 /* The bit number is relative to the mode of operand 1 which is
6426 usually QImode (this might actually be a bug in expmed.c). Note
6427 that the bit number is negative in big-endian mode in this case.
6428 We have to convert that to the offset. */
6429 if (WORDS_BIG_ENDIAN)
6430 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6431 - INTVAL (operands[2]) - INTVAL (operands[3]);
6433 ofs = INTVAL (operands[3]);
6437 alpha_expand_unaligned_load (operands[0], operands[1],
6438 INTVAL (operands[2]) / 8,
6443 (define_expand "extzv"
6444 [(set (match_operand:DI 0 "register_operand" "")
6445 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
6446 (match_operand:DI 2 "immediate_operand" "")
6447 (match_operand:DI 3 "immediate_operand" "")))]
6450 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6451 if (INTVAL (operands[3]) % 8 != 0
6452 || (INTVAL (operands[2]) != 8
6453 && INTVAL (operands[2]) != 16
6454 && INTVAL (operands[2]) != 32
6455 && INTVAL (operands[2]) != 64))
6458 if (GET_CODE (operands[1]) == MEM)
6462 /* Fail 8 bit fields, falling back on a simple byte load. */
6463 if (INTVAL (operands[2]) == 8)
6466 /* The bit number is relative to the mode of operand 1 which is
6467 usually QImode (this might actually be a bug in expmed.c). Note
6468 that the bit number is negative in big-endian mode in this case.
6469 We have to convert that to the offset. */
6470 if (WORDS_BIG_ENDIAN)
6471 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6472 - INTVAL (operands[2]) - INTVAL (operands[3]);
6474 ofs = INTVAL (operands[3]);
6478 alpha_expand_unaligned_load (operands[0], operands[1],
6479 INTVAL (operands[2]) / 8,
6485 (define_expand "insv"
6486 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
6487 (match_operand:DI 1 "immediate_operand" "")
6488 (match_operand:DI 2 "immediate_operand" ""))
6489 (match_operand:DI 3 "register_operand" ""))]
6494 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6495 if (INTVAL (operands[2]) % 8 != 0
6496 || (INTVAL (operands[1]) != 16
6497 && INTVAL (operands[1]) != 32
6498 && INTVAL (operands[1]) != 64))
6501 /* From mips.md: store_bit_field doesn't verify that our source
6502 matches the predicate, so we force it to be a MEM here. */
6503 if (GET_CODE (operands[0]) != MEM)
6506 /* The bit number is relative to the mode of operand 1 which is
6507 usually QImode (this might actually be a bug in expmed.c). Note
6508 that the bit number is negative in big-endian mode in this case.
6509 We have to convert that to the offset. */
6510 if (WORDS_BIG_ENDIAN)
6511 ofs = GET_MODE_BITSIZE (GET_MODE (operands[0]))
6512 - INTVAL (operands[1]) - INTVAL (operands[2]);
6514 ofs = INTVAL (operands[2]);
6518 alpha_expand_unaligned_store (operands[0], operands[3],
6519 INTVAL (operands[1]) / 8, ofs);
6523 ;; Block move/clear, see alpha.c for more details.
6524 ;; Argument 0 is the destination
6525 ;; Argument 1 is the source
6526 ;; Argument 2 is the length
6527 ;; Argument 3 is the alignment
6529 (define_expand "movstrqi"
6530 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6531 (match_operand:BLK 1 "memory_operand" ""))
6532 (use (match_operand:DI 2 "immediate_operand" ""))
6533 (use (match_operand:DI 3 "immediate_operand" ""))])]
6536 if (alpha_expand_block_move (operands))
6542 (define_expand "movstrdi"
6543 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6544 (match_operand:BLK 1 "memory_operand" ""))
6545 (use (match_operand:DI 2 "immediate_operand" ""))
6546 (use (match_operand:DI 3 "immediate_operand" ""))
6548 (clobber (reg:DI 25))
6549 (clobber (reg:DI 16))
6550 (clobber (reg:DI 17))
6551 (clobber (reg:DI 18))
6552 (clobber (reg:DI 19))
6553 (clobber (reg:DI 20))
6554 (clobber (reg:DI 26))
6555 (clobber (reg:DI 27))])]
6556 "TARGET_ABI_OPEN_VMS"
6558 operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$MOVE");
6559 alpha_need_linkage (XSTR (operands[4], 0), 0);
6562 (define_insn "*movstrdi_1"
6563 [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
6564 (match_operand:BLK 1 "memory_operand" "m,m"))
6565 (use (match_operand:DI 2 "nonmemory_operand" "r,i"))
6566 (use (match_operand:DI 3 "immediate_operand" ""))
6567 (use (match_operand:DI 4 "call_operand" "i,i"))
6568 (clobber (reg:DI 25))
6569 (clobber (reg:DI 16))
6570 (clobber (reg:DI 17))
6571 (clobber (reg:DI 18))
6572 (clobber (reg:DI 19))
6573 (clobber (reg:DI 20))
6574 (clobber (reg:DI 26))
6575 (clobber (reg:DI 27))]
6576 "TARGET_ABI_OPEN_VMS"
6578 operands [5] = alpha_use_linkage (operands [4], cfun->decl, 0, 1);
6579 switch (which_alternative)
6582 return "lda $16,%0\;bis $31,%2,$17\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
6584 return "lda $16,%0\;lda $17,%2($31)\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
6589 [(set_attr "type" "multi")
6590 (set_attr "length" "28")])
6592 (define_expand "clrstrqi"
6593 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6595 (use (match_operand:DI 1 "immediate_operand" ""))
6596 (use (match_operand:DI 2 "immediate_operand" ""))])]
6599 if (alpha_expand_block_clear (operands))
6605 (define_expand "clrstrdi"
6606 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6608 (use (match_operand:DI 1 "immediate_operand" ""))
6609 (use (match_operand:DI 2 "immediate_operand" ""))
6611 (clobber (reg:DI 25))
6612 (clobber (reg:DI 16))
6613 (clobber (reg:DI 17))
6614 (clobber (reg:DI 26))
6615 (clobber (reg:DI 27))])]
6616 "TARGET_ABI_OPEN_VMS"
6618 operands[3] = gen_rtx_SYMBOL_REF (Pmode, "OTS$ZERO");
6619 alpha_need_linkage (XSTR (operands[3], 0), 0);
6622 (define_insn "*clrstrdi_1"
6623 [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
6625 (use (match_operand:DI 1 "nonmemory_operand" "r,i"))
6626 (use (match_operand:DI 2 "immediate_operand" ""))
6627 (use (match_operand:DI 3 "call_operand" "i,i"))
6628 (clobber (reg:DI 25))
6629 (clobber (reg:DI 16))
6630 (clobber (reg:DI 17))
6631 (clobber (reg:DI 26))
6632 (clobber (reg:DI 27))]
6633 "TARGET_ABI_OPEN_VMS"
6635 operands [4] = alpha_use_linkage (operands [3], cfun->decl, 0, 1);
6636 switch (which_alternative)
6639 return "lda $16,%0\;bis $31,%1,$17\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
6641 return "lda $16,%0\;lda $17,%1($31)\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
6646 [(set_attr "type" "multi")
6647 (set_attr "length" "24")])
6650 ;; Subroutine of stack space allocation. Perform a stack probe.
6651 (define_expand "probe_stack"
6652 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
6655 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
6656 INTVAL (operands[0])));
6657 MEM_VOLATILE_P (operands[1]) = 1;
6659 operands[0] = const0_rtx;
6662 ;; This is how we allocate stack space. If we are allocating a
6663 ;; constant amount of space and we know it is less than 4096
6664 ;; bytes, we need do nothing.
6666 ;; If it is more than 4096 bytes, we need to probe the stack
6668 (define_expand "allocate_stack"
6670 (plus:DI (reg:DI 30)
6671 (match_operand:DI 1 "reg_or_cint_operand" "")))
6672 (set (match_operand:DI 0 "register_operand" "=r")
6676 if (GET_CODE (operands[1]) == CONST_INT
6677 && INTVAL (operands[1]) < 32768)
6679 if (INTVAL (operands[1]) >= 4096)
6681 /* We do this the same way as in the prologue and generate explicit
6682 probes. Then we update the stack by the constant. */
6686 emit_insn (gen_probe_stack (GEN_INT (- probed)));
6687 while (probed + 8192 < INTVAL (operands[1]))
6688 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
6690 if (probed + 4096 < INTVAL (operands[1]))
6691 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
6694 operands[1] = GEN_INT (- INTVAL (operands[1]));
6695 operands[2] = virtual_stack_dynamic_rtx;
6700 rtx loop_label = gen_label_rtx ();
6701 rtx want = gen_reg_rtx (Pmode);
6702 rtx tmp = gen_reg_rtx (Pmode);
6705 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
6706 force_reg (Pmode, operands[1])));
6707 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
6709 if (GET_CODE (operands[1]) != CONST_INT)
6711 out_label = gen_label_rtx ();
6712 emit_insn (gen_cmpdi (want, tmp));
6713 emit_jump_insn (gen_bgeu (out_label));
6716 emit_label (loop_label);
6717 memref = gen_rtx_MEM (DImode, tmp);
6718 MEM_VOLATILE_P (memref) = 1;
6719 emit_move_insn (memref, const0_rtx);
6720 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
6721 emit_insn (gen_cmpdi (tmp, want));
6722 emit_jump_insn (gen_bgtu (loop_label));
6724 memref = gen_rtx_MEM (DImode, want);
6725 MEM_VOLATILE_P (memref) = 1;
6726 emit_move_insn (memref, const0_rtx);
6729 emit_label (out_label);
6731 emit_move_insn (stack_pointer_rtx, want);
6732 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6737 ;; This is used by alpha_expand_prolog to do the same thing as above,
6738 ;; except we cannot at that time generate new basic blocks, so we hide
6739 ;; the loop in this one insn.
6741 (define_insn "prologue_stack_probe_loop"
6742 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
6743 (match_operand:DI 1 "register_operand" "r")]
6747 operands[2] = gen_label_rtx ();
6748 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6749 CODE_LABEL_NUMBER (operands[2]));
6751 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2";
6753 [(set_attr "length" "16")
6754 (set_attr "type" "multi")])
6756 (define_expand "prologue"
6757 [(clobber (const_int 0))]
6760 alpha_expand_prologue ();
6764 ;; These take care of emitting the ldgp insn in the prologue. This will be
6765 ;; an lda/ldah pair and we want to align them properly. So we have two
6766 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
6767 ;; and the second of which emits nothing. However, both are marked as type
6768 ;; IADD (the default) so the alignment code in alpha.c does the right thing
6771 (define_expand "prologue_ldgp"
6773 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6775 (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))]
6778 operands[0] = pic_offset_table_rtx;
6779 operands[1] = gen_rtx_REG (Pmode, 27);
6780 operands[2] = (TARGET_EXPLICIT_RELOCS
6781 ? GEN_INT (alpha_next_sequence_number++)
6785 (define_insn "*ldgp_er_1"
6786 [(set (match_operand:DI 0 "register_operand" "=r")
6787 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6788 (match_operand 2 "const_int_operand" "")]
6790 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6791 "ldah %0,0(%1)\t\t!gpdisp!%2"
6792 [(set_attr "cannot_copy" "true")])
6794 (define_insn "*ldgp_er_2"
6795 [(set (match_operand:DI 0 "register_operand" "=r")
6796 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
6797 (match_operand 2 "const_int_operand" "")]
6799 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6800 "lda %0,0(%1)\t\t!gpdisp!%2"
6801 [(set_attr "cannot_copy" "true")])
6803 (define_insn "*prologue_ldgp_er_2"
6804 [(set (match_operand:DI 0 "register_operand" "=r")
6805 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6806 (match_operand 2 "const_int_operand" "")]
6808 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6809 "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:"
6810 [(set_attr "cannot_copy" "true")])
6812 (define_insn "*prologue_ldgp_1"
6813 [(set (match_operand:DI 0 "register_operand" "=r")
6814 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6815 (match_operand 2 "const_int_operand" "")]
6818 "ldgp %0,0(%1)\n$%~..ng:"
6819 [(set_attr "cannot_copy" "true")])
6821 (define_insn "*prologue_ldgp_2"
6822 [(set (match_operand:DI 0 "register_operand" "=r")
6823 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6824 (match_operand 2 "const_int_operand" "")]
6829 ;; The _mcount profiling hook has special calling conventions, and
6830 ;; does not clobber all the registers that a normal call would. So
6831 ;; hide the fact this is a call at all.
6833 (define_insn "prologue_mcount"
6834 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)]
6837 if (TARGET_EXPLICIT_RELOCS)
6838 /* Note that we cannot use a lituse_jsr reloc, since _mcount
6839 cannot be called via the PLT. */
6840 return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount";
6842 return "lda $28,_mcount\;jsr $28,($28),_mcount";
6844 [(set_attr "type" "multi")
6845 (set_attr "length" "8")])
6847 (define_insn "init_fp"
6848 [(set (match_operand:DI 0 "register_operand" "=r")
6849 (match_operand:DI 1 "register_operand" "r"))
6850 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
6854 (define_expand "epilogue"
6858 alpha_expand_epilogue ();
6861 (define_expand "sibcall_epilogue"
6865 alpha_expand_epilogue ();
6869 (define_expand "builtin_longjmp"
6870 [(use (match_operand:DI 0 "register_operand" "r"))]
6873 /* The elements of the buffer are, in order: */
6874 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6875 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
6876 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
6877 rtx pv = gen_rtx_REG (Pmode, 27);
6879 /* This bit is the same as expand_builtin_longjmp. */
6880 emit_move_insn (hard_frame_pointer_rtx, fp);
6881 emit_move_insn (pv, lab);
6882 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6883 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6884 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6886 /* Load the label we are jumping through into $27 so that we know
6887 where to look for it when we get back to setjmp's function for
6888 restoring the gp. */
6889 emit_jump_insn (gen_builtin_longjmp_internal (pv));
6894 ;; This is effectively a copy of indirect_jump, but constrained such
6895 ;; that register renaming cannot foil our cunning plan with $27.
6896 (define_insn "builtin_longjmp_internal"
6898 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
6902 [(set_attr "type" "ibr")])
6904 (define_expand "builtin_setjmp_receiver"
6905 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6909 (define_insn_and_split "*builtin_setjmp_receiver_1"
6910 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR)]
6913 if (TARGET_EXPLICIT_RELOCS)
6916 return "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)";
6918 "&& TARGET_EXPLICIT_RELOCS && reload_completed"
6919 [(unspec_volatile [(match_dup 0)] UNSPECV_SETJMPR_ER)
6921 (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1))
6923 (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))]
6925 operands[1] = pic_offset_table_rtx;
6926 operands[2] = gen_rtx_REG (Pmode, 27);
6927 operands[3] = GEN_INT (alpha_next_sequence_number++);
6929 [(set_attr "length" "12")
6930 (set_attr "type" "multi")])
6932 (define_insn "*builtin_setjmp_receiver_er_sl_1"
6933 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR_ER)]
6934 "TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS && TARGET_AS_CAN_SUBTRACT_LABELS"
6935 "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:")
6937 (define_insn "*builtin_setjmp_receiver_er_1"
6938 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR_ER)]
6939 "TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS"
6940 "br $27,$LSJ%=\n$LSJ%=:"
6941 [(set_attr "type" "ibr")])
6943 (define_expand "exception_receiver"
6944 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)]
6947 if (TARGET_LD_BUGGY_LDGP)
6948 operands[0] = alpha_gp_save_rtx ();
6950 operands[0] = const0_rtx;
6953 (define_insn "*exception_receiver_2"
6954 [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)]
6955 "TARGET_ABI_OSF && TARGET_LD_BUGGY_LDGP"
6957 [(set_attr "type" "ild")])
6959 (define_insn_and_split "*exception_receiver_1"
6960 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)]
6963 if (TARGET_EXPLICIT_RELOCS)
6964 return "ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*";
6966 return "ldgp $29,0($26)";
6968 "&& TARGET_EXPLICIT_RELOCS && reload_completed"
6970 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6972 (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))]
6974 operands[0] = pic_offset_table_rtx;
6975 operands[1] = gen_rtx_REG (Pmode, 26);
6976 operands[2] = GEN_INT (alpha_next_sequence_number++);
6978 [(set_attr "length" "8")
6979 (set_attr "type" "multi")])
6981 (define_expand "nonlocal_goto_receiver"
6982 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6983 (set (reg:DI 27) (mem:DI (reg:DI 29)))
6984 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6986 "TARGET_ABI_OPEN_VMS"
6989 (define_insn "arg_home"
6990 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
7005 (clobber (mem:BLK (const_int 0)))
7006 (clobber (reg:DI 24))
7007 (clobber (reg:DI 25))
7008 (clobber (reg:DI 0))]
7009 "TARGET_ABI_OPEN_VMS"
7010 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
7011 [(set_attr "length" "16")
7012 (set_attr "type" "multi")])
7014 ;; Load the CIW into r2 for calling __T3E_MISMATCH
7016 (define_expand "umk_mismatch_args"
7017 [(set:DI (match_dup 1) (mem:DI (plus:DI (reg:DI 15) (const_int -16))))
7018 (set:DI (match_dup 2) (mem:DI (plus:DI (match_dup 1) (const_int -32))))
7019 (set:DI (reg:DI 1) (match_operand:DI 0 "const_int_operand" ""))
7020 (set:DI (match_dup 3) (plus:DI (mult:DI (reg:DI 25)
7023 (set:DI (reg:DI 2) (mem:DI (match_dup 3)))]
7024 "TARGET_ABI_UNICOSMK"
7026 operands[1] = gen_reg_rtx (DImode);
7027 operands[2] = gen_reg_rtx (DImode);
7028 operands[3] = gen_reg_rtx (DImode);
7031 (define_insn "arg_home_umk"
7032 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
7047 (clobber (mem:BLK (const_int 0)))
7049 (clobber (reg:DI 22))
7050 (clobber (reg:DI 23))
7051 (clobber (reg:DI 24))
7052 (clobber (reg:DI 0))
7053 (clobber (reg:DI 1))
7054 (clobber (reg:DI 2))
7055 (clobber (reg:DI 3))
7056 (clobber (reg:DI 4))
7057 (clobber (reg:DI 5))
7058 (clobber (reg:DI 6))
7059 (clobber (reg:DI 7))
7060 (clobber (reg:DI 8))])]
7061 "TARGET_ABI_UNICOSMK"
7062 "laum $4,__T3E_MISMATCH($31)\;sll $4,32,$4\;lalm $4,__T3E_MISMATCH($4)\;lal $4,__T3E_MISMATCH($4)\;jsr $3,($4)"
7063 [(set_attr "length" "16")
7064 (set_attr "type" "multi")])
7068 ;; On EV4, these instructions are nops -- no load occurs.
7070 ;; On EV5, these instructions act as a normal load, and thus can trap
7071 ;; if the address is invalid. The OS may (or may not) handle this in
7072 ;; the entMM fault handler and suppress the fault. If so, then this
7073 ;; has the effect of a read prefetch instruction.
7075 ;; On EV6, these become official prefetch instructions.
7077 (define_insn "prefetch"
7078 [(prefetch (match_operand:DI 0 "address_operand" "p")
7079 (match_operand:DI 1 "const_int_operand" "n")
7080 (match_operand:DI 2 "const_int_operand" "n"))]
7081 "TARGET_FIXUP_EV5_PREFETCH || TARGET_CPU_EV6"
7083 /* Interpret "no temporal locality" as this data should be evicted once
7084 it is used. The "evict next" alternatives load the data into the cache
7085 and leave the LRU eviction counter pointing to that block. */
7086 static const char * const alt[2][2] = {
7088 "ldq $31,%a0", /* read, evict next */
7089 "ldl $31,%a0", /* read, evict last */
7092 "ldt $f31,%a0", /* write, evict next */
7093 "lds $f31,%a0", /* write, evict last */
7097 bool write = INTVAL (operands[1]) != 0;
7098 bool lru = INTVAL (operands[2]) != 0;
7100 return alt[write][lru];
7102 [(set_attr "type" "ild")])
7104 ;; Close the trap shadow of preceding instructions. This is generated
7107 (define_insn "trapb"
7108 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)]
7111 [(set_attr "type" "misc")])
7113 ;; No-op instructions used by machine-dependent reorg to preserve
7114 ;; alignment for instruction issue.
7115 ;; The Unicos/Mk assembler does not support these opcodes.
7121 [(set_attr "type" "ilog")])
7126 "cpys $f31,$f31,$f31"
7127 [(set_attr "type" "fcpys")])
7134 ;; On Unicos/Mk we use a macro for aligning code.
7136 (define_insn "realign"
7137 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")]
7141 if (TARGET_ABI_UNICOSMK)
7142 return "gcc@code@align %0";
7144 return ".align %0 #realign";
7147 ;; Instructions to be emitted from __builtins.
7149 (define_insn "builtin_cmpbge"
7150 [(set (match_operand:DI 0 "register_operand" "=r")
7151 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rJ")
7152 (match_operand:DI 2 "reg_or_8bit_operand" "rI")]
7156 ;; The EV6 data sheets list this as ILOG. OTOH, EV6 doesn't
7157 ;; actually differentiate between ILOG and ICMP in the schedule.
7158 [(set_attr "type" "icmp")])
7160 (define_expand "builtin_extbl"
7161 [(match_operand:DI 0 "register_operand" "")
7162 (match_operand:DI 1 "reg_or_0_operand" "")
7163 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7166 rtx (*gen) (rtx, rtx, rtx, rtx);
7167 if (WORDS_BIG_ENDIAN)
7171 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (8), operands[2]));
7175 (define_expand "builtin_extwl"
7176 [(match_operand:DI 0 "register_operand" "")
7177 (match_operand:DI 1 "reg_or_0_operand" "")
7178 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7181 rtx (*gen) (rtx, rtx, rtx, rtx);
7182 if (WORDS_BIG_ENDIAN)
7186 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (16), operands[2]));
7190 (define_expand "builtin_extll"
7191 [(match_operand:DI 0 "register_operand" "")
7192 (match_operand:DI 1 "reg_or_0_operand" "")
7193 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7196 rtx (*gen) (rtx, rtx, rtx, rtx);
7197 if (WORDS_BIG_ENDIAN)
7201 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (32), operands[2]));
7205 (define_expand "builtin_extql"
7206 [(match_operand:DI 0 "register_operand" "")
7207 (match_operand:DI 1 "reg_or_0_operand" "")
7208 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7211 rtx (*gen) (rtx, rtx, rtx, rtx);
7212 if (WORDS_BIG_ENDIAN)
7216 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (64), operands[2]));
7220 (define_expand "builtin_extwh"
7221 [(match_operand:DI 0 "register_operand" "")
7222 (match_operand:DI 1 "reg_or_0_operand" "")
7223 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7226 rtx (*gen) (rtx, rtx, rtx);
7227 if (WORDS_BIG_ENDIAN)
7231 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7235 (define_expand "builtin_extlh"
7236 [(match_operand:DI 0 "register_operand" "")
7237 (match_operand:DI 1 "reg_or_0_operand" "")
7238 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7241 rtx (*gen) (rtx, rtx, rtx);
7242 if (WORDS_BIG_ENDIAN)
7246 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7250 (define_expand "builtin_extqh"
7251 [(match_operand:DI 0 "register_operand" "")
7252 (match_operand:DI 1 "reg_or_0_operand" "")
7253 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7256 rtx (*gen) (rtx, rtx, rtx);
7257 if (WORDS_BIG_ENDIAN)
7261 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7265 (define_expand "builtin_insbl"
7266 [(match_operand:DI 0 "register_operand" "")
7267 (match_operand:DI 1 "reg_or_0_operand" "")
7268 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7271 rtx (*gen) (rtx, rtx, rtx);
7272 if (WORDS_BIG_ENDIAN)
7276 operands[1] = gen_lowpart (QImode, operands[1]);
7277 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7281 (define_expand "builtin_inswl"
7282 [(match_operand:DI 0 "register_operand" "")
7283 (match_operand:DI 1 "reg_or_0_operand" "")
7284 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7287 rtx (*gen) (rtx, rtx, rtx);
7288 if (WORDS_BIG_ENDIAN)
7292 operands[1] = gen_lowpart (HImode, operands[1]);
7293 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7297 (define_expand "builtin_insll"
7298 [(match_operand:DI 0 "register_operand" "")
7299 (match_operand:DI 1 "reg_or_0_operand" "")
7300 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7303 rtx (*gen) (rtx, rtx, rtx);
7304 if (WORDS_BIG_ENDIAN)
7308 operands[1] = gen_lowpart (SImode, operands[1]);
7309 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7310 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7314 (define_expand "builtin_insql"
7315 [(match_operand:DI 0 "register_operand" "")
7316 (match_operand:DI 1 "reg_or_0_operand" "")
7317 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7320 rtx (*gen) (rtx, rtx, rtx);
7321 if (WORDS_BIG_ENDIAN)
7325 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7329 (define_expand "builtin_inswh"
7330 [(match_operand:DI 0 "register_operand" "")
7331 (match_operand:DI 1 "register_operand" "")
7332 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7335 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2]));
7339 (define_expand "builtin_inslh"
7340 [(match_operand:DI 0 "register_operand" "")
7341 (match_operand:DI 1 "register_operand" "")
7342 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7345 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2]));
7349 (define_expand "builtin_insqh"
7350 [(match_operand:DI 0 "register_operand" "")
7351 (match_operand:DI 1 "register_operand" "")
7352 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7355 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2]));
7359 (define_expand "builtin_mskbl"
7360 [(match_operand:DI 0 "register_operand" "")
7361 (match_operand:DI 1 "reg_or_0_operand" "")
7362 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7365 rtx (*gen) (rtx, rtx, rtx, rtx);
7367 if (WORDS_BIG_ENDIAN)
7371 mask = GEN_INT (0xff);
7372 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7376 (define_expand "builtin_mskwl"
7377 [(match_operand:DI 0 "register_operand" "")
7378 (match_operand:DI 1 "reg_or_0_operand" "")
7379 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7382 rtx (*gen) (rtx, rtx, rtx, rtx);
7384 if (WORDS_BIG_ENDIAN)
7388 mask = GEN_INT (0xffff);
7389 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7393 (define_expand "builtin_mskll"
7394 [(match_operand:DI 0 "register_operand" "")
7395 (match_operand:DI 1 "reg_or_0_operand" "")
7396 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7399 rtx (*gen) (rtx, rtx, rtx, rtx);
7401 if (WORDS_BIG_ENDIAN)
7405 mask = immed_double_const (0xffffffff, 0, DImode);
7406 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7410 (define_expand "builtin_mskql"
7411 [(match_operand:DI 0 "register_operand" "")
7412 (match_operand:DI 1 "reg_or_0_operand" "")
7413 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7416 rtx (*gen) (rtx, rtx, rtx, rtx);
7418 if (WORDS_BIG_ENDIAN)
7423 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7427 (define_expand "builtin_mskwh"
7428 [(match_operand:DI 0 "register_operand" "")
7429 (match_operand:DI 1 "register_operand" "")
7430 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7433 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2]));
7437 (define_expand "builtin_msklh"
7438 [(match_operand:DI 0 "register_operand" "")
7439 (match_operand:DI 1 "register_operand" "")
7440 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7443 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2]));
7447 (define_expand "builtin_mskqh"
7448 [(match_operand:DI 0 "register_operand" "")
7449 (match_operand:DI 1 "register_operand" "")
7450 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7453 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2]));
7457 (define_expand "builtin_zap"
7458 [(set (match_operand:DI 0 "register_operand" "")
7460 [(match_operand:DI 2 "reg_or_const_int_operand" "")]
7462 (match_operand:DI 1 "reg_or_const_int_operand" "")))]
7465 if (GET_CODE (operands[2]) == CONST_INT)
7467 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7469 if (mask == const0_rtx)
7471 emit_move_insn (operands[0], const0_rtx);
7474 if (mask == constm1_rtx)
7476 emit_move_insn (operands[0], operands[1]);
7480 operands[1] = force_reg (DImode, operands[1]);
7481 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7485 operands[1] = force_reg (DImode, operands[1]);
7486 operands[2] = gen_lowpart (QImode, operands[2]);
7489 (define_insn "*builtin_zap_1"
7490 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
7492 [(match_operand:QI 2 "reg_or_const_int_operand" "n,n,r,r")]
7494 (match_operand:DI 1 "reg_or_const_int_operand" "n,r,J,r")))]
7501 [(set_attr "type" "shift,shift,ilog,shift")])
7504 [(set (match_operand:DI 0 "register_operand" "")
7506 [(match_operand:QI 2 "const_int_operand" "")]
7508 (match_operand:DI 1 "const_int_operand" "")))]
7512 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7513 if (HOST_BITS_PER_WIDE_INT >= 64 || GET_CODE (mask) == CONST_INT)
7514 operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode);
7517 HOST_WIDE_INT c_lo = INTVAL (operands[1]);
7518 HOST_WIDE_INT c_hi = (c_lo < 0 ? -1 : 0);
7519 operands[1] = immed_double_const (c_lo & CONST_DOUBLE_LOW (mask),
7520 c_hi & CONST_DOUBLE_HIGH (mask),
7523 emit_move_insn (operands[0], operands[1]);
7528 [(set (match_operand:DI 0 "register_operand" "")
7530 [(match_operand:QI 2 "const_int_operand" "")]
7532 (match_operand:DI 1 "register_operand" "")))]
7535 (and:DI (match_dup 1) (match_dup 2)))]
7537 operands[2] = alpha_expand_zap_mask (INTVAL (operands[2]));
7538 if (operands[2] == const0_rtx)
7540 emit_move_insn (operands[0], const0_rtx);
7543 if (operands[2] == constm1_rtx)
7545 emit_move_insn (operands[0], operands[1]);
7550 (define_expand "builtin_zapnot"
7551 [(set (match_operand:DI 0 "register_operand" "")
7553 [(not:QI (match_operand:DI 2 "reg_or_const_int_operand" ""))]
7555 (match_operand:DI 1 "reg_or_const_int_operand" "")))]
7558 if (GET_CODE (operands[2]) == CONST_INT)
7560 rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2]));
7562 if (mask == const0_rtx)
7564 emit_move_insn (operands[0], const0_rtx);
7567 if (mask == constm1_rtx)
7569 emit_move_insn (operands[0], operands[1]);
7573 operands[1] = force_reg (DImode, operands[1]);
7574 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7578 operands[1] = force_reg (DImode, operands[1]);
7579 operands[2] = gen_lowpart (QImode, operands[2]);
7582 (define_insn "*builtin_zapnot_1"
7583 [(set (match_operand:DI 0 "register_operand" "=r")
7585 [(not:QI (match_operand:QI 2 "register_operand" "r"))]
7587 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
7590 [(set_attr "type" "shift")])
7592 (define_insn "builtin_amask"
7593 [(set (match_operand:DI 0 "register_operand" "=r")
7594 (unspec:DI [(match_operand:DI 1 "reg_or_8bit_operand" "rI")]
7598 [(set_attr "type" "ilog")])
7600 (define_insn "builtin_implver"
7601 [(set (match_operand:DI 0 "register_operand" "=r")
7602 (unspec:DI [(const_int 0)] UNSPEC_IMPLVER))]
7605 [(set_attr "type" "ilog")])
7607 (define_insn "builtin_rpcc"
7608 [(set (match_operand:DI 0 "register_operand" "=r")
7609 (unspec_volatile:DI [(const_int 0)] UNSPECV_RPCC))]
7612 [(set_attr "type" "ilog")])
7614 (define_expand "builtin_minub8"
7615 [(match_operand:DI 0 "register_operand" "")
7616 (match_operand:DI 1 "reg_or_0_operand" "")
7617 (match_operand:DI 2 "reg_or_0_operand" "")]
7620 alpha_expand_builtin_vector_binop (gen_uminv8qi3, V8QImode, operands[0],
7621 operands[1], operands[2]);
7625 (define_expand "builtin_minsb8"
7626 [(match_operand:DI 0 "register_operand" "")
7627 (match_operand:DI 1 "reg_or_0_operand" "")
7628 (match_operand:DI 2 "reg_or_0_operand" "")]
7631 alpha_expand_builtin_vector_binop (gen_sminv8qi3, V8QImode, operands[0],
7632 operands[1], operands[2]);
7636 (define_expand "builtin_minuw4"
7637 [(match_operand:DI 0 "register_operand" "")
7638 (match_operand:DI 1 "reg_or_0_operand" "")
7639 (match_operand:DI 2 "reg_or_0_operand" "")]
7642 alpha_expand_builtin_vector_binop (gen_uminv4hi3, V4HImode, operands[0],
7643 operands[1], operands[2]);
7647 (define_expand "builtin_minsw4"
7648 [(match_operand:DI 0 "register_operand" "")
7649 (match_operand:DI 1 "reg_or_0_operand" "")
7650 (match_operand:DI 2 "reg_or_0_operand" "")]
7653 alpha_expand_builtin_vector_binop (gen_sminv4hi3, V4HImode, operands[0],
7654 operands[1], operands[2]);
7658 (define_expand "builtin_maxub8"
7659 [(match_operand:DI 0 "register_operand" "")
7660 (match_operand:DI 1 "reg_or_0_operand" "")
7661 (match_operand:DI 2 "reg_or_0_operand" "")]
7664 alpha_expand_builtin_vector_binop (gen_umaxv8qi3, V8QImode, operands[0],
7665 operands[1], operands[2]);
7669 (define_expand "builtin_maxsb8"
7670 [(match_operand:DI 0 "register_operand" "")
7671 (match_operand:DI 1 "reg_or_0_operand" "")
7672 (match_operand:DI 2 "reg_or_0_operand" "")]
7675 alpha_expand_builtin_vector_binop (gen_smaxv8qi3, V8QImode, operands[0],
7676 operands[1], operands[2]);
7680 (define_expand "builtin_maxuw4"
7681 [(match_operand:DI 0 "register_operand" "")
7682 (match_operand:DI 1 "reg_or_0_operand" "")
7683 (match_operand:DI 2 "reg_or_0_operand" "")]
7686 alpha_expand_builtin_vector_binop (gen_umaxv4hi3, V4HImode, operands[0],
7687 operands[1], operands[2]);
7691 (define_expand "builtin_maxsw4"
7692 [(match_operand:DI 0 "register_operand" "")
7693 (match_operand:DI 1 "reg_or_0_operand" "")
7694 (match_operand:DI 2 "reg_or_0_operand" "")]
7697 alpha_expand_builtin_vector_binop (gen_smaxv4hi3, V4HImode, operands[0],
7698 operands[1], operands[2]);
7702 (define_insn "builtin_perr"
7703 [(set (match_operand:DI 0 "register_operand" "=r")
7704 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "%rJ")
7705 (match_operand:DI 2 "reg_or_8bit_operand" "rJ")]
7709 [(set_attr "type" "mvi")])
7711 (define_expand "builtin_pklb"
7712 [(set (match_operand:DI 0 "register_operand" "")
7715 (truncate:V2QI (match_operand:DI 1 "register_operand" ""))
7720 operands[0] = gen_lowpart (V8QImode, operands[0]);
7721 operands[1] = gen_lowpart (V2SImode, operands[1]);
7722 operands[2] = CONST0_RTX (V2QImode);
7723 operands[3] = CONST0_RTX (V4QImode);
7726 (define_insn "*pklb"
7727 [(set (match_operand:V8QI 0 "register_operand" "=r")
7730 (truncate:V2QI (match_operand:V2SI 1 "register_operand" "r"))
7731 (match_operand:V2QI 2 "const0_operand" ""))
7732 (match_operand:V4QI 3 "const0_operand" "")))]
7735 [(set_attr "type" "mvi")])
7737 (define_expand "builtin_pkwb"
7738 [(set (match_operand:DI 0 "register_operand" "")
7740 (truncate:V4QI (match_operand:DI 1 "register_operand" ""))
7744 operands[0] = gen_lowpart (V8QImode, operands[0]);
7745 operands[1] = gen_lowpart (V4HImode, operands[1]);
7746 operands[2] = CONST0_RTX (V4QImode);
7749 (define_insn "*pkwb"
7750 [(set (match_operand:V8QI 0 "register_operand" "=r")
7752 (truncate:V4QI (match_operand:V4HI 1 "register_operand" "r"))
7753 (match_operand:V4QI 2 "const0_operand" "")))]
7756 [(set_attr "type" "mvi")])
7758 (define_expand "builtin_unpkbl"
7759 [(set (match_operand:DI 0 "register_operand" "")
7761 (vec_select:V2QI (match_operand:DI 1 "register_operand" "")
7762 (parallel [(const_int 0) (const_int 1)]))))]
7765 operands[0] = gen_lowpart (V2SImode, operands[0]);
7766 operands[1] = gen_lowpart (V8QImode, operands[1]);
7769 (define_insn "*unpkbl"
7770 [(set (match_operand:V2SI 0 "register_operand" "=r")
7772 (vec_select:V2QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7773 (parallel [(const_int 0) (const_int 1)]))))]
7776 [(set_attr "type" "mvi")])
7778 (define_expand "builtin_unpkbw"
7779 [(set (match_operand:DI 0 "register_operand" "")
7781 (vec_select:V4QI (match_operand:DI 1 "register_operand" "")
7782 (parallel [(const_int 0)
7788 operands[0] = gen_lowpart (V4HImode, operands[0]);
7789 operands[1] = gen_lowpart (V8QImode, operands[1]);
7792 (define_insn "*unpkbw"
7793 [(set (match_operand:V4HI 0 "register_operand" "=r")
7795 (vec_select:V4QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7796 (parallel [(const_int 0)
7802 [(set_attr "type" "mvi")])
7804 (define_expand "builtin_cttz"
7805 [(set (match_operand:DI 0 "register_operand" "")
7806 (unspec:DI [(match_operand:DI 1 "register_operand" "")]
7811 (define_insn "builtin_ctlz"
7812 [(set (match_operand:DI 0 "register_operand" "=r")
7813 (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
7817 [(set_attr "type" "mvi")])
7819 (define_insn "builtin_ctpop"
7820 [(set (match_operand:DI 0 "register_operand" "=r")
7821 (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
7825 [(set_attr "type" "mvi")])
7827 ;; The call patterns are at the end of the file because their
7828 ;; wildcard operand0 interferes with nice recognition.
7830 (define_insn "*call_value_osf_1_er"
7831 [(set (match_operand 0 "" "")
7832 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7833 (match_operand 2 "" "")))
7835 (clobber (reg:DI 26))]
7836 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7838 jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
7839 bsr $26,%1\t\t!samegp
7840 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
7841 [(set_attr "type" "jsr")
7842 (set_attr "length" "12,*,16")])
7844 ;; We must use peep2 instead of a split because we need accurate life
7845 ;; information for $gp. Consider the case of { bar(); while (1); }.
7847 [(parallel [(set (match_operand 0 "" "")
7848 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7849 (match_operand 2 "" "")))
7851 (clobber (reg:DI 26))])]
7852 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7853 && ! samegp_function_operand (operands[1], Pmode)
7854 && (peep2_regno_dead_p (1, 29)
7855 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
7856 [(parallel [(set (match_dup 0)
7857 (call (mem:DI (match_dup 3))
7859 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7860 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7862 (use (match_dup 4))])]
7864 if (CONSTANT_P (operands[1]))
7866 operands[3] = gen_rtx_REG (Pmode, 27);
7867 operands[4] = GEN_INT (alpha_next_sequence_number++);
7868 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
7869 operands[1], operands[4]));
7873 operands[3] = operands[1];
7874 operands[1] = const0_rtx;
7875 operands[4] = const0_rtx;
7880 [(parallel [(set (match_operand 0 "" "")
7881 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7882 (match_operand 2 "" "")))
7884 (clobber (reg:DI 26))])]
7885 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7886 && ! samegp_function_operand (operands[1], Pmode)
7887 && ! (peep2_regno_dead_p (1, 29)
7888 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
7889 [(parallel [(set (match_dup 0)
7890 (call (mem:DI (match_dup 3))
7892 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7893 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7895 (use (match_dup 5))])
7897 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7899 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
7901 if (CONSTANT_P (operands[1]))
7903 operands[3] = gen_rtx_REG (Pmode, 27);
7904 operands[5] = GEN_INT (alpha_next_sequence_number++);
7905 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
7906 operands[1], operands[5]));
7910 operands[3] = operands[1];
7911 operands[1] = const0_rtx;
7912 operands[5] = const0_rtx;
7914 operands[4] = GEN_INT (alpha_next_sequence_number++);
7917 ;; We add a blockage unspec_volatile to prevent insns from moving down
7918 ;; from above the call to in between the call and the ldah gpdisp.
7919 (define_insn "*call_value_osf_2_er"
7920 [(set (match_operand 0 "" "")
7921 (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
7922 (match_operand 2 "" "")))
7924 (plus:DI (pc) (const_int 4)))
7925 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7926 (use (match_operand 3 "" ""))
7927 (use (match_operand 4 "" ""))]
7928 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7929 "jsr $26,(%1),%3%J4"
7930 [(set_attr "type" "jsr")
7931 (set_attr "cannot_copy" "true")])
7933 (define_insn "*call_value_osf_1_noreturn"
7934 [(set (match_operand 0 "" "")
7935 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7936 (match_operand 2 "" "")))
7938 (clobber (reg:DI 26))]
7939 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
7940 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7945 [(set_attr "type" "jsr")
7946 (set_attr "length" "*,*,8")])
7948 (define_insn_and_split "call_value_osf_tlsgd"
7949 [(set (match_operand 0 "" "")
7950 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
7952 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSGD_CALL)
7954 (clobber (reg:DI 26))]
7957 "&& reload_completed"
7959 (unspec:DI [(match_dup 5)
7961 (match_dup 2)] UNSPEC_LITERAL))
7962 (parallel [(set (match_dup 0)
7963 (call (mem:DI (match_dup 3))
7965 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7966 (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
7968 (use (unspec [(match_dup 2)] UNSPEC_TLSGD_CALL))])
7970 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7972 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))]
7974 operands[3] = gen_rtx_REG (Pmode, 27);
7975 operands[4] = GEN_INT (alpha_next_sequence_number++);
7976 operands[5] = pic_offset_table_rtx;
7978 [(set_attr "type" "multi")])
7980 (define_insn_and_split "call_value_osf_tlsldm"
7981 [(set (match_operand 0 "" "")
7982 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
7984 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSLDM_CALL)
7986 (clobber (reg:DI 26))]
7989 "&& reload_completed"
7991 (unspec:DI [(match_dup 5)
7993 (match_dup 2)] UNSPEC_LITERAL))
7994 (parallel [(set (match_dup 0)
7995 (call (mem:DI (match_dup 3))
7997 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7998 (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
8000 (use (unspec [(match_dup 2)] UNSPEC_TLSLDM_CALL))])
8002 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
8004 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
8006 operands[3] = gen_rtx_REG (Pmode, 27);
8007 operands[4] = GEN_INT (alpha_next_sequence_number++);
8008 operands[5] = pic_offset_table_rtx;
8010 [(set_attr "type" "multi")])
8012 (define_insn "*call_value_osf_1"
8013 [(set (match_operand 0 "" "")
8014 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
8015 (match_operand 2 "" "")))
8017 (clobber (reg:DI 26))]
8018 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
8020 jsr $26,($27),0\;ldgp $29,0($26)
8022 jsr $26,%1\;ldgp $29,0($26)"
8023 [(set_attr "type" "jsr")
8024 (set_attr "length" "12,*,16")])
8026 (define_insn "*sibcall_value_osf_1_er"
8027 [(set (match_operand 0 "" "")
8028 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
8029 (match_operand 2 "" "")))
8030 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
8031 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
8033 br $31,%1\t\t!samegp
8034 ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#"
8035 [(set_attr "type" "jsr")
8036 (set_attr "length" "*,8")])
8038 (define_insn "*sibcall_value_osf_1"
8039 [(set (match_operand 0 "" "")
8040 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
8041 (match_operand 2 "" "")))
8042 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
8043 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
8046 lda $27,%1\;jmp $31,($27),%1"
8047 [(set_attr "type" "jsr")
8048 (set_attr "length" "*,8")])
8050 (define_insn "*call_value_nt_1"
8051 [(set (match_operand 0 "" "")
8052 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,s"))
8053 (match_operand 2 "" "")))
8054 (clobber (reg:DI 26))]
8055 "TARGET_ABI_WINDOWS_NT"
8060 [(set_attr "type" "jsr")
8061 (set_attr "length" "*,*,12")])
8063 ; GAS relies on the order and position of instructions output below in order
8064 ; to generate relocs for VMS link to potentially optimize the call.
8065 ; Please do not molest.
8066 (define_insn "*call_value_vms_1"
8067 [(set (match_operand 0 "" "")
8068 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s"))
8069 (match_operand 2 "" "")))
8070 (use (match_operand:DI 3 "nonmemory_operand" "r,n"))
8073 (clobber (reg:DI 27))]
8074 "TARGET_ABI_OPEN_VMS"
8076 switch (which_alternative)
8079 return "mov %3,$27\;jsr $26,0\;ldq $27,0($29)";
8081 operands [3] = alpha_use_linkage (operands [1], cfun->decl, 1, 0);
8082 operands [4] = alpha_use_linkage (operands [1], cfun->decl, 0, 0);
8083 return "ldq $26,%4\;ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)";
8088 [(set_attr "type" "jsr")
8089 (set_attr "length" "12,16")])
8091 (define_insn "*call_value_umk"
8092 [(set (match_operand 0 "" "")
8093 (call (mem:DI (match_operand:DI 1 "call_operand" "r"))
8094 (match_operand 2 "" "")))
8096 (clobber (reg:DI 26))]
8097 "TARGET_ABI_UNICOSMK"
8099 [(set_attr "type" "jsr")])