1 /* $NetBSD: rpb.h,v 1.20 1998/04/15 00:47:33 mjacob Exp $ */
5 * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
8 * Author: Keith Bostic, Chris G. Demetriou
10 * Permission to use, copy, modify and distribute this software and
11 * its documentation is hereby granted, provided that both the copyright
12 * notice and this permission notice appear in all copies of the
13 * software, derivative works or modified versions, and any portions
14 * thereof, and that both notices appear in supporting documentation.
16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
18 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
20 * Carnegie Mellon requests users of this software to return to
22 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
23 * School of Computer Science
24 * Carnegie Mellon University
25 * Pittsburgh PA 15213-3890
27 * any improvements or extensions that they make and grant Carnegie the
28 * rights to redistribute these changes.
32 * From DEC 3000 300/400/500/600/700/800/900 System Programmer's Manual,
37 * HWRPB (Hardware Restart Parameter Block).
39 #define HWRPB_ADDR 0x10000000 /* virtual address, at boot */
43 u_int64_t rpb_phys; /* 0: HWRPB phys. address. */
44 char rpb_magic[8]; /* 8: "HWRPB" (in ASCII) */
45 u_int64_t rpb_version; /* 10 */
46 u_int64_t rpb_size; /* 18: HWRPB size in bytes */
47 u_int64_t rpb_primary_cpu_id; /* 20 */
48 u_int64_t rpb_page_size; /* 28: (8192) */
49 u_int64_t rpb_phys_addr_size; /* 30: (34) */
50 u_int64_t rpb_max_asn; /* 38: (16) */
51 char rpb_ssn[16]; /* 40: only first 10 valid */
53 #define ST_ADU 1 /* Alpha Demo. Unit */
54 #define ST_DEC_4000 2 /* "Cobra/Fang" (?) */
55 #define ST_DEC_7000 3 /* "Ruby/Laser" (?) */
56 #define ST_DEC_3000_500 4 /* "Flamingo" family (TC) */
57 /* 5 = "Mannequin" simulator */
58 #define ST_DEC_2000_300 6 /* "Jensen" (EISA/ISA) */
59 #define ST_DEC_3000_300 7 /* "Pelican" (TC) */
60 #define ST_AVALON_A12 8 /* XXX Avalon Multicomputer */
61 #define ST_DEC_2100_A500 9 /* "Sable" (EISA/PCI) */
62 #define ST_DEC_APXVME_64 10 /* "AXPvme" (VME) */
63 #define ST_DEC_AXPPCI_33 11 /* "NoName" (PCI/ISA/PCMCIA) */
64 #define ST_DEC_21000 12 /* "TurboLaser" (PCI/EISA) */
65 #define ST_DEC_2100_A50 13 /* "Avanti" (PCI/ISA) */
66 #define ST_DEC_MUSTANG 14 /* "Mustang" (?) */
67 #define ST_DEC_KN20AA 15 /* "Alcor" (PCI/EISA) */
69 #define ST_DEC_1000 17 /* "Mikasa" (PCI/EISA) */
70 #define ST_DEC_EB64 18 /* EB64 (PCI/ISA?) */
71 #define ST_EB66 19 /* EB66 (PCI/ISA?) */
72 #define ST_EB64P 20 /* EB64+ (PCI/ISA?) */
73 #define ST_ALPHABOOK1 21 /* Alphabook (?) */
74 #define ST_DEC_4100 22 /* "Rawhide" (PCI/EISA) */
75 #define ST_DEC_EV45_PBP 23 /* "K2" (PCI/ISA) */
76 #define ST_DEC_2100A_A500 24 /* "Lynx" (EISA/PCI) */
77 #define ST_DEC_ALPHAXL 25 /* AlphaXL (PCI/ISA) */
78 #define ST_EB164 26 /* EB164 (PCI/ISA) */
79 #define ST_DEC_1000A 27 /* "Noritake" (PCI/EISA) */
80 #define ST_DEC_ALPHAVME_224 28 /* "Cortex" (VME) */
82 #define ST_DEC_550 30 /* "Miata" (PCI/ISA) */
83 #define ST_DEC_XXM 31 /* "XXM" ?? */
84 #define ST_DEC_EV56_PBP 32 /* "Takara" (PCI/ISA) */
85 #define ST_DEC_ALPHAVME_320 33 /* "Yukon" (VME) */
86 #define ST_DEC_6600 34 /* "Tsunami/Typhoon" (PCI) */
87 #define ST_DEC_WILDFIRE 35 /* "Wildfire" (PCI)" */
88 #define ST_DEC_CUSCO 36 /* "Cusco" */
89 #define ST_DEC_EIGER 37 /* "Eiger" */
90 #define ST_DEC_TITAN 38 /* "Titan" ES45 (PCI) */
91 #define ST_DEC_MARVEL 39 /* "Marvel" (PCI) */
92 /* 40 = "Phoenix" (cPCI) */
95 * System types for Alpha Processor Inc. machines
98 #define API_ST_BASE 200
99 #define ST_API_UP1000 201 /* "Nautilus" */
101 u_int64_t rpb_type; /* 50: */
103 #define SV_MPCAP 0x00000001 /* multiprocessor capable */
105 #define SV_CONSOLE 0x0000001e /* console hardware mask */
106 #define SV_CONSOLE_DETACHED 0x00000002
107 #define SV_CONSOLE_EMBEDDED 0x00000004
109 #define SV_POWERFAIL 0x000000e0 /* powerfail mask */
110 #define SV_PF_UNITED 0x00000020
111 #define SV_PF_SEPARATE 0x00000040
112 #define SV_PF_BBACKUP 0x00000060
113 #define SV_PF_ACTION 0x00000100 /* powerfail restart */
115 #define SV_GRAPHICS 0x00000200 /* graphic engine present */
117 #define SV_ST_MASK 0x0000fc00 /* system type mask */
118 #define SV_ST_RESERVED 0x00000000 /* RESERVED */
121 * System types for the DEC 3000/500 (Flamingo) Family
123 #define SV_ST_SANDPIPER 0x00000400 /* Sandpiper; 3000/400 */
124 #define SV_ST_FLAMINGO 0x00000800 /* Flamingo; 3000/500 */
125 #define SV_ST_HOTPINK 0x00000c00 /* "Hot Pink"; 3000/500X */
126 #define SV_ST_FLAMINGOPLUS 0x00001000 /* Flamingo+; 3000/800 */
127 #define SV_ST_ULTRA 0x00001400 /* "Ultra", aka Flamingo+ */
128 #define SV_ST_SANDPLUS 0x00001800 /* Sandpiper+; 3000/600 */
129 #define SV_ST_SANDPIPER45 0x00001c00 /* Sandpiper45; 3000/700 */
130 #define SV_ST_FLAMINGO45 0x00002000 /* Flamingo45; 3000/900 */
135 #define SV_ST_SABLE 0x00000400 /* Sable (?) */
138 * System types for the DEC 3000/300 (Pelican) Family
140 #define SV_ST_PELICAN 0x00000000 /* Pelican; 3000/300 */
141 #define SV_ST_PELICA 0x00000400 /* Pelica; 3000/300L */
142 #define SV_ST_PELICANPLUS 0x00000800 /* Pelican+; 3000/300X */
143 #define SV_ST_PELICAPLUS 0x00000c00 /* Pelica+; 3000/300LX */
146 * System types for the AlphaStation Family
148 #define SV_ST_AVANTI 0x00000000 /* Avanti; 400 4/233 */
149 #define SV_ST_MUSTANG2_4_166 0x00000800 /* Mustang II; 200 4/166 */
150 #define SV_ST_MUSTANG2_4_233 0x00001000 /* Mustang II; 200 4/233 */
151 #define SV_ST_AVANTI_XXX 0x00001400 /* also Avanti; 400 4/233 */
152 #define SV_ST_AVANTI_4_266 0x00002000
153 #define SV_ST_MUSTANG2_4_100 0x00002400 /* Mustang II; 200 4/100 */
154 #define SV_ST_AVANTI_4_233 0x0000a800 /* AlphaStation 255/233 */
156 #define SV_ST_KN20AA 0x00000400 /* AlphaStation 500/600 */
159 * System types for the AXPvme Family
161 #define SV_ST_AXPVME_64 0x00000000 /* 21068, 64MHz */
162 #define SV_ST_AXPVME_160 0x00000400 /* 21066, 160MHz */
163 #define SV_ST_AXPVME_100 0x00000c00 /* 21066A, 99MHz */
164 #define SV_ST_AXPVME_230 0x00001000 /* 21066A, 231MHz */
165 #define SV_ST_AXPVME_66 0x00001400 /* 21066A, 66MHz */
166 #define SV_ST_AXPVME_166 0x00001800 /* 21066A, 165MHz */
167 #define SV_ST_AXPVME_264 0x00001c00 /* 21066A, 264MHz */
170 * System types for the EB164 Family
172 #define SV_ST_EB164_266 0x00000400 /* EB164, 266MHz */
173 #define SV_ST_EB164_300 0x00000800 /* EB164, 300MHz */
174 #define SV_ST_ALPHAPC164_366 0x00000c00 /* AlphaPC164, 366MHz */
175 #define SV_ST_ALPHAPC164_400 0x00001000 /* AlphaPC164, 400MHz */
176 #define SV_ST_ALPHAPC164_433 0x00001400 /* AlphaPC164, 433MHz */
177 #define SV_ST_ALPHAPC164_466 0x00001800 /* AlphaPC164, 466MHz */
178 #define SV_ST_ALPHAPC164_500 0x00001c00 /* AlphaPC164, 500MHz */
179 #define SV_ST_ALPHAPC164LX_400 0x00002000 /* AlphaPC164LX, 400MHz */
180 #define SV_ST_ALPHAPC164LX_466 0x00002400 /* AlphaPC164LX, 466MHz */
181 #define SV_ST_ALPHAPC164LX_533 0x00002800 /* AlphaPC164LX, 533MHz */
182 #define SV_ST_ALPHAPC164LX_600 0x00002c00 /* AlphaPC164LX, 600MHz */
183 #define SV_ST_ALPHAPC164SX_400 0x00003000 /* AlphaPC164SX, 400MHz */
184 #define SV_ST_ALPHAPC164SX_466 0x00003400 /* AlphaPC164SX, 433MHz */
185 #define SV_ST_ALPHAPC164SX_533 0x00003800 /* AlphaPC164SX, 533MHz */
186 #define SV_ST_ALPHAPC164SX_600 0x00003c00 /* AlphaPC164SX, 600MHz */
189 * System types for the Digital Personal Workstation (Miata) Family
190 * XXX These are not very complete!
192 #define SV_ST_MIATA_1_5 0x00004c00 /* Miata 1.5 */
194 u_int64_t rpb_variation; /* 58 */
196 char rpb_revision[8]; /* 60; only first 4 valid */
197 u_int64_t rpb_intr_freq; /* 68; scaled by 4096 */
198 u_int64_t rpb_cc_freq; /* 70: cycle cntr frequency */
199 vm_offset_t rpb_vptb; /* 78: */
200 u_int64_t rpb_reserved_arch; /* 80: */
201 vm_offset_t rpb_tbhint_off; /* 88: */
202 u_int64_t rpb_pcs_cnt; /* 90: */
203 u_int64_t rpb_pcs_size; /* 98; pcs size in bytes */
204 vm_offset_t rpb_pcs_off; /* A0: offset to pcs info */
205 u_int64_t rpb_ctb_cnt; /* A8: console terminal */
206 u_int64_t rpb_ctb_size; /* B0: ctb size in bytes */
207 vm_offset_t rpb_ctb_off; /* B8: offset to ctb */
208 vm_offset_t rpb_crb_off; /* C0: offset to crb */
209 vm_offset_t rpb_memdat_off; /* C8: memory data offset */
210 vm_offset_t rpb_condat_off; /* D0: config data offset */
211 vm_offset_t rpb_fru_off; /* D8: FRU table offset */
212 u_int64_t rpb_save_term; /* E0: terminal save */
213 u_int64_t rpb_save_term_val; /* E8: */
214 u_int64_t rpb_rest_term; /* F0: terminal restore */
215 u_int64_t rpb_rest_term_val; /* F8: */
216 u_int64_t rpb_restart; /* 100: restart */
217 u_int64_t rpb_restart_val; /* 108: */
218 u_int64_t rpb_reserve_os; /* 110: */
219 u_int64_t rpb_reserve_hw; /* 118: */
220 u_int64_t rpb_checksum; /* 120: HWRPB checksum */
221 u_int64_t rpb_rxrdy; /* 128: receive ready */
222 u_int64_t rpb_txrdy; /* 130: transmit ready */
223 vm_offset_t rpb_dsrdb_off; /* 138: HWRPB + DSRDB offset */
224 u_int64_t rpb_tbhint[8]; /* 149: TB hint block */
227 #define LOCATE_PCS(h,cpunumber) ((struct pcs *) \
228 ((char *)(h) + (h)->rpb_pcs_off + ((cpunumber) * (h)->rpb_pcs_size)))
231 * PCS: Per-CPU information.
235 u_int64_t pcs_hwpcb[16]; /* 0: PAL dependent */
237 #define PCS_BIP 0x000001 /* boot in progress */
238 #define PCS_RC 0x000002 /* restart possible */
239 #define PCS_PA 0x000004 /* processor available */
240 #define PCS_PP 0x000008 /* processor present */
241 #define PCS_OH 0x000010 /* user halted */
242 #define PCS_CV 0x000020 /* context valid */
243 #define PCS_PV 0x000040 /* PALcode valid */
244 #define PCS_PMV 0x000080 /* PALcode memory valid */
245 #define PCS_PL 0x000100 /* PALcode loaded */
247 #define PCS_HALT_REQ 0xff0000 /* halt request mask */
248 #define PCS_HALT_DEFAULT 0x000000
249 #define PCS_HALT_SAVE_EXIT 0x010000
250 #define PCS_HALT_COLD_BOOT 0x020000
251 #define PCS_HALT_WARM_BOOT 0x030000
252 #define PCS_HALT_STAY_HALTED 0x040000
253 #define PCS_mbz 0xffffffffff000000 /* 24:63 -- must be zero */
254 u_int64_t pcs_flags; /* 128: */
256 u_int64_t pcs_pal_memsize; /* 136: PAL memory size */
257 u_int64_t pcs_pal_scrsize; /* 144: PAL scratch size */
258 vm_offset_t pcs_pal_memaddr; /* 152: PAL memory addr */
259 vm_offset_t pcs_pal_scraddr; /* 160: PAL scratch addr */
262 minorrev : 8, /* alphabetic char 'a' - 'z' */
263 majorrev : 8, /* alphabetic char 'a' - 'z' */
264 #define PAL_TYPE_STANDARD 0
265 #define PAL_TYPE_VMS 1
266 #define PAL_TYPE_OSF1 2
267 pal_type : 8, /* PALcode type:
271 * 3-127 DIGITAL reserv.
272 * 128-255 non-DIGITAL reserv.
275 compatibility : 16, /* Compatibility revision */
276 proc_cnt : 16; /* Processor count */
277 } pcs_pal_rev; /* 168: */
278 #define pcs_minorrev pcs_pal_rev.minorrev
279 #define pcs_majorrev pcs_pal_rev.majorrev
280 #define pcs_pal_type pcs_pal_rev.pal_type
281 #define pcs_compatibility pcs_pal_rev.compatibility
282 #define pcs_proc_cnt pcs_pal_rev.proc_cnt
284 u_int64_t pcs_proc_type; /* 176: processor type */
286 #define PCS_PROC_MAJOR 0x00000000ffffffff
287 #define PCS_PROC_MAJORSHIFT 0
289 #define PCS_PROC_EV3 1 /* EV3 */
290 #define PCS_PROC_EV4 2 /* EV4: 21064 */
291 #define PCS_PROC_SIMULATION 3 /* Simulation */
292 #define PCS_PROC_LCA4 4 /* LCA4: 2106[68] */
293 #define PCS_PROC_EV5 5 /* EV5: 21164 */
294 #define PCS_PROC_EV45 6 /* EV45: 21064A */
295 #define PCS_PROC_EV56 7 /* EV56: 21164A */
296 #define PCS_PROC_EV6 8 /* EV6: 21264 */
297 #define PCS_PROC_PCA56 9 /* PCA256: 21164PC */
298 #define PCS_PROC_PCA57 10 /* PCA257: 21164PC */
299 #define PCS_PROC_EV67 11 /* EV67: 21264A */
300 #define PCS_PROC_EV68CB 12 /* EV68CB: 21264C */
301 #define PCS_PROC_EV68AL 13 /* EV6AL: 21264B */
302 #define PCS_PROC_EV68CX 14 /* EV6CX: 21264D */
304 #define PCS_PROC_MINOR 0xffffffff00000000
305 #define PCS_PROC_MINORSHIFT 32
307 /* Minor number interpretation is processor specific. See cpu.c. */
309 u_int64_t pcs_proc_var; /* 184: processor variation. */
311 #define PCS_VAR_VAXFP 0x0000000000000001 /* VAX FP support */
312 #define PCS_VAR_IEEEFP 0x0000000000000002 /* IEEE FP support */
313 #define PCS_VAR_PE 0x0000000000000004 /* Primary Eligible */
314 #define PCS_VAR_RESERVED 0xfffffffffffffff8 /* Reserved */
316 char pcs_proc_revision[8]; /* 192: only first 4 valid */
317 char pcs_proc_sn[16]; /* 200: only first 10 valid */
318 vm_offset_t pcs_machcheck; /* 216: mach chk phys addr. */
319 u_int64_t pcs_machcheck_len; /* 224: length in bytes */
320 vm_offset_t pcs_halt_pcbb; /* 232: pa of halt PCB */
321 vm_offset_t pcs_halt_pc; /* 240: halt PC */
322 u_int64_t pcs_halt_ps; /* 248: halt PS */
323 u_int64_t pcs_halt_r25; /* 256: halt argument list */
324 u_int64_t pcs_halt_r26; /* 264: halt ra list */
325 u_int64_t pcs_halt_r27; /* 272: halt procedure value */
327 #define PCS_HALT_RESERVED 0
328 #define PCS_HALT_POWERUP 1
329 #define PCS_HALT_CONSOLE_HALT 2
330 #define PCS_HALT_CONSOLE_CRASH 3
331 #define PCS_HALT_KERNEL_MODE 4
332 #define PCS_HALT_KERNEL_STACK_INVALID 5
333 #define PCS_HALT_DOUBLE_ERROR_ABORT 6
334 #define PCS_HALT_SCBB 7
335 #define PCS_HALT_PTBR 8 /* 9-FF: reserved */
336 u_int64_t pcs_halt_reason; /* 280: */
338 u_int64_t pcs_reserved_soft; /* 288: preserved software */
344 } pcs_buffer; /* 296: console buffers */
346 #define PALvar_reserved 0
347 #define PALvar_OpenVMS 1
348 #define PALvar_OSF1 2
349 u_int64_t pcs_palrevisions[16]; /* 464: PALcode revisions */
351 u_int64_t pcs_reserved_arch[6]; /* 592: reserved arch */
355 * CTB: Console Terminal Block
358 u_int64_t ctb_type; /* 0: always 4 */
359 u_int64_t ctb_unit; /* 8: */
360 u_int64_t ctb_reserved; /* 16: */
361 u_int64_t ctb_len; /* 24: bytes of info */
362 u_int64_t ctb_ipl; /* 32: console ipl level */
363 vm_offset_t ctb_tintr_vec; /* 40: transmit vec (0x800) */
364 vm_offset_t ctb_rintr_vec; /* 48: receive vec (0x800) */
366 #define CTB_GRAPHICS 3 /* graphics device */
367 #define CTB_NETWORK 0xC0 /* network device */
368 #define CTB_PRINTERPORT 2 /* printer port on the SCC */
369 u_int64_t ctb_term_type; /* 56: terminal type */
371 u_int64_t ctb_keybd_type; /* 64: keyboard nationality */
372 vm_offset_t ctb_keybd_trans; /* 72: trans. table addr */
373 vm_offset_t ctb_keybd_map; /* 80: map table addr */
374 u_int64_t ctb_keybd_state; /* 88: keyboard flags */
375 u_int64_t ctb_keybd_last; /* 96: last key entered */
376 vm_offset_t ctb_font_us; /* 104: US font table addr */
377 vm_offset_t ctb_font_mcs; /* 112: MCS font table addr */
378 u_int64_t ctb_font_width; /* 120: font width, height */
379 u_int64_t ctb_font_height; /* 128: in pixels */
380 u_int64_t ctb_mon_width; /* 136: monitor width, height */
381 u_int64_t ctb_mon_height; /* 144: in pixels */
382 u_int64_t ctb_dpi; /* 152: monitor dots per inch */
383 u_int64_t ctb_planes; /* 160: # of planes */
384 u_int64_t ctb_cur_width; /* 168: cursor width, height */
385 u_int64_t ctb_cur_height; /* 176: in pixels */
386 u_int64_t ctb_head_cnt; /* 184: # of heads */
387 u_int64_t ctb_opwindow; /* 192: opwindow on screen */
388 vm_offset_t ctb_head_offset; /* 200: offset to head info */
389 vm_offset_t ctb_putchar; /* 208: output char to TURBO */
390 u_int64_t ctb_io_state; /* 216: I/O flags */
391 u_int64_t ctb_listen_state; /* 224: listener flags */
392 vm_offset_t ctb_xaddr; /* 232: extended info addr */
393 u_int64_t ctb_turboslot; /* 248: TURBOchannel slot # */
394 u_int64_t ctb_server_off; /* 256: offset to server info */
395 u_int64_t ctb_line_off; /* 264: line parameter offset */
396 u_int8_t ctb_csd; /* 272: console specific data */
400 * CRD: Console Routine Descriptor
408 * CRB: Console Routine Block
411 struct crd *crb_v_dispatch; /* 0: virtual dispatch addr */
412 vm_offset_t crb_p_dispatch; /* 8: phys dispatch addr */
413 struct crd *crb_v_fixup; /* 10: virtual fixup addr */
414 vm_offset_t crb_p_fixup; /* 18: phys fixup addr */
415 u_int64_t crb_map_cnt; /* 20: phys/virt map entries */
416 u_int64_t crb_page_cnt; /* 28: pages to be mapped */
420 * MDDT: Memory Data Descriptor Table
423 int64_t mddt_cksum; /* 0: 7-N checksum */
424 vm_offset_t mddt_physaddr; /* 8: bank config addr
425 * IMPLEMENTATION SPECIFIC
427 u_int64_t mddt_cluster_cnt; /* 10: memory cluster count */
428 struct mddt_cluster {
429 vm_offset_t mddt_pfn; /* 0: starting PFN */
430 u_int64_t mddt_pg_cnt; /* 8: 8KB page count */
431 u_int64_t mddt_pg_test; /* 10: tested page count */
432 vm_offset_t mddt_v_bitaddr; /* 18: bitmap virt addr */
433 vm_offset_t mddt_p_bitaddr; /* 20: bitmap phys addr */
434 int64_t mddt_bit_cksum; /* 28: bitmap checksum */
436 #define MDDT_NONVOLATILE 0x10 /* cluster is non-volatile */
437 #define MDDT_PALCODE 0x01 /* console and PAL only */
438 #define MDDT_SYSTEM 0x00 /* system software only */
439 #define MDDT_mbz 0xfffffffffffffffc /* 2:63 -- must be zero */
440 int64_t mddt_usage; /* 30: bitmap permissions */
441 } mddt_clusters[1]; /* variable length array */
445 * DSR: Dynamic System Recognition. We're interested in the sysname
446 * offset. The data pointed to by sysname is:
448 * [8 bytes: length of system name][N bytes: system name string]
450 * The system name string is NUL-terminated.
453 int64_t dsr_smm; /* 0: SMM number */
454 u_int64_t dsr_lurt_off; /* 8: LURT table offset */
455 u_int64_t dsr_sysname_off; /* 16: offset to sysname */
459 * The DSR appeared in version 5 of the HWRPB.
461 #define HWRPB_DSRDB_MINVERS 5
463 #endif /* ASSEMBLER */