6/sys/alpha/pci/apecs_pci.c

   1 /*-
   2  * Copyright (c) 1998 Doug Rabson
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPEAPECSL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include <sys/param.h>
  31 #include <sys/systm.h>
  32 #include <sys/kernel.h>
  33 #include <sys/module.h>
  34 #include <sys/bus.h>
  35 #include <machine/bus.h>
  36 #include <sys/rman.h>
  37 #include <dev/pci/pcireg.h>
  38 #include <dev/pci/pcivar.h>
  39 #include <machine/cpuconf.h>
  40 #include <machine/swiz.h>
  41 #include <machine/md_var.h>
  42 #include <machine/rpb.h>
  43 #include <machine/resource.h>
  44
  45 #include <alpha/pci/apecsreg.h>
  46 #include <alpha/pci/apecsvar.h>
  47 #include <alpha/pci/pcibus.h>
  48 #include <alpha/isa/isavar.h>
  49
  50 #include "alphapci_if.h"
  51 #include "pcib_if.h"
  52
  53 #define KV(pa)                  ALPHA_PHYS_TO_K0SEG(pa)
  54
  55 static devclass_t       pcib_devclass;
  56
  57 static int
  58 apecs_pcib_probe(device_t dev)
  59 {
  60         device_set_desc(dev, "2107x PCI host bus adapter");
  61
  62         pci_init_resources();
  63         device_add_child(dev, "pci", 0);
  64
  65         return 0;
  66 }
  67
  68 static int
  69 apecs_pcib_read_ivar(device_t dev, device_t child, int which, u_long *result)
  70 {
  71         if (which == PCIB_IVAR_BUS) {
  72                 *result = 0;
  73                 return 0;
  74         }
  75         return ENOENT;
  76 }
  77
  78 static struct resource *
  79 apecs_pcib_alloc_resource(device_t bus, device_t child, int type, int *rid,
  80                           u_long start, u_long end, u_long count, u_int flags)
  81 {
  82         struct resource *rv = NULL;
  83
  84         if ((hwrpb->rpb_type == ST_DEC_2100_A50) &&
  85             (type == SYS_RES_IRQ))
  86                 rv = isa_alloc_intr(bus, child, start);
  87         else
  88                 rv = alpha_pci_alloc_resource(bus, child, type, rid,
  89                     start, end, count, flags);
  90         if (rv != NULL)
  91                 rman_set_rid(rv, *rid);
  92         return (rv);
  93 }
  94
  95 static int
  96 apecs_pcib_release_resource(device_t bus, device_t child, int type, int rid,
  97                             struct resource *r)
  98 {
  99         if ((hwrpb->rpb_type == ST_DEC_2100_A50) &&
 100             (type == SYS_RES_IRQ))
 101                 return isa_release_intr(bus, child, r);
 102         else
 103                 return pci_release_resource(bus, child, type, rid, r);
 104 }
 105
 106 static void *
 107 apecs_pcib_cvt_dense(device_t dev, vm_offset_t addr)
 108 {
 109         addr &= 0xffffffffUL;
 110         return (void *) KV(addr | APECS_PCI_DENSE);
 111 }
 112
 113 static int
 114 apecs_pcib_maxslots(device_t dev)
 115 {
 116         return 31;
 117 }
 118
 119 #define APECS_SWIZ_CFGOFF(b, s, f, r) \
 120         (((b) << 16) | ((s) << 11) | ((f) << 8) | (r))
 121
 122 #define APECS_TYPE1_SETUP(b,s,old_haxr2) if((b)) {      \
 123         do {                                            \
 124                 (s) = splhigh();                        \
 125                 (old_haxr2) = REGVAL(EPIC_HAXR2);       \
 126                 alpha_mb();                             \
 127                 REGVAL(EPIC_HAXR2) = (old_haxr2) | 0x1; \
 128                 alpha_mb();                             \
 129         } while(0);                                     \
 130 }
 131
 132 #define APECS_TYPE1_TEARDOWN(b,s,old_haxr2) if((b)) {   \
 133         do {                                            \
 134                 alpha_mb();                             \
 135                 REGVAL(EPIC_HAXR2) = (old_haxr2);       \
 136                 alpha_mb();                             \
 137                 splx((s));                              \
 138         } while(0);                                     \
 139 }
 140
 141 #define SWIZ_CFGREAD(b, s, f, r, width, type) do {                      \
 142         type val = ~0;                                                  \
 143         int ipl = 0;                                                    \
 144         u_int32_t old_haxr2 = 0;                                        \
 145         vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r);                \
 146         vm_offset_t kv =                                                \
 147                 SPARSE_##width##_ADDRESS(KV(APECS_PCI_CONF), off);      \
 148         alpha_mb();                                                     \
 149         APECS_TYPE1_SETUP(b,ipl,old_haxr2);                             \
 150         if (!badaddr((caddr_t)kv, sizeof(type))) {                      \
 151                 val = SPARSE_##width##_EXTRACT(off, SPARSE_READ(kv));   \
 152         }                                                               \
 153         APECS_TYPE1_TEARDOWN(b,ipl,old_haxr2);                          \
 154         return val;                                                     \
 155 } while (0)
 156
 157 #define SWIZ_CFGWRITE(b, s, f, r, data, width, type) do {               \
 158         int ipl = 0;                                                    \
 159         u_int32_t old_haxr2 = 0;                                        \
 160         vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r);                \
 161         vm_offset_t kv =                                                \
 162                 SPARSE_##width##_ADDRESS(KV(APECS_PCI_CONF), off);      \
 163         alpha_mb();                                                     \
 164         APECS_TYPE1_SETUP(b,ipl,old_haxr2);                             \
 165         if (!badaddr((caddr_t)kv, sizeof(type))) {                      \
 166                 SPARSE_WRITE(kv, SPARSE_##width##_INSERT(off, data));   \
 167                 alpha_wmb();                                            \
 168         }                                                               \
 169         APECS_TYPE1_TEARDOWN(b,ipl,old_haxr2);                          \
 170         return;                                                         \
 171 } while (0)
 172
 173 u_int32_t
 174 apecs_pcib_read_config(device_t dev, u_int b, u_int s, u_int f,
 175                        u_int reg, int width)
 176 {
 177         pcicfgregs cfg;
 178
 179         if ((reg == PCIR_INTLINE) && (width == 1) &&
 180              (platform.pci_intr_map != NULL)) {
 181                 cfg.bus = b;
 182                 cfg.slot = s;
 183                 cfg.func = f;
 184                 cfg.intline = 255;
 185                 cfg.intpin =
 186                     apecs_pcib_read_config(dev, b, s, f, PCIR_INTPIN, 1);
 187                 platform.pci_intr_map((void *)&cfg);
 188                 if (cfg.intline != 255)
 189                         return cfg.intline;
 190         }
 191
 192         switch (width) {
 193         case 1:
 194                 SWIZ_CFGREAD(b, s, f, reg, BYTE, u_int8_t);
 195                 break;
 196         case 2:
 197                 SWIZ_CFGREAD(b, s, f, reg, WORD, u_int16_t);
 198                 break;
 199         case 4:
 200                 SWIZ_CFGREAD(b, s, f, reg, LONG, u_int32_t);
 201         }
 202         return ~0;
 203 }
 204
 205 static void
 206 apecs_pcib_write_config(device_t dev, u_int b, u_int s, u_int f,
 207                         u_int reg, u_int32_t val, int width)
 208 {
 209         switch (width) {
 210         case 1:
 211                 SWIZ_CFGWRITE(b, s, f, reg, val, BYTE, u_int8_t);
 212                 break;
 213         case 2:
 214                 SWIZ_CFGWRITE(b, s, f, reg, val, WORD, u_int16_t);
 215                 break;
 216         case 4:
 217                 SWIZ_CFGWRITE(b, s, f, reg, val, LONG, u_int32_t);
 218         }
 219 }
 220
 221 static device_method_t apecs_pcib_methods[] = {
 222         /* Device interface */
 223         DEVMETHOD(device_probe,         apecs_pcib_probe),
 224         DEVMETHOD(device_attach,        bus_generic_attach),
 225
 226         /* Bus interface */
 227         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 228         DEVMETHOD(bus_read_ivar,        apecs_pcib_read_ivar),
 229         DEVMETHOD(bus_alloc_resource,   apecs_pcib_alloc_resource),
 230         DEVMETHOD(bus_release_resource, apecs_pcib_release_resource),
 231         DEVMETHOD(bus_activate_resource, pci_activate_resource),
 232         DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource),
 233         DEVMETHOD(bus_setup_intr,       bus_generic_setup_intr),
 234         DEVMETHOD(bus_teardown_intr,    bus_generic_teardown_intr),
 235
 236         /* alphapci interface */
 237         DEVMETHOD(alphapci_cvt_dense,   apecs_pcib_cvt_dense),
 238
 239         /* pcib interface */
 240         DEVMETHOD(pcib_maxslots,        apecs_pcib_maxslots),
 241         DEVMETHOD(pcib_read_config,     apecs_pcib_read_config),
 242         DEVMETHOD(pcib_write_config,    apecs_pcib_write_config),
 243         DEVMETHOD(pcib_route_interrupt, alpha_pci_route_interrupt),
 244
 245         { 0, 0 }
 246 };
 247
 248 static driver_t apecs_pcib_driver = {
 249         "pcib",
 250         apecs_pcib_methods,
 251         1,
 252 };
 253
 254 DRIVER_MODULE(pcib, apecs, apecs_pcib_driver, pcib_devclass, 0, 0);