2 * Copyright (c) 1991 Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
6 * the Systems Programming Group of the University of Utah Computer
7 * Science Department and William Jolitz of UUNET Technologies Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by the University of
20 * California, Berkeley and its contributors.
21 * 4. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * Derived from hp300 version by Mike Hibler, this version by William
38 * Jolitz uses a recursive map [a pde points to the page directory] to
39 * map the page tables using the pagetables themselves. This is done to
40 * reduce the impact on kernel virtual memory for lots of sparse address
41 * space, and to reduce the cost of memory to each process.
43 * from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90
44 * from: @(#)pmap.h 7.4 (Berkeley) 5/12/91
45 * from: FreeBSD: src/sys/i386/include/pmap.h,v 1.70 2000/11/30
50 #ifndef _MACHINE_PMAP_H_
51 #define _MACHINE_PMAP_H_
53 #include <machine/pte.h>
60 #define PTE_PAGETABLE 2
64 #include <sys/queue.h>
66 #define PDESIZE sizeof(pd_entry_t) /* for assembly files */
67 #define PTESIZE sizeof(pt_entry_t) /* for assembly files */
71 #define vtophys(va) pmap_extract(pmap_kernel(), (vm_offset_t)(va))
72 #define pmap_kextract(va) pmap_extract(pmap_kernel(), (vm_offset_t)(va))
76 #define pmap_page_is_mapped(m) (!TAILQ_EMPTY(&(m)->md.pv_list))
82 * This structure is used to hold a virtual<->physical address
83 * association and is used mostly by bootstrap code
86 SLIST_ENTRY(pv_addr) pv_list;
98 u_short s_mappings[2]; /* Assume kernel count <= 65535 */
101 #define kro_mappings k_u.s_mappings[0]
102 #define krw_mappings k_u.s_mappings[1]
103 #define k_mappings k_u.i_mappings
105 TAILQ_HEAD(,pv_entry) pv_list;
108 #define VM_MDPAGE_INIT(pg) \
110 TAILQ_INIT(&pg->pv_list); \
111 mtx_init(&(pg)->md_page.pvh_mtx, "MDPAGE Mutex", NULL, MTX_DEV);\
112 (pg)->mdpage.pvh_attrs = 0; \
113 (pg)->mdpage.uro_mappings = 0; \
114 (pg)->mdpage.urw_mappings = 0; \
115 (pg)->mdpage.k_mappings = 0; \
116 } while (/*CONSTCOND*/0)
123 * The number of L2 descriptor tables which can be tracked by an l2_dtable.
124 * A bucket size of 16 provides for 16MB of contiguous virtual address
125 * space per l2_dtable. Most processes will, therefore, require only two or
126 * three of these to map their whole working set.
128 #define L2_BUCKET_LOG2 4
129 #define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2)
131 * Given the above "L2-descriptors-per-l2_dtable" constant, the number
132 * of l2_dtable structures required to track all possible page descriptors
133 * mappable by an L1 translation table is given by the following constants:
135 #define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2)
136 #define L2_SIZE (1 << L2_LOG2)
140 struct l1_ttable *pm_l1;
141 struct l2_dtable *pm_l2[L2_SIZE];
142 pd_entry_t *pm_pdir; /* KVA of page directory */
143 int pm_count; /* reference count */
144 int pm_active; /* active on cpus */
145 struct pmap_statistics pm_stats; /* pmap statictics */
146 TAILQ_HEAD(,pv_entry) pm_pvlist; /* list of mappings in pmap */
147 LIST_ENTRY(pmap) pm_list; /* List of all pmaps */
150 typedef struct pmap *pmap_t;
153 extern pmap_t kernel_pmap;
154 #define pmap_kernel() kernel_pmap
160 * For each vm_page_t, there is a list of all currently valid virtual
161 * mappings of that page. An entry is a pv_entry_t, the list is pv_table.
163 typedef struct pv_entry {
164 pmap_t pv_pmap; /* pmap where mapping lies */
165 vm_offset_t pv_va; /* virtual address for mapping */
166 TAILQ_ENTRY(pv_entry) pv_list;
167 TAILQ_ENTRY(pv_entry) pv_plist;
168 int pv_flags; /* flags (wired, etc...) */
171 #define PV_ENTRY_NULL ((pv_entry_t) 0)
175 boolean_t pmap_get_pde_pte(pmap_t, vm_offset_t, pd_entry_t **, pt_entry_t **);
178 * virtual address to page table entry and
179 * to physical address. Likewise for alternate address space.
180 * Note: these work recursively, thus vtopte of a pte will give
181 * the corresponding pde that in turn maps it.
185 * The current top of kernel VM.
187 extern vm_offset_t pmap_curmaxkvaddr;
191 void pmap_set_pcb_pagedir(pmap_t, struct pcb *);
192 /* Virtual address to page table entry */
193 static __inline pt_entry_t *
194 vtopte(vm_offset_t va)
199 if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == FALSE)
204 extern vm_offset_t avail_end;
205 extern vm_offset_t clean_eva;
206 extern vm_offset_t clean_sva;
207 extern vm_offset_t phys_avail[];
208 extern vm_offset_t virtual_avail;
209 extern vm_offset_t virtual_end;
211 void pmap_bootstrap(vm_offset_t, vm_offset_t, struct pv_addr *);
212 void pmap_kenter(vm_offset_t va, vm_paddr_t pa);
213 void pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa);
214 void pmap_kenter_user(vm_offset_t va, vm_paddr_t pa);
215 void pmap_kremove(vm_offset_t);
216 void *pmap_mapdev(vm_offset_t, vm_size_t);
217 void pmap_unmapdev(vm_offset_t, vm_size_t);
218 vm_page_t pmap_use_pt(pmap_t, vm_offset_t);
219 void pmap_debug(int);
220 void pmap_map_section(vm_offset_t, vm_offset_t, vm_offset_t, int, int);
221 void pmap_link_l2pt(vm_offset_t, vm_offset_t, struct pv_addr *);
222 vm_size_t pmap_map_chunk(vm_offset_t, vm_offset_t, vm_offset_t, vm_size_t, int, int);
224 pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot,
226 int pmap_fault_fixup(pmap_t, vm_offset_t, vm_prot_t, int);
229 * Definitions for MMU domains
231 #define PMAP_DOMAINS 15 /* 15 'user' domains (0-14) */
232 #define PMAP_DOMAIN_KERNEL 15 /* The kernel uses domain #15 */
235 * The new pmap ensures that page-tables are always mapping Write-Thru.
236 * Thus, on some platforms we can run fast and loose and avoid syncing PTEs
239 * Unfortunately, not all CPUs have a write-through cache mode. So we
240 * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs,
241 * and if there is the chance for PTE syncs to be needed, we define
242 * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run)
245 extern int pmap_needs_pte_sync;
248 * These macros define the various bit masks in the PTE.
250 * We use these macros since we use different bits on different processor
253 #define L1_S_PROT_U (L1_S_AP(AP_U))
254 #define L1_S_PROT_W (L1_S_AP(AP_W))
255 #define L1_S_PROT_MASK (L1_S_PROT_U|L1_S_PROT_W)
257 #define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C)
258 #define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X))
260 #define L2_L_PROT_U (L2_AP(AP_U))
261 #define L2_L_PROT_W (L2_AP(AP_W))
262 #define L2_L_PROT_MASK (L2_L_PROT_U|L2_L_PROT_W)
264 #define L2_L_CACHE_MASK_generic (L2_B|L2_C)
265 #define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_L_TEX(TEX_XSCALE_X))
267 #define L2_S_PROT_U_generic (L2_AP(AP_U))
268 #define L2_S_PROT_W_generic (L2_AP(AP_W))
269 #define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W)
271 #define L2_S_PROT_U_xscale (L2_AP0(AP_U))
272 #define L2_S_PROT_W_xscale (L2_AP0(AP_W))
273 #define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W)
275 #define L2_S_CACHE_MASK_generic (L2_B|L2_C)
276 #define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_T_TEX(TEX_XSCALE_X))
278 #define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP)
279 #define L1_S_PROTO_xscale (L1_TYPE_S)
281 #define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2)
282 #define L1_C_PROTO_xscale (L1_TYPE_C)
284 #define L2_L_PROTO (L2_TYPE_L)
286 #define L2_S_PROTO_generic (L2_TYPE_S)
287 #define L2_S_PROTO_xscale (L2_TYPE_XSCALE_XS)
290 * User-visible names for the ones that vary with MMU class.
294 /* More than one MMU class configured; use variables. */
295 #define L2_S_PROT_U pte_l2_s_prot_u
296 #define L2_S_PROT_W pte_l2_s_prot_w
297 #define L2_S_PROT_MASK pte_l2_s_prot_mask
299 #define L1_S_CACHE_MASK pte_l1_s_cache_mask
300 #define L2_L_CACHE_MASK pte_l2_l_cache_mask
301 #define L2_S_CACHE_MASK pte_l2_s_cache_mask
303 #define L1_S_PROTO pte_l1_s_proto
304 #define L1_C_PROTO pte_l1_c_proto
305 #define L2_S_PROTO pte_l2_s_proto
307 #elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
308 #define L2_S_PROT_U L2_S_PROT_U_generic
309 #define L2_S_PROT_W L2_S_PROT_W_generic
310 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic
312 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic
313 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic
314 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic
316 #define L1_S_PROTO L1_S_PROTO_generic
317 #define L1_C_PROTO L1_C_PROTO_generic
318 #define L2_S_PROTO L2_S_PROTO_generic
320 #elif ARM_MMU_XSCALE == 1
321 #define L2_S_PROT_U L2_S_PROT_U_xscale
322 #define L2_S_PROT_W L2_S_PROT_W_xscale
323 #define L2_S_PROT_MASK L2_S_PROT_MASK_xscale
325 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale
326 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale
327 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale
329 #define L1_S_PROTO L1_S_PROTO_xscale
330 #define L1_C_PROTO L1_C_PROTO_xscale
331 #define L2_S_PROTO L2_S_PROTO_xscale
333 #endif /* ARM_NMMUS > 1 */
335 #ifdef SKYEYE_WORKAROUNDS
336 #define PMAP_NEED_PTE_SYNC 1
337 #define PMAP_INCLUDE_PTE_SYNC
339 #if (ARM_MMU_SA1 == 1) && (ARM_NMMUS == 1)
340 #define PMAP_NEEDS_PTE_SYNC 1
341 #define PMAP_INCLUDE_PTE_SYNC
342 #elif (ARM_MMU_SA1 == 0)
343 #define PMAP_NEEDS_PTE_SYNC 0
348 * These macros return various bits based on kernel/user and protection.
349 * Note that the compiler will usually fold these at compile time.
351 #define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \
352 (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0))
354 #define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \
355 (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : 0))
357 #define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \
358 (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0))
361 * Macros to test if a mapping is mappable with an L1 Section mapping
362 * or an L2 Large Page mapping.
364 #define L1_S_MAPPABLE_P(va, pa, size) \
365 ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE)
367 #define L2_L_MAPPABLE_P(va, pa, size) \
368 ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE)
371 * Provide a fallback in case we were not able to determine it at
374 #ifndef PMAP_NEEDS_PTE_SYNC
375 #define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync
376 #define PMAP_INCLUDE_PTE_SYNC
379 #define PTE_SYNC(pte) \
381 if (PMAP_NEEDS_PTE_SYNC) \
382 cpu_dcache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\
383 } while (/*CONSTCOND*/0)
385 #define PTE_SYNC_RANGE(pte, cnt) \
387 if (PMAP_NEEDS_PTE_SYNC) { \
388 cpu_dcache_wb_range((vm_offset_t)(pte), \
389 (cnt) << 2); /* * sizeof(pt_entry_t) */ \
391 } while (/*CONSTCOND*/0)
393 extern pt_entry_t pte_l1_s_cache_mode;
394 extern pt_entry_t pte_l1_s_cache_mask;
396 extern pt_entry_t pte_l2_l_cache_mode;
397 extern pt_entry_t pte_l2_l_cache_mask;
399 extern pt_entry_t pte_l2_s_cache_mode;
400 extern pt_entry_t pte_l2_s_cache_mask;
402 extern pt_entry_t pte_l1_s_cache_mode_pt;
403 extern pt_entry_t pte_l2_l_cache_mode_pt;
404 extern pt_entry_t pte_l2_s_cache_mode_pt;
406 extern pt_entry_t pte_l2_s_prot_u;
407 extern pt_entry_t pte_l2_s_prot_w;
408 extern pt_entry_t pte_l2_s_prot_mask;
410 extern pt_entry_t pte_l1_s_proto;
411 extern pt_entry_t pte_l1_c_proto;
412 extern pt_entry_t pte_l2_s_proto;
414 extern void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t);
415 extern void (*pmap_zero_page_func)(vm_paddr_t, int, int);
417 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
418 void pmap_copy_page_generic(vm_paddr_t, vm_paddr_t);
419 void pmap_zero_page_generic(vm_paddr_t, int, int);
421 void pmap_pte_init_generic(void);
422 #if defined(CPU_ARM8)
423 void pmap_pte_init_arm8(void);
425 #if defined(CPU_ARM9)
426 void pmap_pte_init_arm9(void);
427 #endif /* CPU_ARM9 */
428 #if defined(CPU_ARM10)
429 void pmap_pte_init_arm10(void);
430 #endif /* CPU_ARM10 */
431 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
433 #if /* ARM_MMU_SA1 == */1
434 void pmap_pte_init_sa1(void);
435 #endif /* ARM_MMU_SA1 == 1 */
437 #if ARM_MMU_XSCALE == 1
438 void pmap_copy_page_xscale(vm_paddr_t, vm_paddr_t);
439 void pmap_zero_page_xscale(vm_paddr_t, int, int);
441 void pmap_pte_init_xscale(void);
443 void xscale_setup_minidata(vm_offset_t, vm_offset_t, vm_offset_t);
445 void pmap_use_minicache(vm_offset_t, vm_size_t);
446 #endif /* ARM_MMU_XSCALE == 1 */
449 #define l1pte_valid(pde) ((pde) != 0)
450 #define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S)
451 #define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C)
452 #define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F)
454 #define l2pte_index(v) (((v) & L2_ADDR_BITS) >> L2_S_SHIFT)
455 #define l2pte_valid(pte) ((pte) != 0)
456 #define l2pte_pa(pte) ((pte) & L2_S_FRAME)
457 #define l2pte_minidata(pte) (((pte) & \
458 (L2_B | L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))\
459 == (L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))
461 /* L1 and L2 page table macros */
462 #define pmap_pde_v(pde) l1pte_valid(*(pde))
463 #define pmap_pde_section(pde) l1pte_section_p(*(pde))
464 #define pmap_pde_page(pde) l1pte_page_p(*(pde))
465 #define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde))
467 #define pmap_pte_v(pte) l2pte_valid(*(pte))
468 #define pmap_pte_pa(pte) l2pte_pa(*(pte))
471 * Flags that indicate attributes of pages or mappings of pages.
473 * The PVF_MOD and PVF_REF flags are stored in the mdpage for each
474 * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual
475 * pv_entry's for each page. They live in the same "namespace" so
476 * that we can clear multiple attributes at a time.
478 * Note the "non-cacheable" flag generally means the page has
479 * multiple mappings in a given address space.
481 #define PVF_MOD 0x01 /* page is modified */
482 #define PVF_REF 0x02 /* page is referenced */
483 #define PVF_WIRED 0x04 /* mapping is wired */
484 #define PVF_WRITE 0x08 /* mapping is writable */
485 #define PVF_EXEC 0x10 /* mapping is executable */
486 #define PVF_UNC 0x20 /* mapping is 'user' non-cacheable */
487 #define PVF_KNC 0x40 /* mapping is 'kernel' non-cacheable */
488 #define PVF_NC (PVF_UNC|PVF_KNC)
490 void vector_page_setprot(int);
492 void pmap_update(pmap_t);
495 * This structure is used by machine-dependent code to describe
496 * static mappings of devices, created at bootstrap time.
499 vm_offset_t pd_va; /* virtual address */
500 vm_paddr_t pd_pa; /* physical address */
501 vm_size_t pd_size; /* size of region */
502 vm_prot_t pd_prot; /* protection code */
503 int pd_cache; /* cache attributes */
506 const struct pmap_devmap *pmap_devmap_find_pa(vm_paddr_t, vm_size_t);
507 const struct pmap_devmap *pmap_devmap_find_va(vm_offset_t, vm_size_t);
509 void pmap_devmap_bootstrap(vm_offset_t, const struct pmap_devmap *);
510 void pmap_devmap_register(const struct pmap_devmap *);
512 #define SECTION_CACHE 0x1
513 #define SECTION_PT 0x2
514 void pmap_kenter_section(vm_offset_t, vm_paddr_t, int flags);
518 #ifdef ARM_USE_SMALL_ALLOC
519 void arm_add_smallalloc_pages(void *, void *, int, int);
520 vm_offset_t arm_ptovirt(vm_paddr_t);
521 void arm_init_smallalloc(void);
522 struct arm_small_page {
524 TAILQ_ENTRY(arm_small_page) pg_list;
527 #define ARM_NOCACHE_KVA_SIZE 0x600000
528 extern vm_offset_t arm_nocache_startaddr;
529 void *arm_remap_nocache(void *, vm_size_t);
530 void arm_unmap_nocache(void *, vm_size_t);
532 extern vm_paddr_t dump_avail[];
538 #endif /* !_MACHINE_PMAP_H_ */