1 /*******************************************************************************
3 Copyright (c) 2001-2007, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 *******************************************************************************/
40 #include "e1000_api.h"
41 #include "e1000_82575.h"
43 void e1000_init_function_pointers_82575(struct e1000_hw *hw);
45 STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
46 STATIC s32 e1000_init_nvm_params_82575(struct e1000_hw *hw);
47 STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
48 STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw);
49 STATIC void e1000_release_phy_82575(struct e1000_hw *hw);
50 STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
51 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw);
52 STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw);
53 STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
54 STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
56 STATIC s32 e1000_init_hw_82575(struct e1000_hw *hw);
57 STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
58 STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
60 STATIC void e1000_rar_set_82575(struct e1000_hw *hw, u8 *addr, u32 index);
61 STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw);
62 STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
64 STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
65 STATIC s32 e1000_setup_fiber_serdes_link_82575(struct e1000_hw *hw);
66 STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
67 u32 offset, u16 data);
68 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
69 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
70 static s32 e1000_configure_pcs_link_82575(struct e1000_hw *hw);
71 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
72 u16 *speed, u16 *duplex);
73 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
74 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
75 static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
76 STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
77 STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
79 struct e1000_dev_spec_82575 {
84 * e1000_init_phy_params_82575 - Init PHY func ptrs.
85 * @hw: pointer to the HW structure
87 * This is a function pointer entry point called by the api module.
89 STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
91 struct e1000_phy_info *phy = &hw->phy;
92 struct e1000_functions *func = &hw->func;
93 s32 ret_val = E1000_SUCCESS;
95 DEBUGFUNC("e1000_init_phy_params_82575");
97 if (hw->phy.media_type != e1000_media_type_copper) {
98 phy->type = e1000_phy_none;
102 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
103 phy->reset_delay_us = 100;
105 func->acquire_phy = e1000_acquire_phy_82575;
106 func->check_reset_block = e1000_check_reset_block_generic;
107 func->commit_phy = e1000_phy_sw_reset_generic;
108 func->get_cfg_done = e1000_get_cfg_done_82575;
109 func->release_phy = e1000_release_phy_82575;
111 if (e1000_sgmii_active_82575(hw)) {
112 func->reset_phy = e1000_phy_hw_reset_sgmii_82575;
113 func->read_phy_reg = e1000_read_phy_reg_sgmii_82575;
114 func->write_phy_reg = e1000_write_phy_reg_sgmii_82575;
116 func->reset_phy = e1000_phy_hw_reset_generic;
117 func->read_phy_reg = e1000_read_phy_reg_igp;
118 func->write_phy_reg = e1000_write_phy_reg_igp;
121 /* Set phy->phy_addr and phy->id. */
122 ret_val = e1000_get_phy_id_82575(hw);
124 /* Verify phy id and set remaining function pointers */
126 case M88E1111_I_PHY_ID:
127 phy->type = e1000_phy_m88;
128 func->check_polarity = e1000_check_polarity_m88;
129 func->get_phy_info = e1000_get_phy_info_m88;
130 func->get_cable_length = e1000_get_cable_length_m88;
131 func->force_speed_duplex = e1000_phy_force_speed_duplex_m88;
133 case IGP03E1000_E_PHY_ID:
134 phy->type = e1000_phy_igp_3;
135 func->check_polarity = e1000_check_polarity_igp;
136 func->get_phy_info = e1000_get_phy_info_igp;
137 func->get_cable_length = e1000_get_cable_length_igp_2;
138 func->force_speed_duplex = e1000_phy_force_speed_duplex_igp;
139 func->set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
140 func->set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
143 ret_val = -E1000_ERR_PHY;
152 * e1000_init_nvm_params_82575 - Init NVM func ptrs.
153 * @hw: pointer to the HW structure
155 * This is a function pointer entry point called by the api module.
157 STATIC s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
159 struct e1000_nvm_info *nvm = &hw->nvm;
160 struct e1000_functions *func = &hw->func;
161 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
164 DEBUGFUNC("e1000_init_nvm_params_82575");
166 nvm->opcode_bits = 8;
168 switch (nvm->override) {
169 case e1000_nvm_override_spi_large:
171 nvm->address_bits = 16;
173 case e1000_nvm_override_spi_small:
175 nvm->address_bits = 8;
178 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
179 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
183 nvm->type = e1000_nvm_eeprom_spi;
185 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
186 E1000_EECD_SIZE_EX_SHIFT);
189 * Added to a constant, "size" becomes the left-shift value
190 * for setting word_size.
192 size += NVM_WORD_SIZE_BASE_SHIFT;
193 nvm->word_size = 1 << size;
195 /* Function Pointers */
196 func->acquire_nvm = e1000_acquire_nvm_82575;
197 func->read_nvm = e1000_read_nvm_eerd;
198 func->release_nvm = e1000_release_nvm_82575;
199 func->update_nvm = e1000_update_nvm_checksum_generic;
200 func->valid_led_default = e1000_valid_led_default_generic;
201 func->validate_nvm = e1000_validate_nvm_checksum_generic;
202 func->write_nvm = e1000_write_nvm_spi;
204 return E1000_SUCCESS;
208 * e1000_init_mac_params_82575 - Init MAC func ptrs.
209 * @hw: pointer to the HW structure
211 * This is a function pointer entry point called by the api module.
213 STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
215 struct e1000_mac_info *mac = &hw->mac;
216 struct e1000_functions *func = &hw->func;
217 struct e1000_dev_spec_82575 *dev_spec;
219 s32 ret_val = E1000_SUCCESS;
221 DEBUGFUNC("e1000_init_mac_params_82575");
223 hw->dev_spec_size = sizeof(struct e1000_dev_spec_82575);
225 /* Device-specific structure allocation */
226 ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size);
230 dev_spec = (struct e1000_dev_spec_82575 *)hw->dev_spec;
234 * The 82575 uses bits 22:23 for link mode. The mode can be changed
235 * based on the EEPROM. We cannot rely upon device ID. There
236 * is no distinguishable difference between fiber and internal
237 * SerDes mode on the 82575. There can be an external PHY attached
238 * on the SGMII interface. For this, we'll set sgmii_active to TRUE.
240 hw->phy.media_type = e1000_media_type_copper;
241 dev_spec->sgmii_active = FALSE;
243 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
244 if ((ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) ==
245 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES) {
246 hw->phy.media_type = e1000_media_type_internal_serdes;
247 } else if (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII) {
248 dev_spec->sgmii_active = TRUE;
249 ctrl = E1000_READ_REG(hw, E1000_CTRL);
250 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_I2C_ENA));
253 /* Set mta register count */
254 mac->mta_reg_count = 128;
255 /* Set rar entry count */
256 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
257 /* Set if part includes ASF firmware */
258 mac->asf_firmware_present = TRUE;
259 /* Set if manageability features are enabled. */
260 mac->arc_subsystem_valid =
261 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
264 /* Function pointers */
266 /* bus type/speed/width */
267 func->get_bus_info = e1000_get_bus_info_pcie_generic;
269 func->reset_hw = e1000_reset_hw_82575;
270 /* hw initialization */
271 func->init_hw = e1000_init_hw_82575;
273 func->setup_link = e1000_setup_link_generic;
274 /* physical interface link setup */
275 func->setup_physical_interface =
276 (hw->phy.media_type == e1000_media_type_copper)
277 ? e1000_setup_copper_link_82575
278 : e1000_setup_fiber_serdes_link_82575;
280 func->check_for_link = e1000_check_for_link_82575;
281 /* receive address register setting */
282 func->rar_set = e1000_rar_set_82575;
283 /* read mac address */
284 func->read_mac_addr = e1000_read_mac_addr_82575;
285 /* multicast address update */
286 func->update_mc_addr_list = e1000_update_mc_addr_list_generic;
288 func->write_vfta = e1000_write_vfta_generic;
290 func->clear_vfta = e1000_clear_vfta_generic;
292 func->mta_set = e1000_mta_set_generic;
294 func->blink_led = e1000_blink_led_generic;
296 func->setup_led = e1000_setup_led_generic;
298 func->cleanup_led = e1000_cleanup_led_generic;
299 /* turn on/off LED */
300 func->led_on = e1000_led_on_generic;
301 func->led_off = e1000_led_off_generic;
303 func->remove_device = e1000_remove_device_generic;
304 /* clear hardware counters */
305 func->clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
307 func->get_link_up_info = e1000_get_link_up_info_82575;
314 * e1000_init_function_pointers_82575 - Init func ptrs.
315 * @hw: pointer to the HW structure
317 * The only function explicitly called by the api module to initialize
318 * all function pointers and parameters.
320 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
322 DEBUGFUNC("e1000_init_function_pointers_82575");
324 hw->func.init_mac_params = e1000_init_mac_params_82575;
325 hw->func.init_nvm_params = e1000_init_nvm_params_82575;
326 hw->func.init_phy_params = e1000_init_phy_params_82575;
330 * e1000_acquire_phy_82575 - Acquire rights to access PHY
331 * @hw: pointer to the HW structure
333 * Acquire access rights to the correct PHY. This is a
334 * function pointer entry point called by the api module.
336 STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
340 DEBUGFUNC("e1000_acquire_phy_82575");
342 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
344 return e1000_acquire_swfw_sync_82575(hw, mask);
348 * e1000_release_phy_82575 - Release rights to access PHY
349 * @hw: pointer to the HW structure
351 * A wrapper to release access rights to the correct PHY. This is a
352 * function pointer entry point called by the api module.
354 STATIC void e1000_release_phy_82575(struct e1000_hw *hw)
358 DEBUGFUNC("e1000_release_phy_82575");
360 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
361 e1000_release_swfw_sync_82575(hw, mask);
365 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
366 * @hw: pointer to the HW structure
367 * @offset: register offset to be read
368 * @data: pointer to the read data
370 * Reads the PHY register at offset using the serial gigabit media independent
371 * interface and stores the retrieved information in data.
373 STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
376 struct e1000_phy_info *phy = &hw->phy;
379 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
381 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
382 DEBUGOUT1("PHY Address %u is out of range\n", offset);
383 return -E1000_ERR_PARAM;
387 * Set up Op-code, Phy Address, and register address in the I2CCMD
388 * register. The MAC will take care of interfacing with the
389 * PHY to retrieve the desired data.
391 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
392 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
393 (E1000_I2CCMD_OPCODE_READ));
395 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
397 /* Poll the ready bit to see if the I2C read completed */
398 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
400 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
401 if (i2ccmd & E1000_I2CCMD_READY)
404 if (!(i2ccmd & E1000_I2CCMD_READY)) {
405 DEBUGOUT("I2CCMD Read did not complete\n");
406 return -E1000_ERR_PHY;
408 if (i2ccmd & E1000_I2CCMD_ERROR) {
409 DEBUGOUT("I2CCMD Error bit set\n");
410 return -E1000_ERR_PHY;
413 /* Need to byte-swap the 16-bit value. */
414 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
416 return E1000_SUCCESS;
420 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
421 * @hw: pointer to the HW structure
422 * @offset: register offset to write to
423 * @data: data to write at register offset
425 * Writes the data to PHY register at the offset using the serial gigabit
426 * media independent interface.
428 STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
431 struct e1000_phy_info *phy = &hw->phy;
433 u16 phy_data_swapped;
435 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
437 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
438 DEBUGOUT1("PHY Address %d is out of range\n", offset);
439 return -E1000_ERR_PARAM;
442 /* Swap the data bytes for the I2C interface */
443 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
446 * Set up Op-code, Phy Address, and register address in the I2CCMD
447 * register. The MAC will take care of interfacing with the
448 * PHY to retrieve the desired data.
450 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
451 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
452 E1000_I2CCMD_OPCODE_WRITE |
455 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
457 /* Poll the ready bit to see if the I2C read completed */
458 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
460 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
461 if (i2ccmd & E1000_I2CCMD_READY)
464 if (!(i2ccmd & E1000_I2CCMD_READY)) {
465 DEBUGOUT("I2CCMD Write did not complete\n");
466 return -E1000_ERR_PHY;
468 if (i2ccmd & E1000_I2CCMD_ERROR) {
469 DEBUGOUT("I2CCMD Error bit set\n");
470 return -E1000_ERR_PHY;
473 return E1000_SUCCESS;
477 * e1000_get_phy_id_82575 - Retreive PHY addr and id
478 * @hw: pointer to the HW structure
480 * Retreives the PHY address and ID for both PHY's which do and do not use
483 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
485 struct e1000_phy_info *phy = &hw->phy;
486 s32 ret_val = E1000_SUCCESS;
489 DEBUGFUNC("e1000_get_phy_id_82575");
492 * For SGMII PHYs, we try the list of possible addresses until
493 * we find one that works. For non-SGMII PHYs
494 * (e.g. integrated copper PHYs), an address of 1 should
495 * work. The result of this function should mean phy->phy_addr
496 * and phy->id are set correctly.
498 if (!(e1000_sgmii_active_82575(hw))) {
500 ret_val = e1000_get_phy_id(hw);
505 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
506 * Therefore, we need to test 1-7
508 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
509 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
510 if (ret_val == E1000_SUCCESS) {
511 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
515 * At the time of this writing, The M88 part is
516 * the only supported SGMII PHY product.
518 if (phy_id == M88_VENDOR)
521 DEBUGOUT1("PHY address %u was unreadable\n",
526 /* A valid PHY type couldn't be found. */
527 if (phy->addr == 8) {
529 ret_val = -E1000_ERR_PHY;
533 ret_val = e1000_get_phy_id(hw);
540 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
541 * @hw: pointer to the HW structure
543 * Resets the PHY using the serial gigabit media independent interface.
545 STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
549 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
552 * This isn't a true "hard" reset, but is the only reset
553 * available to us at this time.
556 DEBUGOUT("Soft resetting SGMII attached PHY...\n");
559 * SFP documentation requires the following to configure the SPF module
560 * to work on SGMII. No further documentation is given.
562 ret_val = e1000_write_phy_reg(hw, 0x1B, 0x8084);
566 ret_val = e1000_phy_commit(hw);
573 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
574 * @hw: pointer to the HW structure
575 * @active: TRUE to enable LPLU, FALSE to disable
577 * Sets the LPLU D0 state according to the active flag. When
578 * activating LPLU this function also disables smart speed
579 * and vice versa. LPLU will not be activated unless the
580 * device autonegotiation advertisement meets standards of
581 * either 10 or 10/100 or 10/100/1000 at all duplexes.
582 * This is a function pointer entry point only called by
583 * PHY setup routines.
585 STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
587 struct e1000_phy_info *phy = &hw->phy;
591 DEBUGFUNC("e1000_set_d0_lplu_state_82575");
593 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
598 data |= IGP02E1000_PM_D0_LPLU;
599 ret_val = e1000_write_phy_reg(hw,
600 IGP02E1000_PHY_POWER_MGMT,
605 /* When LPLU is enabled, we should disable SmartSpeed */
606 ret_val = e1000_read_phy_reg(hw,
607 IGP01E1000_PHY_PORT_CONFIG,
609 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
610 ret_val = e1000_write_phy_reg(hw,
611 IGP01E1000_PHY_PORT_CONFIG,
616 data &= ~IGP02E1000_PM_D0_LPLU;
617 ret_val = e1000_write_phy_reg(hw,
618 IGP02E1000_PHY_POWER_MGMT,
621 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
622 * during Dx states where the power conservation is most
623 * important. During driver activity we should enable
624 * SmartSpeed, so performance is maintained.
626 if (phy->smart_speed == e1000_smart_speed_on) {
627 ret_val = e1000_read_phy_reg(hw,
628 IGP01E1000_PHY_PORT_CONFIG,
633 data |= IGP01E1000_PSCFR_SMART_SPEED;
634 ret_val = e1000_write_phy_reg(hw,
635 IGP01E1000_PHY_PORT_CONFIG,
639 } else if (phy->smart_speed == e1000_smart_speed_off) {
640 ret_val = e1000_read_phy_reg(hw,
641 IGP01E1000_PHY_PORT_CONFIG,
646 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
647 ret_val = e1000_write_phy_reg(hw,
648 IGP01E1000_PHY_PORT_CONFIG,
660 * e1000_acquire_nvm_82575 - Request for access to EEPROM
661 * @hw: pointer to the HW structure
663 * Acquire the necessary semaphores for exclussive access to the EEPROM.
664 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
665 * Return successful if access grant bit set, else clear the request for
666 * EEPROM access and return -E1000_ERR_NVM (-1).
668 STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
672 DEBUGFUNC("e1000_acquire_nvm_82575");
674 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
678 ret_val = e1000_acquire_nvm_generic(hw);
681 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
688 * e1000_release_nvm_82575 - Release exclusive access to EEPROM
689 * @hw: pointer to the HW structure
691 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
692 * then release the semaphores acquired.
694 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw)
696 DEBUGFUNC("e1000_release_nvm_82575");
698 e1000_release_nvm_generic(hw);
699 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
703 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
704 * @hw: pointer to the HW structure
705 * @mask: specifies which semaphore to acquire
707 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
708 * will also specify which port we're acquiring the lock for.
710 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
714 u32 fwmask = mask << 16;
715 s32 ret_val = E1000_SUCCESS;
716 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
718 DEBUGFUNC("e1000_acquire_swfw_sync_82575");
720 while (i < timeout) {
721 if (e1000_get_hw_semaphore_generic(hw)) {
722 ret_val = -E1000_ERR_SWFW_SYNC;
726 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
727 if (!(swfw_sync & (fwmask | swmask)))
731 * Firmware currently using resource (fwmask)
732 * or other software thread using resource (swmask)
734 e1000_put_hw_semaphore_generic(hw);
740 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
741 ret_val = -E1000_ERR_SWFW_SYNC;
746 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
748 e1000_put_hw_semaphore_generic(hw);
755 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore
756 * @hw: pointer to the HW structure
757 * @mask: specifies which semaphore to acquire
759 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
760 * will also specify which port we're releasing the lock for.
762 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
766 DEBUGFUNC("e1000_release_swfw_sync_82575");
768 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS);
771 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
773 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
775 e1000_put_hw_semaphore_generic(hw);
779 * e1000_get_cfg_done_82575 - Read config done bit
780 * @hw: pointer to the HW structure
782 * Read the management control register for the config done bit for
783 * completion status. NOTE: silicon which is EEPROM-less will fail trying
784 * to read the config done bit, so an error is *ONLY* logged and returns
785 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
786 * would not be able to be reset or change link.
788 STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
790 s32 timeout = PHY_CFG_TIMEOUT;
791 s32 ret_val = E1000_SUCCESS;
792 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
794 DEBUGFUNC("e1000_get_cfg_done_82575");
796 if (hw->bus.func == 1)
797 mask = E1000_NVM_CFG_DONE_PORT_1;
800 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
806 DEBUGOUT("MNG configuration cycle has not completed.\n");
809 /* If EEPROM is not marked present, init the PHY manually */
810 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) &&
811 (hw->phy.type == e1000_phy_igp_3)) {
812 e1000_phy_init_script_igp3(hw);
819 * e1000_get_link_up_info_82575 - Get link speed/duplex info
820 * @hw: pointer to the HW structure
821 * @speed: stores the current speed
822 * @duplex: stores the current duplex
824 * This is a wrapper function, if using the serial gigabit media independent
825 * interface, use pcs to retreive the link speed and duplex information.
826 * Otherwise, use the generic function to get the link speed and duplex info.
828 STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
833 DEBUGFUNC("e1000_get_link_up_info_82575");
835 if (hw->phy.media_type != e1000_media_type_copper ||
836 e1000_sgmii_active_82575(hw)) {
837 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
840 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
848 * e1000_check_for_link_82575 - Check for link
849 * @hw: pointer to the HW structure
851 * If sgmii is enabled, then use the pcs register to determine link, otherwise
852 * use the generic interface for determining link.
854 STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw)
859 DEBUGFUNC("e1000_check_for_link_82575");
861 /* SGMII link check is done through the PCS register. */
862 if ((hw->phy.media_type != e1000_media_type_copper) ||
863 (e1000_sgmii_active_82575(hw)))
864 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
867 ret_val = e1000_check_for_copper_link_generic(hw);
873 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
874 * @hw: pointer to the HW structure
875 * @speed: stores the current speed
876 * @duplex: stores the current duplex
878 * Using the physical coding sub-layer (PCS), retreive the current speed and
879 * duplex, then store the values in the pointers provided.
881 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
884 struct e1000_mac_info *mac = &hw->mac;
887 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
889 /* Set up defaults for the return values of this function */
890 mac->serdes_has_link = FALSE;
895 * Read the PCS Status register for link state. For non-copper mode,
896 * the status register is not accurate. The PCS status register is
899 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
902 * The link up bit determines when link is up on autoneg. The sync ok
903 * gets set once both sides sync up and agree upon link. Stable link
904 * can be determined by checking for both link up and link sync ok
906 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
907 mac->serdes_has_link = TRUE;
909 /* Detect and store PCS speed */
910 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
912 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
918 /* Detect and store PCS duplex */
919 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
920 *duplex = FULL_DUPLEX;
922 *duplex = HALF_DUPLEX;
926 return E1000_SUCCESS;
930 * e1000_rar_set_82575 - Set receive address register
931 * @hw: pointer to the HW structure
932 * @addr: pointer to the receive address
933 * @index: receive address array register
935 * Sets the receive address array register at index to the address passed
938 void e1000_rar_set_82575(struct e1000_hw *hw, u8 *addr, u32 index)
940 DEBUGFUNC("e1000_rar_set_82575");
942 if (index < E1000_RAR_ENTRIES_82575) {
943 e1000_rar_set_generic(hw, addr, index);
952 * e1000_reset_hw_82575 - Reset hardware
953 * @hw: pointer to the HW structure
955 * This resets the hardware into a known state. This is a
956 * function pointer entry point called by the api module.
958 STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw)
963 DEBUGFUNC("e1000_reset_hw_82575");
966 * Prevent the PCI-E bus from sticking if there is no TLP connection
967 * on the last TLP read/write transaction when MAC is reset.
969 ret_val = e1000_disable_pcie_master_generic(hw);
971 DEBUGOUT("PCI-E Master disable polling has failed.\n");
974 DEBUGOUT("Masking off all interrupts\n");
975 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
977 E1000_WRITE_REG(hw, E1000_RCTL, 0);
978 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
979 E1000_WRITE_FLUSH(hw);
983 ctrl = E1000_READ_REG(hw, E1000_CTRL);
985 DEBUGOUT("Issuing a global reset to MAC\n");
986 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
988 ret_val = e1000_get_auto_rd_done_generic(hw);
991 * When auto config read does not complete, do not
992 * return with an error. This can happen in situations
993 * where there is no eeprom and prevents getting link.
995 DEBUGOUT("Auto Read Done did not complete\n");
998 /* If EEPROM is not present, run manual init scripts */
999 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0)
1000 e1000_reset_init_script_82575(hw);
1002 /* Clear any pending interrupt events. */
1003 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1004 icr = E1000_READ_REG(hw, E1000_ICR);
1006 e1000_check_alt_mac_addr_generic(hw);
1012 * e1000_init_hw_82575 - Initialize hardware
1013 * @hw: pointer to the HW structure
1015 * This inits the hardware readying it for operation.
1017 STATIC s32 e1000_init_hw_82575(struct e1000_hw *hw)
1019 struct e1000_mac_info *mac = &hw->mac;
1021 u16 i, rar_count = mac->rar_entry_count;
1023 DEBUGFUNC("e1000_init_hw_82575");
1025 /* Initialize identification LED */
1026 ret_val = e1000_id_led_init_generic(hw);
1028 DEBUGOUT("Error initializing identification LED\n");
1029 /* This is not fatal and we should not stop init due to this */
1032 /* Disabling VLAN filtering */
1033 DEBUGOUT("Initializing the IEEE VLAN\n");
1034 e1000_clear_vfta(hw);
1036 /* Setup the receive address. */
1037 e1000_init_rx_addrs_generic(hw, rar_count);
1039 /* Zero out the Multicast HASH table */
1040 DEBUGOUT("Zeroing the MTA\n");
1041 for (i = 0; i < mac->mta_reg_count; i++)
1042 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1044 /* Setup link and flow control */
1045 ret_val = e1000_setup_link(hw);
1048 * Clear all of the statistics registers (clear on read). It is
1049 * important that we do this after we have tried to establish link
1050 * because the symbol error count will increment wildly if there
1053 e1000_clear_hw_cntrs_82575(hw);
1059 * e1000_setup_copper_link_82575 - Configure copper link settings
1060 * @hw: pointer to the HW structure
1062 * Configures the link for auto-neg or forced speed and duplex. Then we check
1063 * for link, once link is established calls to configure collision distance
1064 * and flow control are called.
1066 STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1072 DEBUGFUNC("e1000_setup_copper_link_82575");
1074 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1075 ctrl |= E1000_CTRL_SLU;
1076 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1077 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1079 switch (hw->phy.type) {
1081 ret_val = e1000_copper_link_setup_m88(hw);
1083 case e1000_phy_igp_3:
1084 ret_val = e1000_copper_link_setup_igp(hw);
1085 /* Setup activity LED */
1086 led_ctrl = E1000_READ_REG(hw, E1000_LEDCTL);
1087 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1088 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1089 E1000_WRITE_REG(hw, E1000_LEDCTL, led_ctrl);
1092 ret_val = -E1000_ERR_PHY;
1099 if (hw->mac.autoneg) {
1101 * Setup autoneg and flow control advertisement
1102 * and perform autonegotiation.
1104 ret_val = e1000_copper_link_autoneg(hw);
1109 * PHY will be set to 10H, 10F, 100H or 100F
1110 * depending on user settings.
1112 DEBUGOUT("Forcing Speed and Duplex\n");
1113 ret_val = e1000_phy_force_speed_duplex(hw);
1115 DEBUGOUT("Error Forcing Speed and Duplex\n");
1120 ret_val = e1000_configure_pcs_link_82575(hw);
1125 * Check link status. Wait up to 100 microseconds for link to become
1128 ret_val = e1000_phy_has_link_generic(hw,
1129 COPPER_LINK_UP_LIMIT,
1136 DEBUGOUT("Valid link established!!!\n");
1137 /* Config the MAC and PHY after link is up */
1138 e1000_config_collision_dist_generic(hw);
1139 ret_val = e1000_config_fc_after_link_up_generic(hw);
1141 DEBUGOUT("Unable to establish link!!!\n");
1149 * e1000_setup_fiber_serdes_link_82575 - Setup link for fiber/serdes
1150 * @hw: pointer to the HW structure
1152 * Configures speed and duplex for fiber and serdes links.
1154 STATIC s32 e1000_setup_fiber_serdes_link_82575(struct e1000_hw *hw)
1158 DEBUGFUNC("e1000_setup_fiber_serdes_link_82575");
1161 * On the 82575, SerDes loopback mode persists until it is
1162 * explicitly turned off or a power cycle is performed. A read to
1163 * the register does not indicate its status. Therefore, we ensure
1164 * loopback mode is disabled during initialization.
1166 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1168 /* Force link up, set 1gb, set both sw defined pins */
1169 reg = E1000_READ_REG(hw, E1000_CTRL);
1170 reg |= E1000_CTRL_SLU |
1171 E1000_CTRL_SPD_1000 |
1173 E1000_CTRL_SWDPIN0 |
1175 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1177 /* Set switch control to serdes energy detect */
1178 reg = E1000_READ_REG(hw, E1000_CONNSW);
1179 reg |= E1000_CONNSW_ENRGSRC;
1180 E1000_WRITE_REG(hw, E1000_CONNSW, reg);
1183 * New SerDes mode allows for forcing speed or autonegotiating speed
1184 * at 1gb. Autoneg should be default set by most drivers. This is the
1185 * mode that will be compatible with older link partners and switches.
1186 * However, both are supported by the hardware and some drivers/tools.
1188 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1189 if (hw->mac.autoneg) {
1190 /* Set PCS register for autoneg */
1191 reg |= E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1192 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1193 E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1194 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1195 DEBUGOUT1("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg);
1197 /* Set PCS register for forced speed */
1198 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1199 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1200 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1201 E1000_PCS_LCTL_FSD | /* Force Speed */
1202 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1203 DEBUGOUT1("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg);
1205 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1207 return E1000_SUCCESS;
1211 * e1000_configure_pcs_link_82575 - Configure PCS link
1212 * @hw: pointer to the HW structure
1214 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1215 * only used on copper connections where the serialized gigabit media
1216 * independent interface (sgmii) is being used. Configures the link
1217 * for auto-negotiation or forces speed/duplex.
1219 static s32 e1000_configure_pcs_link_82575(struct e1000_hw *hw)
1221 struct e1000_mac_info *mac = &hw->mac;
1224 DEBUGFUNC("e1000_configure_pcs_link_82575");
1226 if (hw->phy.media_type != e1000_media_type_copper ||
1227 !(e1000_sgmii_active_82575(hw)))
1230 /* For SGMII, we need to issue a PCS autoneg restart */
1231 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1233 /* AN time out should be disabled for SGMII mode */
1234 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1237 /* Make sure forced speed and force link are not set */
1238 reg &= ~(E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1241 * The PHY should be setup prior to calling this function.
1242 * All we need to do is restart autoneg and enable autoneg.
1244 reg |= E1000_PCS_LCTL_AN_RESTART | E1000_PCS_LCTL_AN_ENABLE;
1246 /* Set PCS regiseter for forced speed */
1248 /* Turn off bits for full duplex, speed, and autoneg */
1249 reg &= ~(E1000_PCS_LCTL_FSV_1000 |
1250 E1000_PCS_LCTL_FSV_100 |
1251 E1000_PCS_LCTL_FDV_FULL |
1252 E1000_PCS_LCTL_AN_ENABLE);
1254 /* Check for duplex first */
1255 if (mac->forced_speed_duplex & E1000_ALL_FULL_DUPLEX)
1256 reg |= E1000_PCS_LCTL_FDV_FULL;
1259 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED)
1260 reg |= E1000_PCS_LCTL_FSV_100;
1262 /* Force speed and force link */
1263 reg |= E1000_PCS_LCTL_FSD |
1264 E1000_PCS_LCTL_FORCE_LINK |
1265 E1000_PCS_LCTL_FLV_LINK_UP;
1267 DEBUGOUT1("Wrote 0x%08X to PCS_LCTL to configure forced link\n",
1270 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1273 return E1000_SUCCESS;
1277 * e1000_sgmii_active_82575 - Return sgmii state
1278 * @hw: pointer to the HW structure
1280 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1281 * which can be enabled for use in the embedded applications. Simply
1282 * return the current state of the sgmii interface.
1284 static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1286 struct e1000_dev_spec_82575 *dev_spec;
1289 DEBUGFUNC("e1000_sgmii_active_82575");
1291 if (hw->mac.type != e1000_82575) {
1296 dev_spec = (struct e1000_dev_spec_82575 *)hw->dev_spec;
1298 ret_val = dev_spec->sgmii_active;
1305 * e1000_reset_init_script_82575 - Inits HW defaults after reset
1306 * @hw: pointer to the HW structure
1308 * Inits recommended HW defaults after a reset when there is no EEPROM
1309 * detected. This is only for the 82575.
1311 STATIC s32 e1000_reset_init_script_82575(struct e1000_hw* hw)
1313 DEBUGFUNC("e1000_reset_init_script_82575");
1315 if (hw->mac.type == e1000_82575) {
1316 DEBUGOUT("Running reset init script for 82575\n");
1317 /* SerDes configuration via SERDESCTRL */
1318 e1000_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1319 e1000_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1320 e1000_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1321 e1000_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1323 /* CCM configuration via CCMCTL register */
1324 e1000_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1325 e1000_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1327 /* PCIe lanes configuration */
1328 e1000_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1329 e1000_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1330 e1000_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1331 e1000_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1333 /* PCIe PLL Configuration */
1334 e1000_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1335 e1000_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1336 e1000_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1339 return E1000_SUCCESS;
1343 * e1000_read_mac_addr_82575 - Read device MAC address
1344 * @hw: pointer to the HW structure
1346 STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1348 s32 ret_val = E1000_SUCCESS;
1350 DEBUGFUNC("e1000_read_mac_addr_82575");
1351 if (e1000_check_alt_mac_addr_generic(hw))
1352 ret_val = e1000_read_mac_addr_generic(hw);
1358 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
1359 * @hw: pointer to the HW structure
1361 * Clears the hardware counters by reading the counter registers.
1363 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
1367 DEBUGFUNC("e1000_clear_hw_cntrs_82575");
1369 e1000_clear_hw_cntrs_base_generic(hw);
1371 temp = E1000_READ_REG(hw, E1000_PRC64);
1372 temp = E1000_READ_REG(hw, E1000_PRC127);
1373 temp = E1000_READ_REG(hw, E1000_PRC255);
1374 temp = E1000_READ_REG(hw, E1000_PRC511);
1375 temp = E1000_READ_REG(hw, E1000_PRC1023);
1376 temp = E1000_READ_REG(hw, E1000_PRC1522);
1377 temp = E1000_READ_REG(hw, E1000_PTC64);
1378 temp = E1000_READ_REG(hw, E1000_PTC127);
1379 temp = E1000_READ_REG(hw, E1000_PTC255);
1380 temp = E1000_READ_REG(hw, E1000_PTC511);
1381 temp = E1000_READ_REG(hw, E1000_PTC1023);
1382 temp = E1000_READ_REG(hw, E1000_PTC1522);
1384 temp = E1000_READ_REG(hw, E1000_ALGNERRC);
1385 temp = E1000_READ_REG(hw, E1000_RXERRC);
1386 temp = E1000_READ_REG(hw, E1000_TNCRS);
1387 temp = E1000_READ_REG(hw, E1000_CEXTERR);
1388 temp = E1000_READ_REG(hw, E1000_TSCTC);
1389 temp = E1000_READ_REG(hw, E1000_TSCTFC);
1391 temp = E1000_READ_REG(hw, E1000_MGTPRC);
1392 temp = E1000_READ_REG(hw, E1000_MGTPDC);
1393 temp = E1000_READ_REG(hw, E1000_MGTPTC);
1395 temp = E1000_READ_REG(hw, E1000_IAC);
1396 temp = E1000_READ_REG(hw, E1000_ICRXOC);
1398 temp = E1000_READ_REG(hw, E1000_ICRXPTC);
1399 temp = E1000_READ_REG(hw, E1000_ICRXATC);
1400 temp = E1000_READ_REG(hw, E1000_ICTXPTC);
1401 temp = E1000_READ_REG(hw, E1000_ICTXATC);
1402 temp = E1000_READ_REG(hw, E1000_ICTXQEC);
1403 temp = E1000_READ_REG(hw, E1000_ICTXQMTC);
1404 temp = E1000_READ_REG(hw, E1000_ICRXDMTC);
1406 temp = E1000_READ_REG(hw, E1000_CBTMPC);
1407 temp = E1000_READ_REG(hw, E1000_HTDPMC);
1408 temp = E1000_READ_REG(hw, E1000_CBRMPC);
1409 temp = E1000_READ_REG(hw, E1000_RPTHC);
1410 temp = E1000_READ_REG(hw, E1000_HGPTC);
1411 temp = E1000_READ_REG(hw, E1000_HTCBDPC);
1412 temp = E1000_READ_REG(hw, E1000_HGORCL);
1413 temp = E1000_READ_REG(hw, E1000_HGORCH);
1414 temp = E1000_READ_REG(hw, E1000_HGOTCL);
1415 temp = E1000_READ_REG(hw, E1000_HGOTCH);
1416 temp = E1000_READ_REG(hw, E1000_LENERRS);
1418 /* This register should not be read in copper configurations */
1419 if (hw->phy.media_type == e1000_media_type_internal_serdes)
1420 temp = E1000_READ_REG(hw, E1000_SCVPC);