2 * Copyright (c) 1997-2000 Nicolas Souchu
3 * Copyright (c) 2001 Alcove - Nicolas Souchu
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
38 #include <sys/malloc.h>
43 #include <machine/clock.h>
44 #include <machine/bus.h>
45 #include <machine/resource.h>
46 #include <machine/vmparam.h>
49 #include <isa/isareg.h>
50 #include <isa/isavar.h>
52 #include <dev/ppbus/ppbconf.h>
53 #include <dev/ppbus/ppb_msq.h>
55 #include <dev/ppc/ppcvar.h>
56 #include <dev/ppc/ppcreg.h>
60 static int ppc_isa_probe(device_t dev);
62 static void ppcintr(void *arg);
64 #define LOG_PPC(function, ppc, string) \
65 if (bootverbose) printf("%s: %s\n", function, string)
68 #define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev))
70 devclass_t ppc_devclass;
72 static device_method_t ppc_methods[] = {
73 /* device interface */
74 DEVMETHOD(device_probe, ppc_isa_probe),
75 DEVMETHOD(device_attach, ppc_attach),
76 DEVMETHOD(device_detach, ppc_detach),
79 DEVMETHOD(bus_read_ivar, ppc_read_ivar),
80 DEVMETHOD(bus_setup_intr, ppc_setup_intr),
81 DEVMETHOD(bus_teardown_intr, ppc_teardown_intr),
82 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
85 DEVMETHOD(ppbus_io, ppc_io),
86 DEVMETHOD(ppbus_exec_microseq, ppc_exec_microseq),
87 DEVMETHOD(ppbus_reset_epp, ppc_reset_epp),
88 DEVMETHOD(ppbus_setmode, ppc_setmode),
89 DEVMETHOD(ppbus_ecp_sync, ppc_ecp_sync),
90 DEVMETHOD(ppbus_read, ppc_read),
91 DEVMETHOD(ppbus_write, ppc_write),
96 static driver_t ppc_driver = {
99 sizeof(struct ppc_data),
102 static char *ppc_models[] = {
103 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306",
104 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334",
105 "SMC FDC37C935", "PC87303", 0
108 /* list of available modes */
109 static char *ppc_avms[] = {
110 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only",
111 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only",
112 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP",
113 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0
116 /* list of current executing modes
117 * Note that few modes do not actually exist.
119 static char *ppc_modes[] = {
120 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP",
121 "EPP", "EPP", "EPP", "ECP",
122 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP",
123 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0
126 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 };
130 * BIOS printer list - used by BIOS probe.
132 #define BIOS_PPC_PORTS 0x408
133 #define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS)
134 #define BIOS_MAX_PPC 4
141 ppc_ecp_sync(device_t dev) {
144 struct ppc_data *ppc = DEVTOSOFTC(dev);
146 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP))
150 if ((r & 0xe0) != PPC_ECR_EPP)
153 for (i = 0; i < 100; i++) {
160 printf("ppc%d: ECP sync failed as data still " \
161 "present in FIFO.\n", ppc->ppc_unit);
169 * Detect parallel port FIFO
172 ppc_detect_fifo(struct ppc_data *ppc)
175 char ctr_sav, ctr, cc;
179 ecr_sav = r_ecr(ppc);
180 ctr_sav = r_ctr(ppc);
182 /* enter ECP configuration mode, no interrupt, no DMA */
185 /* read PWord size - transfers in FIFO mode must be PWord aligned */
186 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK);
188 /* XXX 16 and 32 bits implementations not supported */
189 if (ppc->ppc_pword != PPC_PWORD_8) {
190 LOG_PPC(__func__, ppc, "PWord not supported");
194 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */
196 w_ctr(ppc, ctr | PCD); /* set direction to 1 */
198 /* enter ECP test mode, no interrupt, no DMA */
202 for (i=0; i<1024; i++) {
203 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
209 LOG_PPC(__func__, ppc, "can't flush FIFO");
213 /* enable interrupts, no DMA */
216 /* determine readIntrThreshold
217 * fill the FIFO until serviceIntr is set
219 for (i=0; i<1024; i++) {
220 w_fifo(ppc, (char)i);
221 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) {
222 /* readThreshold reached */
225 if (r_ecr(ppc) & PPC_FIFO_FULL) {
232 LOG_PPC(__func__, ppc, "can't fill FIFO");
236 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */
237 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */
238 w_ecr(ppc, 0xd0); /* enable interrupts */
240 /* determine writeIntrThreshold
241 * empty the FIFO until serviceIntr is set
243 for (i=ppc->ppc_fifo; i>0; i--) {
244 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) {
245 LOG_PPC(__func__, ppc, "invalid data in FIFO");
248 if (r_ecr(ppc) & PPC_SERVICE_INTR) {
249 /* writeIntrThreshold reached */
250 ppc->ppc_wthr = ppc->ppc_fifo - i+1;
252 /* if FIFO empty before the last byte, error */
253 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) {
254 LOG_PPC(__func__, ppc, "data lost in FIFO");
259 /* FIFO must be empty after the last byte */
260 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
261 LOG_PPC(__func__, ppc, "can't empty the FIFO");
278 ppc_detect_port(struct ppc_data *ppc)
281 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */
283 if (r_dtr(ppc) != 0xaa)
290 * EPP timeout, according to the PC87332 manual
291 * Semantics of clearing EPP timeout bit.
292 * PC87332 - reading SPP_STR does it...
293 * SMC - write 1 to EPP timeout bit XXX
294 * Others - (?) write 0 to EPP timeout bit
297 ppc_reset_epp_timeout(struct ppc_data *ppc)
303 w_str(ppc, r & 0xfe);
309 ppc_check_epp_timeout(struct ppc_data *ppc)
311 ppc_reset_epp_timeout(ppc);
313 return (!(r_str(ppc) & TIMEOUT));
317 * Configure current operating mode
320 ppc_generic_setmode(struct ppc_data *ppc, int mode)
324 /* check if mode is available */
325 if (mode && !(ppc->ppc_avm & mode))
328 /* if ECP mode, configure ecr register */
329 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
330 /* return to byte mode (keeping direction bit),
331 * no interrupt, no DMA to be able to change to
334 w_ecr(ppc, PPC_ECR_RESET);
335 ecr = PPC_DISABLE_INTR;
339 else if (mode & PPB_ECP)
340 /* select ECP mode */
342 else if (mode & PPB_PS2)
343 /* select PS2 mode with ECP */
346 /* select COMPATIBLE/NIBBLE mode */
352 ppc->ppc_mode = mode;
358 * The ppc driver is free to choose options like FIFO or DMA
359 * if ECP mode is available.
361 * The 'RAW' option allows the upper drivers to force the ppc mode
362 * even with FIFO, DMA available.
365 ppc_smclike_setmode(struct ppc_data *ppc, int mode)
369 /* check if mode is available */
370 if (mode && !(ppc->ppc_avm & mode))
373 /* if ECP mode, configure ecr register */
374 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
375 /* return to byte mode (keeping direction bit),
376 * no interrupt, no DMA to be able to change to
379 w_ecr(ppc, PPC_ECR_RESET);
380 ecr = PPC_DISABLE_INTR;
383 /* select EPP mode */
385 else if (mode & PPB_ECP)
386 /* select ECP mode */
388 else if (mode & PPB_PS2)
389 /* select PS2 mode with ECP */
392 /* select COMPATIBLE/NIBBLE mode */
398 ppc->ppc_mode = mode;
403 #ifdef PPC_PROBE_CHIPSET
407 * Probe for a Natsemi PC873xx-family part.
409 * References in this function are to the National Semiconductor
410 * PC87332 datasheet TL/C/11930, May 1995 revision.
412 static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0};
413 static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0};
414 static int pc873xx_irqtab[] = {5, 7, 5, 0};
416 static int pc873xx_regstab[] = {
417 PC873_FER, PC873_FAR, PC873_PTR,
418 PC873_FCR, PC873_PCR, PC873_PMC,
419 PC873_TUP, PC873_SID, PC873_PNP0,
420 PC873_PNP1, PC873_LPTBA, -1
423 static char *pc873xx_rnametab[] = {
424 "FER", "FAR", "PTR", "FCR", "PCR",
425 "PMC", "TUP", "SID", "PNP0", "PNP1",
430 ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */
432 static int index = 0;
434 int ptr, pcr, val, i;
436 while ((idport = pc873xx_basetab[index++])) {
438 /* XXX should check first to see if this location is already claimed */
441 * Pull the 873xx through the power-on ID cycle (2.2,1.).
442 * We can't use this to locate the chip as it may already have
443 * been used by the BIOS.
445 (void)inb(idport); (void)inb(idport);
446 (void)inb(idport); (void)inb(idport);
449 * Read the SID byte. Possible values are :
456 outb(idport, PC873_SID);
457 val = inb(idport + 1);
458 if ((val & 0xf0) == 0x10) {
459 ppc->ppc_model = NS_PC87332;
460 } else if ((val & 0xf8) == 0x70) {
461 ppc->ppc_model = NS_PC87306;
462 } else if ((val & 0xf8) == 0x50) {
463 ppc->ppc_model = NS_PC87334;
464 } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the
465 documentation, but probing
467 ppc->ppc_model = NS_PC87303;
469 if (bootverbose && (val != 0xff))
470 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val);
471 continue ; /* not recognised */
474 /* print registers */
477 for (i=0; pc873xx_regstab[i] != -1; i++) {
478 outb(idport, pc873xx_regstab[i]);
479 printf(" %s=0x%x", pc873xx_rnametab[i],
480 inb(idport + 1) & 0xff);
486 * We think we have one. Is it enabled and where we want it to be?
488 outb(idport, PC873_FER);
489 val = inb(idport + 1);
490 if (!(val & PC873_PPENABLE)) {
492 printf("PC873xx parallel port disabled\n");
495 outb(idport, PC873_FAR);
496 val = inb(idport + 1);
497 /* XXX we should create a driver instance for every port found */
498 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) {
500 /* First try to change the port address to that requested... */
502 switch(ppc->ppc_base) {
520 outb(idport, PC873_FAR);
521 outb(idport + 1, val);
522 outb(idport + 1, val);
524 /* Check for success by reading back the value we supposedly
525 wrote and comparing...*/
527 outb(idport, PC873_FAR);
528 val = inb(idport + 1) & 0x3;
530 /* If we fail, report the failure... */
532 if (pc873xx_porttab[val] != ppc->ppc_base) {
534 printf("PC873xx at 0x%x not for driver at port 0x%x\n",
535 pc873xx_porttab[val], ppc->ppc_base);
540 outb(idport, PC873_PTR);
541 ptr = inb(idport + 1);
543 /* get irq settings */
544 if (ppc->ppc_base == 0x378)
545 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5;
547 irq = pc873xx_irqtab[val];
550 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base);
553 * Check if irq settings are correct
555 if (irq != ppc->ppc_irq) {
557 * If the chipset is not locked and base address is 0x378,
558 * we have another chance
560 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) {
561 if (ppc->ppc_irq == 7) {
562 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
563 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
565 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
566 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
569 printf("PC873xx irq set to %d\n", ppc->ppc_irq);
572 printf("PC873xx sorry, can't change irq setting\n");
576 printf("PC873xx irq settings are correct\n");
579 outb(idport, PC873_PCR);
580 pcr = inb(idport + 1);
582 if ((ptr & PC873_CFGLOCK) || !chipset_mode) {
584 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked");
586 ppc->ppc_avm |= PPB_NIBBLE;
590 if (pcr & PC873_EPPEN) {
591 ppc->ppc_avm |= PPB_EPP;
596 if (pcr & PC873_EPP19)
597 ppc->ppc_epp = EPP_1_9;
599 ppc->ppc_epp = EPP_1_7;
601 if ((ppc->ppc_model == NS_PC87332) && bootverbose) {
602 outb(idport, PC873_PTR);
603 ptr = inb(idport + 1);
604 if (ptr & PC873_EPPRDIR)
605 printf(", Regular mode");
607 printf(", Automatic mode");
609 } else if (pcr & PC873_ECPEN) {
610 ppc->ppc_avm |= PPB_ECP;
614 if (pcr & PC873_ECPCLK) { /* XXX */
615 ppc->ppc_avm |= PPB_PS2;
620 outb(idport, PC873_PTR);
621 ptr = inb(idport + 1);
622 if (ptr & PC873_EXTENDED) {
623 ppc->ppc_avm |= PPB_SPP;
630 printf("PC873xx unlocked");
632 if (chipset_mode & PPB_ECP) {
633 if ((chipset_mode & PPB_EPP) && bootverbose)
634 printf(", ECP+EPP not supported");
637 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */
638 outb(idport + 1, pcr);
639 outb(idport + 1, pcr);
644 } else if (chipset_mode & PPB_EPP) {
645 pcr &= ~(PC873_ECPEN | PC873_ECPCLK);
646 pcr |= (PC873_EPPEN | PC873_EPP19);
647 outb(idport + 1, pcr);
648 outb(idport + 1, pcr);
650 ppc->ppc_epp = EPP_1_9; /* XXX */
655 /* enable automatic direction turnover */
656 if (ppc->ppc_model == NS_PC87332) {
657 outb(idport, PC873_PTR);
658 ptr = inb(idport + 1);
659 ptr &= ~PC873_EPPRDIR;
660 outb(idport + 1, ptr);
661 outb(idport + 1, ptr);
664 printf(", Automatic mode");
667 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN);
668 outb(idport + 1, pcr);
669 outb(idport + 1, pcr);
671 /* configure extended bit in PTR */
672 outb(idport, PC873_PTR);
673 ptr = inb(idport + 1);
675 if (chipset_mode & PPB_PS2) {
676 ptr |= PC873_EXTENDED;
682 /* default to NIBBLE mode */
683 ptr &= ~PC873_EXTENDED;
688 outb(idport + 1, ptr);
689 outb(idport + 1, ptr);
692 ppc->ppc_avm = chipset_mode;
698 ppc->ppc_type = PPC_TYPE_GENERIC;
699 ppc_generic_setmode(ppc, chipset_mode);
701 return(chipset_mode);
707 * ppc_smc37c66xgt_detect
709 * SMC FDC37C66xGT configuration.
712 ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode)
717 int csr = SMC66x_CSR; /* initial value is 0x3F0 */
719 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 };
722 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */
725 * Detection: enter configuration mode and read CRD register.
729 outb(csr, SMC665_iCODE);
730 outb(csr, SMC665_iCODE);
734 if (inb(cio) == 0x65) {
739 for (i = 0; i < 2; i++) {
741 outb(csr, SMC666_iCODE);
742 outb(csr, SMC666_iCODE);
746 if (inb(cio) == 0x66) {
751 /* Another chance, CSR may be hard-configured to be at 0x370 */
757 * If chipset not found, do not continue.
765 /* read the port's address: bits 0 and 1 of CR1 */
766 r = inb(cio) & SMC_CR1_ADDR;
767 if (port_address[(int)r] != ppc->ppc_base)
770 ppc->ppc_model = type;
773 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration
774 * If SPP mode is detected, try to set ECP+EPP mode
779 printf("ppc%d: SMC registers CR1=0x%x", ppc->ppc_unit,
783 printf(" CR4=0x%x", inb(cio) & 0xff);
790 /* autodetect mode */
792 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
793 if (type == SMC_37C666GT) {
794 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
796 printf(" configuration hardwired, supposing " \
800 if ((inb(cio) & SMC_CR1_MODE) == 0) {
801 /* already in extended parallel port mode, read CR4 */
803 r = (inb(cio) & SMC_CR4_EMODE);
807 ppc->ppc_avm |= PPB_SPP;
813 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
819 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
825 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
827 printf(" ECP+EPP SPP");
831 /* not an extended port mode */
832 ppc->ppc_avm |= PPB_SPP;
839 ppc->ppc_avm = chipset_mode;
841 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
842 if (type == SMC_37C666GT)
846 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) {
847 /* do not use ECP when the mode is not forced to */
848 outb(cio, r | SMC_CR1_MODE);
852 /* an extended mode is selected */
853 outb(cio, r & ~SMC_CR1_MODE);
855 /* read CR4 register and reset mode field */
857 r = inb(cio) & ~SMC_CR4_EMODE;
859 if (chipset_mode & PPB_ECP) {
860 if (chipset_mode & PPB_EPP) {
861 outb(cio, r | SMC_ECPEPP);
865 outb(cio, r | SMC_ECP);
871 outb(cio, r | SMC_EPPSPP);
876 ppc->ppc_avm = chipset_mode;
879 /* set FIFO threshold to 16 */
880 if (ppc->ppc_avm & PPB_ECP) {
891 if (ppc->ppc_avm & PPB_EPP) {
897 * Set the EPP protocol...
898 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7
900 if (ppc->ppc_epp == EPP_1_9)
901 outb(cio, (r & ~SMC_CR4_EPPTYPE));
903 outb(cio, (r | SMC_CR4_EPPTYPE));
906 /* end config mode */
909 ppc->ppc_type = PPC_TYPE_SMCLIKE;
910 ppc_smclike_setmode(ppc, chipset_mode);
912 return (chipset_mode);
916 * SMC FDC37C935 configuration
917 * Found on many Alpha machines
920 ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode)
926 outb(SMC935_CFG, 0x55); /* enter config mode */
927 outb(SMC935_CFG, 0x55);
930 outb(SMC935_IND, SMC935_ID); /* check device id */
931 if (inb(SMC935_DAT) == 0x2)
935 outb(SMC935_CFG, 0xaa); /* exit config mode */
939 ppc->ppc_model = type;
941 outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */
942 outb(SMC935_DAT, 3); /* which is logical device 3 */
944 /* set io port base */
945 outb(SMC935_IND, SMC935_PORTHI);
946 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8));
947 outb(SMC935_IND, SMC935_PORTLO);
948 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff));
951 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */
953 ppc->ppc_avm = chipset_mode;
954 outb(SMC935_IND, SMC935_PPMODE);
955 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */
957 /* SPP + EPP or just plain SPP */
958 if (chipset_mode & (PPB_SPP)) {
959 if (chipset_mode & PPB_EPP) {
960 if (ppc->ppc_epp == EPP_1_9) {
961 outb(SMC935_IND, SMC935_PPMODE);
962 outb(SMC935_DAT, SMC935_EPP19SPP);
964 if (ppc->ppc_epp == EPP_1_7) {
965 outb(SMC935_IND, SMC935_PPMODE);
966 outb(SMC935_DAT, SMC935_EPP17SPP);
969 outb(SMC935_IND, SMC935_PPMODE);
970 outb(SMC935_DAT, SMC935_SPP);
974 /* ECP + EPP or just plain ECP */
975 if (chipset_mode & PPB_ECP) {
976 if (chipset_mode & PPB_EPP) {
977 if (ppc->ppc_epp == EPP_1_9) {
978 outb(SMC935_IND, SMC935_PPMODE);
979 outb(SMC935_DAT, SMC935_ECPEPP19);
981 if (ppc->ppc_epp == EPP_1_7) {
982 outb(SMC935_IND, SMC935_PPMODE);
983 outb(SMC935_DAT, SMC935_ECPEPP17);
986 outb(SMC935_IND, SMC935_PPMODE);
987 outb(SMC935_DAT, SMC935_ECP);
992 outb(SMC935_CFG, 0xaa); /* exit config mode */
994 ppc->ppc_type = PPC_TYPE_SMCLIKE;
995 ppc_smclike_setmode(ppc, chipset_mode);
997 return (chipset_mode);
1001 * Winbond W83877F stuff
1003 * EFER: extended function enable register
1004 * EFIR: extended function index register
1005 * EFDR: extended function data register
1007 #define efir ((efer == 0x250) ? 0x251 : 0x3f0)
1008 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1)
1010 static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 };
1011 static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 };
1012 static int w83877f_keyiter[] = { 1, 2, 2, 1 };
1013 static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 };
1016 ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode)
1019 unsigned char r, hefere, hefras;
1021 for (i = 0; i < 4; i ++) {
1022 /* first try to enable configuration registers */
1023 efer = w83877f_efers[i];
1025 /* write the key to the EFER */
1026 for (j = 0; j < w83877f_keyiter[i]; j ++)
1027 outb (efer, w83877f_keys[i]);
1029 /* then check HEFERE and HEFRAS bits */
1031 hefere = inb(efdr) & WINB_HEFERE;
1034 hefras = inb(efdr) & WINB_HEFRAS;
1038 * 0 1 write 89h to 250h (power-on default)
1039 * 1 0 write 86h twice to 3f0h
1040 * 1 1 write 87h twice to 3f0h
1041 * 0 0 write 88h to 250h
1043 if ((hefere | hefras) == w83877f_hefs[i])
1047 return (-1); /* failed */
1050 /* check base port address - read from CR23 */
1052 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */
1055 /* read CHIP ID from CR9/bits0-3 */
1058 switch (inb(efdr) & WINB_CHIPID) {
1059 case WINB_W83877F_ID:
1060 ppc->ppc_model = WINB_W83877F;
1063 case WINB_W83877AF_ID:
1064 ppc->ppc_model = WINB_W83877AF;
1068 ppc->ppc_model = WINB_UNKNOWN;
1072 /* dump of registers */
1073 printf("ppc%d: 0x%x - ", ppc->ppc_unit, w83877f_keys[i]);
1074 for (i = 0; i <= 0xd; i ++) {
1076 printf("0x%x ", inb(efdr));
1078 for (i = 0x10; i <= 0x17; i ++) {
1080 printf("0x%x ", inb(efdr));
1083 printf("0x%x ", inb(efdr));
1084 for (i = 0x20; i <= 0x29; i ++) {
1086 printf("0x%x ", inb(efdr));
1089 printf("ppc%d:", ppc->ppc_unit);
1092 ppc->ppc_type = PPC_TYPE_GENERIC;
1094 if (!chipset_mode) {
1095 /* autodetect mode */
1099 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1);
1103 r |= (inb(efdr) & WINB_PRTMODS2);
1108 printf("ppc%d: W83757 compatible mode\n",
1110 return (-1); /* generic or SMC-like */
1117 printf(" not in parallel port mode\n");
1120 case (WINB_PARALLEL | WINB_EPP_SPP):
1121 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
1126 case (WINB_PARALLEL | WINB_ECP):
1127 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
1132 case (WINB_PARALLEL | WINB_ECP_EPP):
1133 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
1134 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1137 printf(" ECP+EPP SPP");
1140 printf("%s: unknown case (0x%x)!\n", __func__, r);
1146 /* select CR9 and set PRTMODS2 bit */
1148 outb(efdr, inb(efdr) & ~WINB_PRTMODS2);
1150 /* select CR0 and reset PRTMODSx bits */
1152 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1));
1154 if (chipset_mode & PPB_ECP) {
1155 if (chipset_mode & PPB_EPP) {
1156 outb(efdr, inb(efdr) | WINB_ECP_EPP);
1160 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1163 outb(efdr, inb(efdr) | WINB_ECP);
1168 /* select EPP_SPP otherwise */
1169 outb(efdr, inb(efdr) | WINB_EPP_SPP);
1173 ppc->ppc_avm = chipset_mode;
1179 /* exit configuration mode */
1182 switch (ppc->ppc_type) {
1183 case PPC_TYPE_SMCLIKE:
1184 ppc_smclike_setmode(ppc, chipset_mode);
1187 ppc_generic_setmode(ppc, chipset_mode);
1191 return (chipset_mode);
1196 * ppc_generic_detect
1199 ppc_generic_detect(struct ppc_data *ppc, int chipset_mode)
1201 /* default to generic */
1202 ppc->ppc_type = PPC_TYPE_GENERIC;
1205 printf("ppc%d:", ppc->ppc_unit);
1207 /* first, check for ECP */
1208 w_ecr(ppc, PPC_ECR_PS2);
1209 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) {
1210 ppc->ppc_dtm |= PPB_ECP | PPB_SPP;
1214 /* search for SMC style ECP+EPP mode */
1215 w_ecr(ppc, PPC_ECR_EPP);
1218 /* try to reset EPP timeout bit */
1219 if (ppc_check_epp_timeout(ppc)) {
1220 ppc->ppc_dtm |= PPB_EPP;
1222 if (ppc->ppc_dtm & PPB_ECP) {
1223 /* SMC like chipset found */
1224 ppc->ppc_model = SMC_LIKE;
1225 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1234 /* restore to standard mode */
1235 w_ecr(ppc, PPC_ECR_STD);
1238 /* XXX try to detect NIBBLE and PS2 modes */
1239 ppc->ppc_dtm |= PPB_NIBBLE;
1245 ppc->ppc_avm = chipset_mode;
1247 ppc->ppc_avm = ppc->ppc_dtm;
1252 switch (ppc->ppc_type) {
1253 case PPC_TYPE_SMCLIKE:
1254 ppc_smclike_setmode(ppc, chipset_mode);
1257 ppc_generic_setmode(ppc, chipset_mode);
1261 return (chipset_mode);
1267 * mode is the mode suggested at boot
1270 ppc_detect(struct ppc_data *ppc, int chipset_mode) {
1272 #ifdef PPC_PROBE_CHIPSET
1275 /* list of supported chipsets */
1276 int (*chipset_detect[])(struct ppc_data *, int) = {
1278 ppc_smc37c66xgt_detect,
1280 ppc_smc37c935_detect,
1286 /* if can't find the port and mode not forced return error */
1287 if (!ppc_detect_port(ppc) && chipset_mode == 0)
1288 return (EIO); /* failed, port not present */
1290 /* assume centronics compatible mode is supported */
1291 ppc->ppc_avm = PPB_COMPATIBLE;
1293 #ifdef PPC_PROBE_CHIPSET
1294 /* we have to differenciate available chipset modes,
1295 * chipset running modes and IEEE-1284 operating modes
1297 * after detection, the port must support running in compatible mode
1299 if (ppc->ppc_flags & 0x40) {
1301 printf("ppc: chipset forced to generic\n");
1304 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode);
1306 #ifdef PPC_PROBE_CHIPSET
1308 for (i=0; chipset_detect[i] != NULL; i++) {
1309 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) {
1310 ppc->ppc_mode = mode;
1317 /* configure/detect ECP FIFO */
1318 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80))
1319 ppc_detect_fifo(ppc);
1325 * ppc_exec_microseq()
1327 * Execute a microsequence.
1328 * Microsequence mechanism is supposed to handle fast I/O operations.
1331 ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq)
1333 struct ppc_data *ppc = DEVTOSOFTC(dev);
1334 struct ppb_microseq *mi;
1341 register int accum = 0;
1342 register char *ptr = 0;
1344 struct ppb_microseq *stack = 0;
1346 /* microsequence registers are equivalent to PC-like port registers */
1348 #define r_reg(reg,ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, reg))
1349 #define w_reg(reg, ppc, byte) (bus_space_write_1((ppc)->bst, (ppc)->bsh, reg, byte))
1351 #define INCR_PC (mi ++) /* increment program counter */
1355 switch (mi->opcode) {
1357 cc = r_reg(mi->arg[0].i, ppc);
1358 cc &= (char)mi->arg[2].i; /* clear mask */
1359 cc |= (char)mi->arg[1].i; /* assert mask */
1360 w_reg(mi->arg[0].i, ppc, cc);
1364 case MS_OP_RASSERT_P:
1368 if ((len = mi->arg[0].i) == MS_ACCUM) {
1369 accum = ppc->ppc_accum;
1370 for (; accum; accum--)
1371 w_reg(reg, ppc, *ptr++);
1372 ppc->ppc_accum = accum;
1374 for (i=0; i<len; i++)
1375 w_reg(reg, ppc, *ptr++);
1381 case MS_OP_RFETCH_P:
1383 mask = (char)mi->arg[2].i;
1386 if ((len = mi->arg[0].i) == MS_ACCUM) {
1387 accum = ppc->ppc_accum;
1388 for (; accum; accum--)
1389 *ptr++ = r_reg(reg, ppc) & mask;
1390 ppc->ppc_accum = accum;
1392 for (i=0; i<len; i++)
1393 *ptr++ = r_reg(reg, ppc) & mask;
1400 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) &
1408 /* let's suppose the next instr. is the same */
1410 for (;mi->opcode == MS_OP_RASSERT; INCR_PC)
1411 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i);
1413 if (mi->opcode == MS_OP_DELAY) {
1414 DELAY(mi->arg[0].i);
1422 tsleep(NULL, PPBPRI, "ppbdelay",
1423 mi->arg[0].i * (hz/1000));
1429 iter = mi->arg[1].i;
1430 p = (char *)mi->arg[2].p;
1432 /* XXX delay limited to 255 us */
1433 for (i=0; i<iter; i++) {
1434 w_reg(reg, ppc, *p++);
1435 DELAY((unsigned char)*p++);
1441 ppc->ppc_accum = mi->arg[0].i;
1446 if (--ppc->ppc_accum > 0)
1453 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i)
1460 if ((cc & (char)mi->arg[0].i) == 0)
1467 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) ==
1475 * If the C call returns !0 then end the microseq.
1476 * The current state of ptr is passed to the C function
1478 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr)))
1485 ppc->ppc_ptr = (char *)mi->arg[0].p;
1491 panic("%s: too much calls", __func__);
1494 /* store the state of the actual
1499 /* jump to the new microsequence */
1500 mi = (struct ppb_microseq *)mi->arg[0].p;
1507 /* retrieve microseq and pc state before the call */
1510 /* reset the stack */
1513 /* XXX return code */
1521 /* can't return to ppb level during the execution
1522 * of a submicrosequence */
1524 panic("%s: can't return to ppb level",
1527 /* update pc for ppb level of execution */
1530 /* return to ppb level of execution */
1534 panic("%s: unknown microsequence opcode 0x%x",
1535 __func__, mi->opcode);
1545 device_t dev = (device_t)arg;
1546 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(dev);
1547 u_char ctr, ecr, str;
1554 printf("![%x/%x/%x]", ctr, ecr, str);
1557 /* don't use ecp mode with IRQENABLE set */
1558 if (ctr & IRQENABLE) {
1562 /* interrupts are generated by nFault signal
1563 * only in ECP mode */
1564 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) {
1565 /* check if ppc driver has programmed the
1566 * nFault interrupt */
1567 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) {
1569 w_ecr(ppc, ecr | PPC_nFAULT_INTR);
1570 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT;
1572 /* shall be handled by underlying layers XXX */
1577 if (ppc->ppc_irqstat & PPC_IRQ_DMA) {
1578 /* disable interrupts (should be done by hardware though) */
1579 w_ecr(ppc, ecr | PPC_SERVICE_INTR);
1580 ppc->ppc_irqstat &= ~PPC_IRQ_DMA;
1583 /* check if DMA completed */
1584 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) {
1589 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA);
1592 if (ppc->ppc_dmastat == PPC_DMA_STARTED) {
1602 ppc->ppc_dmastat = PPC_DMA_COMPLETE;
1604 /* wakeup the waiting process */
1608 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) {
1610 /* classic interrupt I/O */
1611 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO;
1618 ppc_read(device_t dev, char *buf, int len, int mode)
1624 * Call this function if you want to send data in any advanced mode
1625 * of your parallel port: FIFO, DMA
1627 * If what you want is not possible (no ECP, no DMA...),
1628 * EINVAL is returned
1631 ppc_write(device_t dev, char *buf, int len, int how)
1633 struct ppc_data *ppc = DEVTOSOFTC(dev);
1634 char ecr, ecr_sav, ctr, ctr_sav;
1642 ecr_sav = r_ecr(ppc);
1643 ctr_sav = r_ctr(ppc);
1646 * Send buffer with DMA, FIFO and interrupts
1648 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_registered)) {
1650 if (ppc->ppc_dmachan > 0) {
1652 /* byte mode, no intr, no DMA, dir=0, flush fifo
1654 ecr = PPC_ECR_STD | PPC_DISABLE_INTR;
1657 /* disable nAck interrupts */
1662 ppc->ppc_dmaflags = 0;
1663 ppc->ppc_dmaddr = (caddr_t)buf;
1664 ppc->ppc_dmacnt = (u_int)len;
1666 switch (ppc->ppc_mode) {
1667 case PPB_COMPATIBLE:
1668 /* compatible mode with FIFO, no intr, DMA, dir=0 */
1669 ecr = PPC_ECR_FIFO | PPC_DISABLE_INTR | PPC_ENABLE_DMA;
1672 ecr = PPC_ECR_ECP | PPC_DISABLE_INTR | PPC_ENABLE_DMA;
1682 /* enter splhigh() not to be preempted
1683 * by the dma interrupt, we may miss
1684 * the wakeup otherwise
1688 ppc->ppc_dmastat = PPC_DMA_INIT;
1690 /* enable interrupts */
1691 ecr &= ~PPC_SERVICE_INTR;
1692 ppc->ppc_irqstat = PPC_IRQ_DMA;
1701 printf("s%d", ppc->ppc_dmacnt);
1703 ppc->ppc_dmastat = PPC_DMA_STARTED;
1705 /* Wait for the DMA completed interrupt. We hope we won't
1706 * miss it, otherwise a signal will be necessary to unlock the
1712 PPBPRI | PCATCH, "ppcdma", 0);
1714 } while (error == EWOULDBLOCK);
1724 ppc->ppc_dmaflags, ppc->ppc_dmaddr,
1725 ppc->ppc_dmacnt, ppc->ppc_dmachan);
1727 /* no dma, no interrupt, flush the fifo */
1728 w_ecr(ppc, PPC_ECR_RESET);
1730 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED;
1734 /* wait for an empty fifo */
1735 while (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
1737 for (spin=100; spin; spin--)
1738 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
1743 error = tsleep(ppc, PPBPRI | PCATCH, "ppcfifo", hz/100);
1744 if (error != EWOULDBLOCK) {
1748 /* no dma, no interrupt, flush the fifo */
1749 w_ecr(ppc, PPC_ECR_RESET);
1751 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED;
1758 /* no dma, no interrupt, flush the fifo */
1759 w_ecr(ppc, PPC_ECR_RESET);
1762 error = EINVAL; /* XXX we should FIFO and
1769 /* PDRQ must be kept unasserted until nPDACK is
1770 * deasserted for a minimum of 350ns (SMC datasheet)
1772 * Consequence may be a FIFO that never empty
1776 w_ecr(ppc, ecr_sav);
1777 w_ctr(ppc, ctr_sav);
1783 ppc_reset_epp(device_t dev)
1785 struct ppc_data *ppc = DEVTOSOFTC(dev);
1787 ppc_reset_epp_timeout(ppc);
1793 ppc_setmode(device_t dev, int mode)
1795 struct ppc_data *ppc = DEVTOSOFTC(dev);
1797 switch (ppc->ppc_type) {
1798 case PPC_TYPE_SMCLIKE:
1799 return (ppc_smclike_setmode(ppc, mode));
1802 case PPC_TYPE_GENERIC:
1804 return (ppc_generic_setmode(ppc, mode));
1812 static struct isa_pnp_id lpc_ids[] = {
1813 { 0x0004d041, "Standard parallel printer port" }, /* PNP0400 */
1814 { 0x0104d041, "ECP parallel printer port" }, /* PNP0401 */
1819 ppc_isa_probe(device_t dev)
1824 parent = device_get_parent(dev);
1826 error = ISA_PNP_PROBE(parent, dev, lpc_ids);
1829 else if (error != 0) /* XXX shall be set after detection */
1830 device_set_desc(dev, "Parallel port");
1832 return(ppc_probe(dev));
1836 ppc_probe(device_t dev)
1839 static short next_bios_ppc = 0;
1841 struct ppc_data *ppc;
1846 * Allocate the ppc_data structure.
1848 ppc = DEVTOSOFTC(dev);
1849 bzero(ppc, sizeof(struct ppc_data));
1851 ppc->rid_irq = ppc->rid_drq = ppc->rid_ioport = 0;
1852 ppc->res_irq = ppc->res_drq = ppc->res_ioport = 0;
1854 /* retrieve ISA parameters */
1855 error = bus_get_resource(dev, SYS_RES_IOPORT, 0, &port, NULL);
1859 * If port not specified, use bios list.
1862 if((next_bios_ppc < BIOS_MAX_PPC) &&
1863 (*(BIOS_PORTS+next_bios_ppc) != 0) ) {
1864 port = *(BIOS_PORTS+next_bios_ppc++);
1866 device_printf(dev, "parallel port found at 0x%x\n",
1869 device_printf(dev, "parallel port not found.\n");
1872 bus_set_resource(dev, SYS_RES_IOPORT, 0, port,
1873 IO_LPTSIZE_EXTENDED);
1878 * There isn't a bios list on alpha. Put it in the usual place.
1881 bus_set_resource(dev, SYS_RES_IOPORT, 0, 0x3bc,
1886 /* IO port is mandatory */
1888 /* Try "extended" IO port range...*/
1889 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
1890 &ppc->rid_ioport, 0, ~0,
1891 IO_LPTSIZE_EXTENDED, RF_ACTIVE);
1893 if (ppc->res_ioport != 0) {
1895 device_printf(dev, "using extended I/O port range\n");
1897 /* Failed? If so, then try the "normal" IO port range... */
1898 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
1899 &ppc->rid_ioport, 0, ~0,
1902 if (ppc->res_ioport != 0) {
1904 device_printf(dev, "using normal I/O port range\n");
1906 device_printf(dev, "cannot reserve I/O port range\n");
1911 ppc->ppc_base = rman_get_start(ppc->res_ioport);
1913 ppc->bsh = rman_get_bushandle(ppc->res_ioport);
1914 ppc->bst = rman_get_bustag(ppc->res_ioport);
1916 ppc->ppc_flags = device_get_flags(dev);
1918 if (!(ppc->ppc_flags & 0x20)) {
1919 ppc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1922 ppc->res_drq = bus_alloc_resource_any(dev, SYS_RES_DRQ,
1928 ppc->ppc_irq = rman_get_start(ppc->res_irq);
1930 ppc->ppc_dmachan = rman_get_start(ppc->res_drq);
1932 ppc->ppc_unit = device_get_unit(dev);
1933 ppc->ppc_model = GENERIC;
1935 ppc->ppc_mode = PPB_COMPATIBLE;
1936 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4;
1938 ppc->ppc_type = PPC_TYPE_GENERIC;
1941 * Try to detect the chipset and its mode.
1943 if (ppc_detect(ppc, ppc->ppc_flags & 0xf))
1949 if (ppc->res_irq != 0) {
1950 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1953 if (ppc->res_ioport != 0) {
1954 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1957 if (ppc->res_drq != 0) {
1958 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1965 ppc_attach(device_t dev)
1967 struct ppc_data *ppc = DEVTOSOFTC(dev);
1970 device_t parent = device_get_parent(dev);
1972 device_printf(dev, "%s chipset (%s) in %s mode%s\n",
1973 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm],
1974 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ?
1975 ppc_epp_protocol[ppc->ppc_epp] : "");
1978 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n",
1979 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr);
1981 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_dmachan > 0)) {
1982 /* acquire the DMA channel forever */ /* XXX */
1983 isa_dma_acquire(ppc->ppc_dmachan);
1984 isa_dmainit(ppc->ppc_dmachan, 1024); /* nlpt.BUFSIZE */
1987 /* add ppbus as a child of this isa to parallel bridge */
1988 ppbus = device_add_child(dev, "ppbus", -1);
1991 * Probe the ppbus and attach devices found.
1993 device_probe_and_attach(ppbus);
1995 /* register the ppc interrupt handler as default */
1997 /* default to the tty mask for registration */ /* XXX */
1998 if (BUS_SETUP_INTR(parent, dev, ppc->res_irq, INTR_TYPE_TTY,
1999 ppcintr, dev, &ppc->intr_cookie) == 0) {
2001 /* remember the ppcintr is registered */
2002 ppc->ppc_registered = 1;
2010 ppc_detach(device_t dev)
2012 struct ppc_data *ppc = DEVTOSOFTC(dev);
2016 if (ppc->res_irq == 0) {
2020 /* detach & delete all children */
2021 if (!device_get_children(dev, &children, &nchildren)) {
2022 for (i = 0; i < nchildren; i++)
2024 device_delete_child(dev, children[i]);
2025 free(children, M_TEMP);
2028 if (ppc->res_irq != 0) {
2029 bus_teardown_intr(dev, ppc->res_irq, ppc->intr_cookie);
2030 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
2033 if (ppc->res_ioport != 0) {
2034 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
2037 if (ppc->res_drq != 0) {
2038 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
2046 ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte)
2048 struct ppc_data *ppc = DEVTOSOFTC(ppcdev);
2051 bus_space_write_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt);
2054 bus_space_write_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
2057 bus_space_write_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
2060 bus_space_read_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt);
2063 bus_space_read_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
2066 bus_space_read_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
2069 return (r_dtr(ppc));
2071 return (r_str(ppc));
2073 return (r_ctr(ppc));
2075 return (r_epp_A(ppc));
2077 return (r_epp_D(ppc));
2079 return (r_ecr(ppc));
2081 return (r_fifo(ppc));
2104 panic("%s: unknown I/O operation", __func__);
2108 return (0); /* not significative */
2112 ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val)
2114 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus);
2117 case PPC_IVAR_EPP_PROTO:
2118 *val = (u_long)ppc->ppc_epp;
2121 *val = (u_long)ppc->ppc_irq;
2131 * Resource is useless here since ppbus devices' interrupt handlers are
2132 * multiplexed to the same resource initially allocated by ppc
2135 ppc_setup_intr(device_t bus, device_t child, struct resource *r, int flags,
2136 void (*ihand)(void *), void *arg, void **cookiep)
2139 struct ppc_data *ppc = DEVTOSOFTC(bus);
2141 if (ppc->ppc_registered) {
2142 /* XXX refuse registration if DMA is in progress */
2144 /* first, unregister the default interrupt handler */
2145 if ((error = BUS_TEARDOWN_INTR(device_get_parent(bus),
2146 bus, ppc->res_irq, ppc->intr_cookie)))
2149 /* bus_deactivate_resource(bus, SYS_RES_IRQ, ppc->rid_irq, */
2150 /* ppc->res_irq); */
2152 /* DMA/FIFO operation won't be possible anymore */
2153 ppc->ppc_registered = 0;
2156 /* pass registration to the upper layer, ignore the incoming resource */
2157 return (BUS_SETUP_INTR(device_get_parent(bus), child,
2158 r, flags, ihand, arg, cookiep));
2162 * When no underlying device has a registered interrupt, register the ppc
2166 ppc_teardown_intr(device_t bus, device_t child, struct resource *r, void *ih)
2169 struct ppc_data *ppc = DEVTOSOFTC(bus);
2170 device_t parent = device_get_parent(bus);
2172 /* pass unregistration to the upper layer */
2173 if ((error = BUS_TEARDOWN_INTR(parent, child, r, ih)))
2176 /* default to the tty mask for registration */ /* XXX */
2178 !(error = BUS_SETUP_INTR(parent, bus, ppc->res_irq,
2179 INTR_TYPE_TTY, ppcintr, bus, &ppc->intr_cookie))) {
2181 /* remember the ppcintr is registered */
2182 ppc->ppc_registered = 1;
2188 DRIVER_MODULE(ppc, isa, ppc_driver, ppc_devclass, 0, 0);
2189 DRIVER_MODULE(ppc, acpi, ppc_driver, ppc_devclass, 0, 0);
2190 MODULE_DEPEND(ppc, ppbus, 1, 1, 1);