2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Networking Software Engineer
45 * This driver is designed to support RealTek's next generation of
46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
51 * with the older 8139 family, however it also supports a special
52 * C+ mode of operation that provides several new performance enhancing
53 * features. These include:
55 * o Descriptor based DMA mechanism. Each descriptor represents
56 * a single packet fragment. Data buffers may be aligned on
61 * o TCP/IP checksum offload for both RX and TX
63 * o High and normal priority transmit DMA rings
65 * o VLAN tag insertion and extraction
67 * o TCP large send (segmentation offload)
69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
70 * programming API is fairly straightforward. The RX filtering, EEPROM
71 * access and PHY access is the same as it is on the older 8139 series
74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
75 * same programming API and feature set as the 8139C+ with the following
76 * differences and additions:
82 * o GMII and TBI ports/registers for interfacing with copper
85 * o RX and TX DMA rings can have up to 1024 descriptors
86 * (the 8139C+ allows a maximum of 64)
88 * o Slight differences in register layout from the 8139C+
90 * The TX start and timer interrupt registers are at different locations
91 * on the 8169 than they are on the 8139C+. Also, the status word in the
92 * RX descriptor has a slightly different bit layout. The 8169 does not
93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
97 * (the 'S' stands for 'single-chip'). These devices have the same
98 * programming API as the older 8169, but also have some vendor-specific
99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
102 * This driver takes advantage of the RX and TX checksum offload and
103 * VLAN tag insertion/extraction features. It also implements TX
104 * interrupt moderation using the timer interrupt registers, which
105 * significantly reduces TX interrupt load. There is also support
106 * for jumbo frames, however the 8169/8169S/8110S can not transmit
107 * jumbo frames larger than 7440, so the max MTU possible with this
108 * driver is 7422 bytes.
111 #ifdef HAVE_KERNEL_OPTION_HEADERS
112 #include "opt_device_polling.h"
115 #include <sys/param.h>
116 #include <sys/endian.h>
117 #include <sys/systm.h>
118 #include <sys/sockio.h>
119 #include <sys/mbuf.h>
120 #include <sys/malloc.h>
121 #include <sys/module.h>
122 #include <sys/kernel.h>
123 #include <sys/socket.h>
124 #include <sys/lock.h>
125 #include <sys/mutex.h>
126 #include <sys/taskqueue.h>
129 #include <net/if_arp.h>
130 #include <net/ethernet.h>
131 #include <net/if_dl.h>
132 #include <net/if_media.h>
133 #include <net/if_types.h>
134 #include <net/if_vlan_var.h>
138 #include <machine/bus.h>
139 #include <machine/resource.h>
141 #include <sys/rman.h>
143 #include <dev/mii/mii.h>
144 #include <dev/mii/miivar.h>
146 #include <dev/pci/pcireg.h>
147 #include <dev/pci/pcivar.h>
149 MODULE_DEPEND(re, pci, 1, 1, 1);
150 MODULE_DEPEND(re, ether, 1, 1, 1);
151 MODULE_DEPEND(re, miibus, 1, 1, 1);
153 /* "device miibus" required. See GENERIC if you get errors here. */
154 #include "miibus_if.h"
157 * Default to using PIO access for this driver.
159 #define RE_USEIOSPACE
161 #include <pci/if_rlreg.h>
163 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
166 * Various supported device vendors/types and their names.
168 static struct rl_type re_devs[] = {
169 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169S,
170 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
171 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169_8110SB,
172 "D-Link DGE-528(T) Rev.B1 Gigabit Ethernet Adapter" },
173 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS,
174 "RealTek 8139C+ 10/100BaseTX" },
175 { RT_VENDORID, RT_DEVICEID_8101E, RL_HWREV_8101E,
176 "RealTek 8101E PCIe 10/100baseTX" },
177 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN1,
178 "RealTek 8168/8111B PCIe Gigabit Ethernet" },
179 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN2,
180 "RealTek 8168/8111B PCIe Gigabit Ethernet" },
181 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN3,
182 "RealTek 8168/8111B PCIe Gigabit Ethernet" },
183 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169,
184 "RealTek 8169 Gigabit Ethernet" },
185 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S,
186 "RealTek 8169S Single-chip Gigabit Ethernet" },
187 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SB,
188 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" },
189 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SC,
190 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
191 { RT_VENDORID, RT_DEVICEID_8169SC, RL_HWREV_8169_8110SC,
192 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
193 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S,
194 "RealTek 8110S Single-chip Gigabit Ethernet" },
195 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S,
196 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" },
197 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, RL_HWREV_8169S,
198 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" },
199 { USR_VENDORID, USR_DEVICEID_997902, RL_HWREV_8169S,
200 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" },
204 static struct rl_hwrev re_hwrevs[] = {
205 { RL_HWREV_8139, RL_8139, "" },
206 { RL_HWREV_8139A, RL_8139, "A" },
207 { RL_HWREV_8139AG, RL_8139, "A-G" },
208 { RL_HWREV_8139B, RL_8139, "B" },
209 { RL_HWREV_8130, RL_8139, "8130" },
210 { RL_HWREV_8139C, RL_8139, "C" },
211 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" },
212 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"},
213 { RL_HWREV_8168_SPIN1, RL_8169, "8168"},
214 { RL_HWREV_8169, RL_8169, "8169"},
215 { RL_HWREV_8169S, RL_8169, "8169S"},
216 { RL_HWREV_8110S, RL_8169, "8110S"},
217 { RL_HWREV_8169_8110SB, RL_8169, "8169SB"},
218 { RL_HWREV_8169_8110SC, RL_8169, "8169SC"},
219 { RL_HWREV_8100, RL_8139, "8100"},
220 { RL_HWREV_8101, RL_8139, "8101"},
221 { RL_HWREV_8100E, RL_8169, "8100E"},
222 { RL_HWREV_8101E, RL_8169, "8101E"},
223 { RL_HWREV_8168_SPIN2, RL_8169, "8168"},
224 { RL_HWREV_8168_SPIN3, RL_8169, "8168"},
228 static int re_probe (device_t);
229 static int re_attach (device_t);
230 static int re_detach (device_t);
232 static int re_encap (struct rl_softc *, struct mbuf **, int *);
234 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int);
235 static void re_dma_map_desc (void *, bus_dma_segment_t *, int,
237 static int re_allocmem (device_t, struct rl_softc *);
238 static int re_newbuf (struct rl_softc *, int, struct mbuf *);
239 static int re_rx_list_init (struct rl_softc *);
240 static int re_tx_list_init (struct rl_softc *);
242 static __inline void re_fixup_rx
245 static int re_rxeof (struct rl_softc *);
246 static void re_txeof (struct rl_softc *);
247 #ifdef DEVICE_POLLING
248 static void re_poll (struct ifnet *, enum poll_cmd, int);
249 static void re_poll_locked (struct ifnet *, enum poll_cmd, int);
251 static void re_intr (void *);
252 static void re_tick (void *);
253 static void re_tx_task (void *, int);
254 static void re_int_task (void *, int);
255 static void re_start (struct ifnet *);
256 static int re_ioctl (struct ifnet *, u_long, caddr_t);
257 static void re_init (void *);
258 static void re_init_locked (struct rl_softc *);
259 static void re_stop (struct rl_softc *);
260 static void re_watchdog (struct rl_softc *);
261 static int re_suspend (device_t);
262 static int re_resume (device_t);
263 static void re_shutdown (device_t);
264 static int re_ifmedia_upd (struct ifnet *);
265 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *);
267 static void re_eeprom_putbyte (struct rl_softc *, int);
268 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *);
269 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int);
270 static int re_gmii_readreg (device_t, int, int);
271 static int re_gmii_writereg (device_t, int, int, int);
273 static int re_miibus_readreg (device_t, int, int);
274 static int re_miibus_writereg (device_t, int, int, int);
275 static void re_miibus_statchg (device_t);
277 static void re_setmulti (struct rl_softc *);
278 static void re_reset (struct rl_softc *);
281 static int re_diag (struct rl_softc *);
285 #define RL_RES SYS_RES_IOPORT
286 #define RL_RID RL_PCI_LOIO
288 #define RL_RES SYS_RES_MEMORY
289 #define RL_RID RL_PCI_LOMEM
292 static device_method_t re_methods[] = {
293 /* Device interface */
294 DEVMETHOD(device_probe, re_probe),
295 DEVMETHOD(device_attach, re_attach),
296 DEVMETHOD(device_detach, re_detach),
297 DEVMETHOD(device_suspend, re_suspend),
298 DEVMETHOD(device_resume, re_resume),
299 DEVMETHOD(device_shutdown, re_shutdown),
302 DEVMETHOD(bus_print_child, bus_generic_print_child),
303 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
306 DEVMETHOD(miibus_readreg, re_miibus_readreg),
307 DEVMETHOD(miibus_writereg, re_miibus_writereg),
308 DEVMETHOD(miibus_statchg, re_miibus_statchg),
313 static driver_t re_driver = {
316 sizeof(struct rl_softc)
319 static devclass_t re_devclass;
321 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0);
322 DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0);
323 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
326 CSR_WRITE_1(sc, RL_EECMD, \
327 CSR_READ_1(sc, RL_EECMD) | x)
330 CSR_WRITE_1(sc, RL_EECMD, \
331 CSR_READ_1(sc, RL_EECMD) & ~x)
334 * Send a read command and address to the EEPROM, check for ACK.
337 re_eeprom_putbyte(sc, addr)
343 d = addr | (RL_9346_READ << sc->rl_eewidth);
346 * Feed in each bit and strobe the clock.
349 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) {
351 EE_SET(RL_EE_DATAIN);
353 EE_CLR(RL_EE_DATAIN);
366 * Read a word of data stored in the EEPROM at address 'addr.'
369 re_eeprom_getword(sc, addr, dest)
378 * Send address of word we want to read.
380 re_eeprom_putbyte(sc, addr);
383 * Start reading bits from EEPROM.
385 for (i = 0x8000; i; i >>= 1) {
388 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
400 * Read a sequence of words from the EEPROM.
403 re_read_eeprom(sc, dest, off, cnt)
410 u_int16_t word = 0, *ptr;
412 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
416 for (i = 0; i < cnt; i++) {
417 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL);
418 re_eeprom_getword(sc, off + i, &word);
419 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL);
420 ptr = (u_int16_t *)(dest + (i * 2));
424 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
430 re_gmii_readreg(dev, phy, reg)
441 sc = device_get_softc(dev);
443 /* Let the rgephy driver read the GMEDIASTAT register */
445 if (reg == RL_GMEDIASTAT) {
446 rval = CSR_READ_1(sc, RL_GMEDIASTAT);
450 CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
453 for (i = 0; i < RL_TIMEOUT; i++) {
454 rval = CSR_READ_4(sc, RL_PHYAR);
455 if (rval & RL_PHYAR_BUSY)
460 if (i == RL_TIMEOUT) {
461 device_printf(sc->rl_dev, "PHY read failed\n");
465 return (rval & RL_PHYAR_PHYDATA);
469 re_gmii_writereg(dev, phy, reg, data)
477 sc = device_get_softc(dev);
479 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
480 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
483 for (i = 0; i < RL_TIMEOUT; i++) {
484 rval = CSR_READ_4(sc, RL_PHYAR);
485 if (!(rval & RL_PHYAR_BUSY))
490 if (i == RL_TIMEOUT) {
491 device_printf(sc->rl_dev, "PHY write failed\n");
499 re_miibus_readreg(dev, phy, reg)
505 u_int16_t re8139_reg = 0;
507 sc = device_get_softc(dev);
509 if (sc->rl_type == RL_8169) {
510 rval = re_gmii_readreg(dev, phy, reg);
514 /* Pretend the internal PHY is only at address 0 */
520 re8139_reg = RL_BMCR;
523 re8139_reg = RL_BMSR;
526 re8139_reg = RL_ANAR;
529 re8139_reg = RL_ANER;
532 re8139_reg = RL_LPAR;
538 * Allow the rlphy driver to read the media status
539 * register. If we have a link partner which does not
540 * support NWAY, this is the register which will tell
541 * us the results of parallel detection.
544 rval = CSR_READ_1(sc, RL_MEDIASTAT);
547 device_printf(sc->rl_dev, "bad phy register\n");
550 rval = CSR_READ_2(sc, re8139_reg);
551 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) {
552 /* 8139C+ has different bit layout. */
553 rval &= ~(BMCR_LOOP | BMCR_ISO);
559 re_miibus_writereg(dev, phy, reg, data)
564 u_int16_t re8139_reg = 0;
567 sc = device_get_softc(dev);
569 if (sc->rl_type == RL_8169) {
570 rval = re_gmii_writereg(dev, phy, reg, data);
574 /* Pretend the internal PHY is only at address 0 */
580 re8139_reg = RL_BMCR;
581 if (sc->rl_type == RL_8139CPLUS) {
582 /* 8139C+ has different bit layout. */
583 data &= ~(BMCR_LOOP | BMCR_ISO);
587 re8139_reg = RL_BMSR;
590 re8139_reg = RL_ANAR;
593 re8139_reg = RL_ANER;
596 re8139_reg = RL_LPAR;
603 device_printf(sc->rl_dev, "bad phy register\n");
606 CSR_WRITE_2(sc, re8139_reg, data);
611 re_miibus_statchg(dev)
618 * Program the 64-bit multicast hash filter.
626 u_int32_t hashes[2] = { 0, 0 };
627 struct ifmultiaddr *ifma;
637 rxfilt = CSR_READ_4(sc, RL_RXCFG);
638 rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_MULTI);
639 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
640 if (ifp->if_flags & IFF_PROMISC)
641 rxfilt |= RL_RXCFG_RX_ALLPHYS;
643 * Unlike other hardwares, we have to explicitly set
644 * RL_RXCFG_RX_MULTI to receive multicast frames in
647 rxfilt |= RL_RXCFG_RX_MULTI;
648 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
649 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
650 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
654 /* first, zot all the existing hash bits */
655 CSR_WRITE_4(sc, RL_MAR0, 0);
656 CSR_WRITE_4(sc, RL_MAR4, 0);
658 /* now program new ones */
660 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
661 if (ifma->ifma_addr->sa_family != AF_LINK)
663 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
664 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
666 hashes[0] |= (1 << h);
668 hashes[1] |= (1 << (h - 32));
674 rxfilt |= RL_RXCFG_RX_MULTI;
676 rxfilt &= ~RL_RXCFG_RX_MULTI;
678 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
681 * For some unfathomable reason, RealTek decided to reverse
682 * the order of the multicast hash registers in the PCI Express
683 * parts. This means we have to write the hash pattern in reverse
684 * order for those devices.
687 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
692 case RL_HWREV_8168_SPIN1:
693 case RL_HWREV_8168_SPIN2:
694 case RL_HWREV_8168_SPIN3:
695 CSR_WRITE_4(sc, RL_MAR0, bswap32(hashes[1]));
696 CSR_WRITE_4(sc, RL_MAR4, bswap32(hashes[0]));
699 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
700 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
713 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
715 for (i = 0; i < RL_TIMEOUT; i++) {
717 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
721 device_printf(sc->rl_dev, "reset never completed!\n");
723 CSR_WRITE_1(sc, 0x82, 1);
729 * The following routine is designed to test for a defect on some
730 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
731 * lines connected to the bus, however for a 32-bit only card, they
732 * should be pulled high. The result of this defect is that the
733 * NIC will not work right if you plug it into a 64-bit slot: DMA
734 * operations will be done with 64-bit transfers, which will fail
735 * because the 64-bit data lines aren't connected.
737 * There's no way to work around this (short of talking a soldering
738 * iron to the board), however we can detect it. The method we use
739 * here is to put the NIC into digital loopback mode, set the receiver
740 * to promiscuous mode, and then try to send a frame. We then compare
741 * the frame data we sent to what was received. If the data matches,
742 * then the NIC is working correctly, otherwise we know the user has
743 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
744 * slot. In the latter case, there's no way the NIC can work correctly,
745 * so we print out a message on the console and abort the device attach.
752 struct ifnet *ifp = sc->rl_ifp;
754 struct ether_header *eh;
755 struct rl_desc *cur_rx;
758 int total_len, i, error = 0, phyaddr;
759 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
760 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
762 /* Allocate a single mbuf */
763 MGETHDR(m0, M_DONTWAIT, MT_DATA);
770 * Initialize the NIC in test mode. This sets the chip up
771 * so that it can send and receive frames, but performs the
772 * following special functions:
773 * - Puts receiver in promiscuous mode
774 * - Enables digital loopback mode
775 * - Leaves interrupts turned off
778 ifp->if_flags |= IFF_PROMISC;
783 if (sc->rl_type == RL_8169)
788 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET);
789 for (i = 0; i < RL_TIMEOUT; i++) {
790 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR);
791 if (!(status & BMCR_RESET))
795 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP);
796 CSR_WRITE_2(sc, RL_ISR, RL_INTRS);
800 /* Put some data in the mbuf */
802 eh = mtod(m0, struct ether_header *);
803 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN);
804 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN);
805 eh->ether_type = htons(ETHERTYPE_IP);
806 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
809 * Queue the packet, start transmission.
810 * Note: IF_HANDOFF() ultimately calls re_start() for us.
813 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
815 /* XXX: re_diag must not be called when in ALTQ mode */
816 IF_HANDOFF(&ifp->if_snd, m0, ifp);
820 /* Wait for it to propagate through the chip */
823 for (i = 0; i < RL_TIMEOUT; i++) {
824 status = CSR_READ_2(sc, RL_ISR);
825 CSR_WRITE_2(sc, RL_ISR, status);
826 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) ==
827 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK))
832 if (i == RL_TIMEOUT) {
833 device_printf(sc->rl_dev,
834 "diagnostic failed, failed to receive packet in"
841 * The packet should have been dumped into the first
842 * entry in the RX DMA ring. Grab it from there.
845 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
846 sc->rl_ldata.rl_rx_list_map,
847 BUS_DMASYNC_POSTREAD);
848 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
849 sc->rl_ldata.rl_rx_dmamap[0],
850 BUS_DMASYNC_POSTWRITE);
851 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
852 sc->rl_ldata.rl_rx_dmamap[0]);
854 m0 = sc->rl_ldata.rl_rx_mbuf[0];
855 sc->rl_ldata.rl_rx_mbuf[0] = NULL;
856 eh = mtod(m0, struct ether_header *);
858 cur_rx = &sc->rl_ldata.rl_rx_list[0];
859 total_len = RL_RXBYTES(cur_rx);
860 rxstat = le32toh(cur_rx->rl_cmdstat);
862 if (total_len != ETHER_MIN_LEN) {
863 device_printf(sc->rl_dev,
864 "diagnostic failed, received short packet\n");
869 /* Test that the received packet data matches what we sent. */
871 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) ||
872 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) ||
873 ntohs(eh->ether_type) != ETHERTYPE_IP) {
874 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n");
875 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n",
876 dst, ":", src, ":", ETHERTYPE_IP);
877 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n",
878 eh->ether_dhost, ":", eh->ether_shost, ":",
879 ntohs(eh->ether_type));
880 device_printf(sc->rl_dev, "You may have a defective 32-bit "
881 "NIC plugged into a 64-bit PCI slot.\n");
882 device_printf(sc->rl_dev, "Please re-install the NIC in a "
883 "32-bit slot for proper operation.\n");
884 device_printf(sc->rl_dev, "Read the re(4) man page for more "
890 /* Turn interface off, release resources */
894 ifp->if_flags &= ~IFF_PROMISC;
907 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
908 * IDs against our list and return a device name if we find a match.
920 sc = device_get_softc(dev);
922 while (t->rl_name != NULL) {
923 if ((pci_get_vendor(dev) == t->rl_vid) &&
924 (pci_get_device(dev) == t->rl_did)) {
926 * Only attach to rev. 3 of the Linksys EG1032 adapter.
927 * Rev. 2 i supported by sk(4).
929 if ((t->rl_vid == LINKSYS_VENDORID) &&
930 (t->rl_did == LINKSYS_DEVICEID_EG1032) &&
931 (pci_get_subdevice(dev) !=
932 LINKSYS_SUBDEVICE_EG1032_REV3)) {
938 * Temporarily map the I/O space
939 * so we can read the chip ID register.
942 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid,
944 if (sc->rl_res == NULL) {
946 "couldn't map ports/memory\n");
949 sc->rl_btag = rman_get_bustag(sc->rl_res);
950 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
951 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
952 bus_release_resource(dev, RL_RES,
954 if (t->rl_basetype == hwrev) {
955 device_set_desc(dev, t->rl_name);
956 return (BUS_PROBE_DEFAULT);
966 * This routine takes the segment list provided as the result of
967 * a bus_dma_map_load() operation and assigns the addresses/lengths
968 * to RealTek DMA descriptors. This can be called either by the RX
969 * code or the TX code. In the RX case, we'll probably wind up mapping
970 * at most one segment. For the TX case, there could be any number of
971 * segments since TX packets may span multiple mbufs. In either case,
972 * if the number of segments is larger than the rl_maxsegs limit
973 * specified by the caller, we abort the mapping operation. Sadly,
974 * whoever designed the buffer mapping API did not provide a way to
975 * return an error from here, so we have to fake it a bit.
979 re_dma_map_desc(arg, segs, nseg, mapsize, error)
981 bus_dma_segment_t *segs;
986 struct rl_dmaload_arg *ctx;
987 struct rl_desc *d = NULL;
997 /* Signal error to caller if there's too many segments */
998 if (nseg > ctx->rl_maxsegs) {
1004 * Map the segment array into descriptors. Note that we set the
1005 * start-of-frame and end-of-frame markers for either TX or RX, but
1006 * they really only have meaning in the TX case. (In the RX case,
1007 * it's the chip that tells us where packets begin and end.)
1008 * We also keep track of the end of the ring and set the
1009 * end-of-ring bits as needed, and we set the ownership bits
1010 * in all except the very first descriptor. (The caller will
1011 * set this descriptor later when it start transmission or
1016 d = &ctx->rl_ring[idx];
1017 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) {
1018 ctx->rl_maxsegs = 0;
1021 cmdstat = segs[i].ds_len;
1022 totlen += segs[i].ds_len;
1024 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr));
1025 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr));
1027 cmdstat |= RL_TDESC_CMD_SOF;
1029 cmdstat |= RL_TDESC_CMD_OWN;
1030 if (idx == (RL_RX_DESC_CNT - 1))
1031 cmdstat |= RL_TDESC_CMD_EOR;
1032 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags);
1039 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF);
1040 ctx->rl_maxsegs = nseg;
1045 * Map a single buffer address.
1049 re_dma_map_addr(arg, segs, nseg, error)
1051 bus_dma_segment_t *segs;
1060 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
1062 *addr = segs->ds_addr;
1066 re_allocmem(dev, sc)
1068 struct rl_softc *sc;
1075 * Allocate map for RX mbufs.
1078 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0,
1079 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1080 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW,
1081 NULL, NULL, &sc->rl_ldata.rl_mtag);
1083 device_printf(dev, "could not allocate dma tag\n");
1088 * Allocate map for TX descriptor list.
1090 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1091 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1092 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, 0,
1093 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag);
1095 device_printf(dev, "could not allocate dma tag\n");
1099 /* Allocate DMA'able memory for the TX ring */
1101 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag,
1102 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1103 &sc->rl_ldata.rl_tx_list_map);
1107 /* Load the map for the TX ring. */
1109 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag,
1110 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list,
1111 RL_TX_LIST_SZ, re_dma_map_addr,
1112 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT);
1114 /* Create DMA maps for TX buffers */
1116 for (i = 0; i < RL_TX_DESC_CNT; i++) {
1117 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0,
1118 &sc->rl_ldata.rl_tx_dmamap[i]);
1120 device_printf(dev, "can't create DMA map for TX\n");
1126 * Allocate map for RX descriptor list.
1128 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1129 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1130 NULL, RL_RX_LIST_SZ, 1, RL_RX_LIST_SZ, 0,
1131 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag);
1133 device_printf(dev, "could not allocate dma tag\n");
1137 /* Allocate DMA'able memory for the RX ring */
1139 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag,
1140 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1141 &sc->rl_ldata.rl_rx_list_map);
1145 /* Load the map for the RX ring. */
1147 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag,
1148 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list,
1149 RL_RX_LIST_SZ, re_dma_map_addr,
1150 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT);
1152 /* Create DMA maps for RX buffers */
1154 for (i = 0; i < RL_RX_DESC_CNT; i++) {
1155 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0,
1156 &sc->rl_ldata.rl_rx_dmamap[i]);
1158 device_printf(dev, "can't create DMA map for RX\n");
1167 * Attach the interface. Allocate softc structures, do ifmedia
1168 * setup and ethernet/BPF attach.
1174 u_char eaddr[ETHER_ADDR_LEN];
1175 u_int16_t as[ETHER_ADDR_LEN / 2];
1176 struct rl_softc *sc;
1178 struct rl_hwrev *hw_rev;
1180 u_int16_t re_did = 0;
1181 int error = 0, rid, i;
1183 sc = device_get_softc(dev);
1186 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1188 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
1191 * Map control/status registers.
1193 pci_enable_busmaster(dev);
1196 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid,
1199 if (sc->rl_res == NULL) {
1200 device_printf(dev, "couldn't map ports/memory\n");
1205 sc->rl_btag = rman_get_bustag(sc->rl_res);
1206 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
1208 /* Allocate interrupt */
1210 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1211 RF_SHAREABLE | RF_ACTIVE);
1213 if (sc->rl_irq == NULL) {
1214 device_printf(dev, "couldn't map interrupt\n");
1219 /* Reset the adapter. */
1225 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
1226 while (hw_rev->rl_desc != NULL) {
1227 if (hw_rev->rl_rev == hwrev) {
1228 sc->rl_type = hw_rev->rl_type;
1234 sc->rl_eewidth = RL_9356_ADDR_LEN;
1235 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
1236 if (re_did != 0x8129)
1237 sc->rl_eewidth = RL_9346_ADDR_LEN;
1240 * Get station address from the EEPROM.
1242 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3);
1243 for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
1244 as[i] = le16toh(as[i]);
1245 bcopy(as, eaddr, sizeof(eaddr));
1247 if (sc->rl_type == RL_8169) {
1248 /* Set RX length mask */
1249 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN;
1250 sc->rl_txstart = RL_GTXSTART;
1252 /* Set RX length mask */
1253 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN;
1254 sc->rl_txstart = RL_TXSTART;
1258 * Allocate the parent bus DMA tag appropriate for PCI.
1260 #define RL_NSEG_NEW 32
1261 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
1262 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1263 MAXBSIZE, RL_NSEG_NEW, BUS_SPACE_MAXSIZE_32BIT, 0,
1264 NULL, NULL, &sc->rl_parent_tag);
1268 error = re_allocmem(dev, sc);
1273 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
1275 device_printf(dev, "can not if_alloc()\n");
1281 if (mii_phy_probe(dev, &sc->rl_miibus,
1282 re_ifmedia_upd, re_ifmedia_sts)) {
1283 device_printf(dev, "MII without any phy!\n");
1288 /* Take PHY out of power down mode. */
1289 if (sc->rl_type == RL_8169) {
1292 rev = CSR_READ_4(sc, RL_TXCFG);
1293 /* HWVERID 0, 1 and 2 : bit26-30, bit23 */
1296 /* RTL8169S single chip */
1298 case RL_HWREV_8169_8110SB:
1299 case RL_HWREV_8169_8110SC:
1300 case RL_HWREV_8168_SPIN2:
1301 case RL_HWREV_8168_SPIN3:
1302 re_gmii_writereg(dev, 1, 0x1f, 0);
1303 re_gmii_writereg(dev, 1, 0x0e, 0);
1312 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1313 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1314 ifp->if_ioctl = re_ioctl;
1315 ifp->if_start = re_start;
1316 ifp->if_hwassist = RE_CSUM_FEATURES;
1317 ifp->if_capabilities = IFCAP_HWCSUM;
1318 ifp->if_capenable = ifp->if_capabilities;
1319 ifp->if_init = re_init;
1320 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN);
1321 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN;
1322 IFQ_SET_READY(&ifp->if_snd);
1324 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp);
1325 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc);
1328 * Call MI attach routine.
1330 ether_ifattach(ifp, eaddr);
1332 /* VLAN capability setup */
1333 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
1334 #ifdef IFCAP_VLAN_HWCSUM
1335 if (ifp->if_capabilities & IFCAP_HWCSUM)
1336 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
1338 ifp->if_capenable = ifp->if_capabilities;
1339 #ifdef DEVICE_POLLING
1340 ifp->if_capabilities |= IFCAP_POLLING;
1343 * Tell the upper layer(s) we support long frames.
1344 * Must appear after the call to ether_ifattach() because
1345 * ether_ifattach() sets ifi_hdrlen to the default value.
1347 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1351 * Perform hardware diagnostic on the original RTL8169.
1352 * Some 32-bit cards were incorrectly wired and would
1353 * malfunction if plugged into a 64-bit slot.
1356 if (hwrev == RL_HWREV_8169) {
1357 error = re_diag(sc);
1360 "attach aborted due to hardware diag failure\n");
1361 ether_ifdetach(ifp);
1367 /* Hook interrupt last to avoid having to lock softc */
1368 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE |
1369 INTR_FAST, re_intr, sc, &sc->rl_intrhand);
1371 device_printf(dev, "couldn't set up irq\n");
1372 ether_ifdetach(ifp);
1384 * Shutdown hardware and free up resources. This can be called any
1385 * time after the mutex has been initialized. It is called in both
1386 * the error case in attach and the normal detach case so it needs
1387 * to be careful about only freeing resources that have actually been
1394 struct rl_softc *sc;
1398 sc = device_get_softc(dev);
1400 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized"));
1402 #ifdef DEVICE_POLLING
1403 if (ifp->if_capenable & IFCAP_POLLING)
1404 ether_poll_deregister(ifp);
1406 /* These should only be active if attach succeeded */
1407 if (device_is_attached(dev)) {
1414 callout_drain(&sc->rl_stat_callout);
1415 taskqueue_drain(taskqueue_fast, &sc->rl_inttask);
1416 taskqueue_drain(taskqueue_fast, &sc->rl_txtask);
1418 * Force off the IFF_UP flag here, in case someone
1419 * still had a BPF descriptor attached to this
1420 * interface. If they do, ether_ifdetach() will cause
1421 * the BPF code to try and clear the promisc mode
1422 * flag, which will bubble down to re_ioctl(),
1423 * which will try to call re_init() again. This will
1424 * turn the NIC back on and restart the MII ticker,
1425 * which will panic the system when the kernel tries
1426 * to invoke the re_tick() function that isn't there
1429 ifp->if_flags &= ~IFF_UP;
1430 ether_ifdetach(ifp);
1433 device_delete_child(dev, sc->rl_miibus);
1434 bus_generic_detach(dev);
1437 * The rest is resource deallocation, so we should already be
1441 if (sc->rl_intrhand)
1442 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
1446 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
1448 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1450 /* Unload and free the RX DMA ring memory and map */
1452 if (sc->rl_ldata.rl_rx_list_tag) {
1453 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag,
1454 sc->rl_ldata.rl_rx_list_map);
1455 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag,
1456 sc->rl_ldata.rl_rx_list,
1457 sc->rl_ldata.rl_rx_list_map);
1458 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag);
1461 /* Unload and free the TX DMA ring memory and map */
1463 if (sc->rl_ldata.rl_tx_list_tag) {
1464 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag,
1465 sc->rl_ldata.rl_tx_list_map);
1466 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag,
1467 sc->rl_ldata.rl_tx_list,
1468 sc->rl_ldata.rl_tx_list_map);
1469 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag);
1472 /* Destroy all the RX and TX buffer maps */
1474 if (sc->rl_ldata.rl_mtag) {
1475 for (i = 0; i < RL_TX_DESC_CNT; i++)
1476 bus_dmamap_destroy(sc->rl_ldata.rl_mtag,
1477 sc->rl_ldata.rl_tx_dmamap[i]);
1478 for (i = 0; i < RL_RX_DESC_CNT; i++)
1479 bus_dmamap_destroy(sc->rl_ldata.rl_mtag,
1480 sc->rl_ldata.rl_rx_dmamap[i]);
1481 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag);
1484 /* Unload and free the stats buffer and map */
1486 if (sc->rl_ldata.rl_stag) {
1487 bus_dmamap_unload(sc->rl_ldata.rl_stag,
1488 sc->rl_ldata.rl_rx_list_map);
1489 bus_dmamem_free(sc->rl_ldata.rl_stag,
1490 sc->rl_ldata.rl_stats,
1491 sc->rl_ldata.rl_smap);
1492 bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
1495 if (sc->rl_parent_tag)
1496 bus_dma_tag_destroy(sc->rl_parent_tag);
1498 mtx_destroy(&sc->rl_mtx);
1504 re_newbuf(sc, idx, m)
1505 struct rl_softc *sc;
1509 struct rl_dmaload_arg arg;
1510 struct mbuf *n = NULL;
1514 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1519 m->m_data = m->m_ext.ext_buf;
1521 m->m_len = m->m_pkthdr.len = MCLBYTES;
1524 * This is part of an evil trick to deal with non-x86 platforms.
1525 * The RealTek chip requires RX buffers to be aligned on 64-bit
1526 * boundaries, but that will hose non-x86 machines. To get around
1527 * this, we leave some empty space at the start of each buffer
1528 * and for non-x86 hosts, we copy the buffer back six bytes
1529 * to achieve word alignment. This is slightly more efficient
1530 * than allocating a new buffer, copying the contents, and
1531 * discarding the old buffer.
1533 m_adj(m, RE_ETHER_ALIGN);
1538 arg.rl_ring = sc->rl_ldata.rl_rx_list;
1540 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag,
1541 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc,
1542 &arg, BUS_DMA_NOWAIT);
1543 if (error || arg.rl_maxsegs != 1) {
1546 if (arg.rl_maxsegs == 0)
1547 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
1548 sc->rl_ldata.rl_rx_dmamap[idx]);
1552 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN);
1553 sc->rl_ldata.rl_rx_mbuf[idx] = m;
1555 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
1556 sc->rl_ldata.rl_rx_dmamap[idx],
1557 BUS_DMASYNC_PREREAD);
1563 static __inline void
1568 uint16_t *src, *dst;
1570 src = mtod(m, uint16_t *);
1571 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src;
1573 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1576 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN;
1584 struct rl_softc *sc;
1589 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ);
1590 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf,
1591 (RL_TX_DESC_CNT * sizeof(struct mbuf *)));
1593 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
1594 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE);
1595 sc->rl_ldata.rl_tx_prodidx = 0;
1596 sc->rl_ldata.rl_tx_considx = 0;
1597 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT;
1604 struct rl_softc *sc;
1608 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ);
1609 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf,
1610 (RL_RX_DESC_CNT * sizeof(struct mbuf *)));
1612 for (i = 0; i < RL_RX_DESC_CNT; i++) {
1613 if (re_newbuf(sc, i, NULL) == ENOBUFS)
1617 /* Flush the RX descriptors */
1619 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1620 sc->rl_ldata.rl_rx_list_map,
1621 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1623 sc->rl_ldata.rl_rx_prodidx = 0;
1624 sc->rl_head = sc->rl_tail = NULL;
1630 * RX handler for C+ and 8169. For the gigE chips, we support
1631 * the reception of jumbo frames that have been fragmented
1632 * across multiple 2K mbuf cluster buffers.
1636 struct rl_softc *sc;
1641 struct rl_desc *cur_rx;
1642 u_int32_t rxstat, rxvlan;
1648 i = sc->rl_ldata.rl_rx_prodidx;
1650 /* Invalidate the descriptor memory */
1652 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1653 sc->rl_ldata.rl_rx_list_map,
1654 BUS_DMASYNC_POSTREAD);
1656 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i]) && maxpkt) {
1657 cur_rx = &sc->rl_ldata.rl_rx_list[i];
1658 m = sc->rl_ldata.rl_rx_mbuf[i];
1659 total_len = RL_RXBYTES(cur_rx);
1660 rxstat = le32toh(cur_rx->rl_cmdstat);
1661 rxvlan = le32toh(cur_rx->rl_vlanctl);
1663 /* Invalidate the RX mbuf and unload its map */
1665 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
1666 sc->rl_ldata.rl_rx_dmamap[i],
1667 BUS_DMASYNC_POSTWRITE);
1668 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
1669 sc->rl_ldata.rl_rx_dmamap[i]);
1671 if (!(rxstat & RL_RDESC_STAT_EOF)) {
1672 m->m_len = RE_RX_DESC_BUFLEN;
1673 if (sc->rl_head == NULL)
1674 sc->rl_head = sc->rl_tail = m;
1676 m->m_flags &= ~M_PKTHDR;
1677 sc->rl_tail->m_next = m;
1680 re_newbuf(sc, i, NULL);
1686 * NOTE: for the 8139C+, the frame length field
1687 * is always 12 bits in size, but for the gigE chips,
1688 * it is 13 bits (since the max RX frame length is 16K).
1689 * Unfortunately, all 32 bits in the status word
1690 * were already used, so to make room for the extra
1691 * length bit, RealTek took out the 'frame alignment
1692 * error' bit and shifted the other status bits
1693 * over one slot. The OWN, EOR, FS and LS bits are
1694 * still in the same places. We have already extracted
1695 * the frame length and checked the OWN bit, so rather
1696 * than using an alternate bit mapping, we shift the
1697 * status bits one space to the right so we can evaluate
1698 * them using the 8169 status as though it was in the
1699 * same format as that of the 8139C+.
1701 if (sc->rl_type == RL_8169)
1705 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be
1706 * set, but if CRC is clear, it will still be a valid frame.
1708 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 &&
1709 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) {
1712 * If this is part of a multi-fragment packet,
1713 * discard all the pieces.
1715 if (sc->rl_head != NULL) {
1716 m_freem(sc->rl_head);
1717 sc->rl_head = sc->rl_tail = NULL;
1719 re_newbuf(sc, i, m);
1725 * If allocating a replacement mbuf fails,
1726 * reload the current one.
1729 if (re_newbuf(sc, i, NULL)) {
1731 if (sc->rl_head != NULL) {
1732 m_freem(sc->rl_head);
1733 sc->rl_head = sc->rl_tail = NULL;
1735 re_newbuf(sc, i, m);
1742 if (sc->rl_head != NULL) {
1743 m->m_len = total_len % RE_RX_DESC_BUFLEN;
1745 m->m_len = RE_RX_DESC_BUFLEN;
1747 * Special case: if there's 4 bytes or less
1748 * in this buffer, the mbuf can be discarded:
1749 * the last 4 bytes is the CRC, which we don't
1750 * care about anyway.
1752 if (m->m_len <= ETHER_CRC_LEN) {
1753 sc->rl_tail->m_len -=
1754 (ETHER_CRC_LEN - m->m_len);
1757 m->m_len -= ETHER_CRC_LEN;
1758 m->m_flags &= ~M_PKTHDR;
1759 sc->rl_tail->m_next = m;
1762 sc->rl_head = sc->rl_tail = NULL;
1763 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1765 m->m_pkthdr.len = m->m_len =
1766 (total_len - ETHER_CRC_LEN);
1772 m->m_pkthdr.rcvif = ifp;
1774 /* Do RX checksumming if enabled */
1776 if (ifp->if_capenable & IFCAP_RXCSUM) {
1778 /* Check IP header checksum */
1779 if (rxstat & RL_RDESC_STAT_PROTOID)
1780 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1781 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD))
1782 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1784 /* Check TCP/UDP checksum */
1785 if ((RL_TCPPKT(rxstat) &&
1786 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
1787 (RL_UDPPKT(rxstat) &&
1788 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
1789 m->m_pkthdr.csum_flags |=
1790 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1791 m->m_pkthdr.csum_data = 0xffff;
1795 if (rxvlan & RL_RDESC_VLANCTL_TAG) {
1796 VLAN_INPUT_TAG_NEW(ifp, m,
1797 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)));
1802 (*ifp->if_input)(ifp, m);
1806 /* Flush the RX DMA ring */
1808 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1809 sc->rl_ldata.rl_rx_list_map,
1810 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1812 sc->rl_ldata.rl_rx_prodidx = i;
1822 struct rl_softc *sc;
1829 idx = sc->rl_ldata.rl_tx_considx;
1831 /* Invalidate the TX descriptor list */
1832 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
1833 sc->rl_ldata.rl_tx_list_map,
1834 BUS_DMASYNC_POSTREAD);
1836 while (sc->rl_ldata.rl_tx_free < RL_TX_DESC_CNT) {
1837 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat);
1838 if (txstat & RL_TDESC_CMD_OWN)
1841 sc->rl_ldata.rl_tx_list[idx].rl_bufaddr_lo = 0;
1844 * We only stash mbufs in the last descriptor
1845 * in a fragment chain, which also happens to
1846 * be the only place where the TX status bits
1849 if (txstat & RL_TDESC_CMD_EOF) {
1850 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]);
1851 sc->rl_ldata.rl_tx_mbuf[idx] = NULL;
1852 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
1853 sc->rl_ldata.rl_tx_dmamap[idx]);
1854 if (txstat & (RL_TDESC_STAT_EXCESSCOL|
1855 RL_TDESC_STAT_COLCNT))
1856 ifp->if_collisions++;
1857 if (txstat & RL_TDESC_STAT_TXERRSUM)
1862 sc->rl_ldata.rl_tx_free++;
1865 sc->rl_ldata.rl_tx_considx = idx;
1867 /* No changes made to the TX ring, so no flush needed */
1869 if (sc->rl_ldata.rl_tx_free > RL_TX_DESC_THLD)
1870 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1872 if (sc->rl_ldata.rl_tx_free < RL_TX_DESC_CNT) {
1874 * Some chips will ignore a second TX request issued
1875 * while an existing transmission is in progress. If
1876 * the transmitter goes idle but there are still
1877 * packets waiting to be sent, we need to restart the
1878 * channel here to flush them out. This only seems to
1879 * be required with the PCIe devices.
1881 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
1883 #ifdef RE_TX_MODERATION
1885 * If not all descriptors have been reaped yet, reload
1886 * the timer so that we will eventually get another
1887 * interrupt that will cause us to re-enter this routine.
1888 * This is done in case the transmitter has gone idle.
1890 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
1893 sc->rl_watchdog_timer = 0;
1900 struct rl_softc *sc;
1901 struct mii_data *mii;
1911 mii = device_get_softc(sc->rl_miibus);
1914 if (!(mii->mii_media_status & IFM_ACTIVE))
1917 if (mii->mii_media_status & IFM_ACTIVE &&
1918 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1920 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1921 taskqueue_enqueue_fast(taskqueue_fast,
1926 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
1929 #ifdef DEVICE_POLLING
1931 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1933 struct rl_softc *sc = ifp->if_softc;
1936 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1937 re_poll_locked(ifp, cmd, count);
1942 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1944 struct rl_softc *sc = ifp->if_softc;
1948 sc->rxcycles = count;
1952 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1953 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask);
1955 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1958 status = CSR_READ_2(sc, RL_ISR);
1959 if (status == 0xffff)
1962 CSR_WRITE_2(sc, RL_ISR, status);
1965 * XXX check behaviour on receiver stalls.
1968 if (status & RL_ISR_SYSTEM_ERR) {
1974 #endif /* DEVICE_POLLING */
1980 struct rl_softc *sc;
1985 status = CSR_READ_2(sc, RL_ISR);
1986 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0)
1988 CSR_WRITE_2(sc, RL_IMR, 0);
1990 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
1996 re_int_task(arg, npending)
2000 struct rl_softc *sc;
2011 status = CSR_READ_2(sc, RL_ISR);
2012 CSR_WRITE_2(sc, RL_ISR, status);
2014 if (sc->suspended || !(ifp->if_flags & IFF_UP)) {
2020 #ifdef DEVICE_POLLING
2021 if (ifp->if_capenable & IFCAP_POLLING) {
2028 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW))
2029 rval = re_rxeof(sc);
2031 #ifdef RE_TX_MODERATION
2032 if (status & (RL_ISR_TIMEOUT_EXPIRED|
2034 if (status & (RL_ISR_TX_OK|
2036 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL))
2039 if (status & RL_ISR_SYSTEM_ERR) {
2044 if (status & RL_ISR_LINKCHG) {
2045 callout_stop(&sc->rl_stat_callout);
2049 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2050 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask);
2055 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) {
2056 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
2060 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2066 re_encap(sc, m_head, idx)
2067 struct rl_softc *sc;
2068 struct mbuf **m_head;
2071 struct mbuf *m_new = NULL;
2072 struct rl_dmaload_arg arg;
2079 if (sc->rl_ldata.rl_tx_free <= RL_TX_DESC_THLD)
2083 * Set up checksum offload. Note: checksum offload bits must
2084 * appear in all descriptors of a multi-descriptor transmit
2085 * attempt. This is according to testing done with an 8169
2086 * chip. This is a requirement.
2091 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP)
2092 arg.rl_flags |= RL_TDESC_CMD_IPCSUM;
2093 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP)
2094 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM;
2095 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP)
2096 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM;
2099 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free;
2100 if (arg.rl_maxsegs > RL_TX_DESC_THLD)
2101 arg.rl_maxsegs -= RL_TX_DESC_THLD;
2102 arg.rl_ring = sc->rl_ldata.rl_tx_list;
2104 map = sc->rl_ldata.rl_tx_dmamap[*idx];
2107 * With some of the RealTek chips, using the checksum offload
2108 * support in conjunction with the autopadding feature results
2109 * in the transmission of corrupt frames. For example, if we
2110 * need to send a really small IP fragment that's less than 60
2111 * bytes in size, and IP header checksumming is enabled, the
2112 * resulting ethernet frame that appears on the wire will
2113 * have garbled payload. To work around this, if TX checksum
2114 * offload is enabled, we always manually pad short frames out
2115 * to the minimum ethernet frame size. We do this by pretending
2116 * the mbuf chain has too many fragments so the coalescing code
2117 * below can assemble the packet into a single buffer that's
2118 * padded out to the mininum frame size.
2120 * Note: this appears unnecessary for TCP, and doing it for TCP
2121 * with PCIe adapters seems to result in bad checksums.
2124 if (arg.rl_flags && !(arg.rl_flags & RL_TDESC_CMD_TCPCSUM) &&
2125 (*m_head)->m_pkthdr.len < RL_MIN_FRAMELEN)
2128 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map,
2129 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
2131 if (error && error != EFBIG) {
2132 device_printf(sc->rl_dev, "can't map mbuf (error %d)\n", error);
2136 /* Too many segments to map, coalesce into a single mbuf */
2138 if (error || arg.rl_maxsegs == 0) {
2139 if (arg.rl_maxsegs == 0)
2140 bus_dmamap_unload(sc->rl_ldata.rl_mtag, map);
2141 m_new = m_defrag(*m_head, M_DONTWAIT);
2142 if (m_new == NULL) {
2150 * Manually pad short frames, and zero the pad space
2151 * to avoid leaking data.
2153 if (m_new->m_pkthdr.len < RL_MIN_FRAMELEN) {
2154 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len,
2155 RL_MIN_FRAMELEN - m_new->m_pkthdr.len);
2156 m_new->m_pkthdr.len += RL_MIN_FRAMELEN -
2157 m_new->m_pkthdr.len;
2158 m_new->m_len = m_new->m_pkthdr.len;
2161 /* Note that we'll run over RL_TX_DESC_THLD here. */
2162 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free;
2163 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map,
2164 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
2165 if (error || arg.rl_maxsegs == 0) {
2166 device_printf(sc->rl_dev,
2167 "can't map defragmented mbuf (error %d)\n", error);
2170 if (arg.rl_maxsegs == 0)
2171 bus_dmamap_unload(sc->rl_ldata.rl_mtag, map);
2177 * Insure that the map for this transmission
2178 * is placed at the array index of the last descriptor
2179 * in this chain. (Swap last and first dmamaps.)
2181 sc->rl_ldata.rl_tx_dmamap[*idx] =
2182 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx];
2183 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map;
2185 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = *m_head;
2186 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs;
2189 * Set up hardware VLAN tagging. Note: vlan tag info must
2190 * appear in the first descriptor of a multi-descriptor
2191 * transmission attempt.
2194 mtag = VLAN_OUTPUT_TAG(sc->rl_ifp, *m_head);
2196 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl =
2197 htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG);
2199 /* Transfer ownership of packet to the chip. */
2201 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |=
2202 htole32(RL_TDESC_CMD_OWN);
2203 if (*idx != arg.rl_idx)
2204 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |=
2205 htole32(RL_TDESC_CMD_OWN);
2207 RL_DESC_INC(arg.rl_idx);
2214 re_tx_task(arg, npending)
2229 * Main transmit routine for C+ and gigE NICs.
2235 struct rl_softc *sc;
2236 struct mbuf *m_head = NULL;
2237 int idx, queued = 0;
2243 if (!sc->rl_link || ifp->if_drv_flags & IFF_DRV_OACTIVE) {
2248 idx = sc->rl_ldata.rl_tx_prodidx;
2250 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) {
2251 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2255 if (re_encap(sc, &m_head, &idx)) {
2258 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2259 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2264 * If there's a BPF listener, bounce a copy of this frame
2267 ETHER_BPF_MTAP(ifp, m_head);
2273 #ifdef RE_TX_MODERATION
2274 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT)
2275 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2281 /* Flush the TX descriptors */
2283 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2284 sc->rl_ldata.rl_tx_list_map,
2285 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2287 sc->rl_ldata.rl_tx_prodidx = idx;
2289 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2291 #ifdef RE_TX_MODERATION
2293 * Use the countdown timer for interrupt moderation.
2294 * 'TX done' interrupts are disabled. Instead, we reset the
2295 * countdown timer, which will begin counting until it hits
2296 * the value in the TIMERINT register, and then trigger an
2297 * interrupt. Each time we write to the TIMERCNT register,
2298 * the timer count is reset to 0.
2300 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2304 * Set a timeout in case the chip goes out to lunch.
2306 sc->rl_watchdog_timer = 5;
2317 struct rl_softc *sc = xsc;
2326 struct rl_softc *sc;
2328 struct ifnet *ifp = sc->rl_ifp;
2329 struct mii_data *mii;
2330 u_int32_t rxcfg = 0;
2332 uint32_t align_dummy;
2333 u_char eaddr[ETHER_ADDR_LEN];
2338 mii = device_get_softc(sc->rl_miibus);
2341 * Cancel pending I/O and free all RX/TX buffers.
2346 * Enable C+ RX and TX mode, as well as VLAN stripping and
2347 * RX checksum offload. We must configure the C+ register
2348 * before all others.
2350 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB|
2351 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW|
2352 RL_CPLUSCMD_VLANSTRIP|RL_CPLUSCMD_RXCSUM_ENB);
2355 * Init our MAC address. Even though the chipset
2356 * documentation doesn't mention it, we need to enter "Config
2357 * register write enable" mode to modify the ID registers.
2359 /* Copy MAC address on stack to align. */
2360 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN);
2361 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
2362 CSR_WRITE_4(sc, RL_IDR0,
2363 htole32(*(u_int32_t *)(&eaddr.eaddr[0])));
2364 CSR_WRITE_4(sc, RL_IDR4,
2365 htole32(*(u_int32_t *)(&eaddr.eaddr[4])));
2366 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2369 * For C+ mode, initialize the RX descriptors and mbufs.
2371 re_rx_list_init(sc);
2372 re_tx_list_init(sc);
2375 * Load the addresses of the RX and TX lists into the chip.
2378 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI,
2379 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr));
2380 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO,
2381 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr));
2383 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,
2384 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr));
2385 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
2386 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
2389 * Enable transmit and receive.
2391 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
2394 * Set the initial TX and RX configuration.
2396 if (sc->rl_testmode) {
2397 if (sc->rl_type == RL_8169)
2398 CSR_WRITE_4(sc, RL_TXCFG,
2399 RL_TXCFG_CONFIG|RL_LOOPTEST_ON);
2401 CSR_WRITE_4(sc, RL_TXCFG,
2402 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS);
2404 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
2406 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);
2408 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
2410 /* Set the individual bit to receive frames for this host only. */
2411 rxcfg = CSR_READ_4(sc, RL_RXCFG);
2412 rxcfg |= RL_RXCFG_RX_INDIV;
2414 /* If we want promiscuous mode, set the allframes bit. */
2415 if (ifp->if_flags & IFF_PROMISC)
2416 rxcfg |= RL_RXCFG_RX_ALLPHYS;
2418 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
2419 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
2422 * Set capture broadcast bit to capture broadcast frames.
2424 if (ifp->if_flags & IFF_BROADCAST)
2425 rxcfg |= RL_RXCFG_RX_BROAD;
2427 rxcfg &= ~RL_RXCFG_RX_BROAD;
2428 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
2431 * Program the multicast filter, if necessary.
2435 #ifdef DEVICE_POLLING
2437 * Disable interrupts if we are polling.
2439 if (ifp->if_capenable & IFCAP_POLLING)
2440 CSR_WRITE_2(sc, RL_IMR, 0);
2441 else /* otherwise ... */
2445 * Enable interrupts.
2447 if (sc->rl_testmode)
2448 CSR_WRITE_2(sc, RL_IMR, 0);
2450 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2451 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS);
2453 /* Set initial TX threshold */
2454 sc->rl_txthresh = RL_TX_THRESH_INIT;
2456 /* Start RX/TX process. */
2457 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
2459 /* Enable receiver and transmitter. */
2460 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
2463 #ifdef RE_TX_MODERATION
2465 * Initialize the timer interrupt register so that
2466 * a timer interrupt will be generated once the timer
2467 * reaches a certain number of ticks. The timer is
2468 * reloaded on each transmit. This gives us TX interrupt
2469 * moderation, which dramatically improves TX frame rate.
2471 if (sc->rl_type == RL_8169)
2472 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800);
2474 CSR_WRITE_4(sc, RL_TIMERINT, 0x400);
2478 * For 8169 gigE NICs, set the max allowed RX packet
2479 * size so we can receive jumbo frames.
2481 if (sc->rl_type == RL_8169)
2482 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383);
2484 if (sc->rl_testmode)
2489 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD);
2491 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2492 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2495 sc->rl_watchdog_timer = 0;
2496 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
2500 * Set media options.
2506 struct rl_softc *sc;
2507 struct mii_data *mii;
2510 mii = device_get_softc(sc->rl_miibus);
2519 * Report current media status.
2522 re_ifmedia_sts(ifp, ifmr)
2524 struct ifmediareq *ifmr;
2526 struct rl_softc *sc;
2527 struct mii_data *mii;
2530 mii = device_get_softc(sc->rl_miibus);
2535 ifmr->ifm_active = mii->mii_media_active;
2536 ifmr->ifm_status = mii->mii_media_status;
2540 re_ioctl(ifp, command, data)
2545 struct rl_softc *sc = ifp->if_softc;
2546 struct ifreq *ifr = (struct ifreq *) data;
2547 struct mii_data *mii;
2553 if (ifr->ifr_mtu > RL_JUMBO_MTU)
2555 ifp->if_mtu = ifr->ifr_mtu;
2560 if ((ifp->if_flags & IFF_UP) != 0) {
2561 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2562 if (((ifp->if_flags ^ sc->rl_if_flags)
2563 & IFF_PROMISC) != 0)
2568 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2571 sc->rl_if_flags = ifp->if_flags;
2582 mii = device_get_softc(sc->rl_miibus);
2583 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2589 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2591 #ifdef DEVICE_POLLING
2592 if (mask & IFCAP_POLLING) {
2593 if (ifr->ifr_reqcap & IFCAP_POLLING) {
2594 error = ether_poll_register(re_poll, ifp);
2598 /* Disable interrupts */
2599 CSR_WRITE_2(sc, RL_IMR, 0x0000);
2600 ifp->if_capenable |= IFCAP_POLLING;
2603 error = ether_poll_deregister(ifp);
2604 /* Enable interrupts. */
2606 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2607 ifp->if_capenable &= ~IFCAP_POLLING;
2611 #endif /* DEVICE_POLLING */
2612 if (mask & IFCAP_HWCSUM) {
2613 ifp->if_capenable ^= IFCAP_HWCSUM;
2614 if (ifp->if_capenable & IFCAP_TXCSUM)
2615 ifp->if_hwassist = RE_CSUM_FEATURES;
2617 ifp->if_hwassist = 0;
2620 if (mask & IFCAP_VLAN_HWTAGGING) {
2621 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2624 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING)
2626 #ifdef VLAN_CAPABILITIES
2627 VLAN_CAPABILITIES(ifp);
2632 error = ether_ioctl(ifp, command, data);
2641 struct rl_softc *sc;
2646 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0)
2649 device_printf(sc->rl_dev, "watchdog timeout\n");
2650 sc->rl_ifp->if_oerrors++;
2658 * Stop the adapter and free any mbufs allocated to the
2663 struct rl_softc *sc;
2672 sc->rl_watchdog_timer = 0;
2673 callout_stop(&sc->rl_stat_callout);
2674 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2676 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
2677 CSR_WRITE_2(sc, RL_IMR, 0x0000);
2678 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
2680 if (sc->rl_head != NULL) {
2681 m_freem(sc->rl_head);
2682 sc->rl_head = sc->rl_tail = NULL;
2685 /* Free the TX list buffers. */
2687 for (i = 0; i < RL_TX_DESC_CNT; i++) {
2688 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) {
2689 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
2690 sc->rl_ldata.rl_tx_dmamap[i]);
2691 m_freem(sc->rl_ldata.rl_tx_mbuf[i]);
2692 sc->rl_ldata.rl_tx_mbuf[i] = NULL;
2696 /* Free the RX list buffers. */
2698 for (i = 0; i < RL_RX_DESC_CNT; i++) {
2699 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) {
2700 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
2701 sc->rl_ldata.rl_rx_dmamap[i]);
2702 m_freem(sc->rl_ldata.rl_rx_mbuf[i]);
2703 sc->rl_ldata.rl_rx_mbuf[i] = NULL;
2709 * Device suspend routine. Stop the interface and save some PCI
2710 * settings in case the BIOS doesn't restore them properly on
2717 struct rl_softc *sc;
2719 sc = device_get_softc(dev);
2730 * Device resume routine. Restore some PCI settings in case the BIOS
2731 * doesn't, re-enable busmastering, and restart the interface if
2738 struct rl_softc *sc;
2741 sc = device_get_softc(dev);
2747 /* reinitialize interface if necessary */
2748 if (ifp->if_flags & IFF_UP)
2758 * Stop all chip I/O so that the kernel's probe routines don't
2759 * get confused by errant DMAs when rebooting.
2765 struct rl_softc *sc;
2767 sc = device_get_softc(dev);
2772 * Mark interface as down since otherwise we will panic if
2773 * interrupt comes in later on, which can happen in some
2776 sc->rl_ifp->if_flags &= ~IFF_UP;