2 * Copyright (c) 2003 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
34 #include <machine/bus.h>
36 #include <dev/uart/uart.h>
37 #include <dev/uart/uart_cpu.h>
38 #include <dev/uart/uart_bus.h>
40 #include <dev/ic/sab82532.h>
44 #define DEFAULT_RCLK 29491200
47 * NOTE: To allow us to read the baudrate divisor from the chip, we
48 * copy the value written to the write-only BGR register to an unused
49 * read-write register. We use TCR for that.
53 sab82532_delay(struct uart_bas *bas)
58 bgr = uart_getreg(bas, SAB_TCR);
59 ccr2 = uart_getreg(bas, SAB_CCR2);
61 m = (bgr >> 6) | ((ccr2 >> 4) & 0xC);
64 /* 1/10th the time to transmit 1 character (estimate). */
65 return (16000000 * divisor / bas->rclk);
69 sab82532_divisor(int rclk, int baudrate)
71 int act_baud, act_div, divisor;
77 divisor = (rclk / (baudrate << 3) + 1) >> 1;
78 if (divisor < 2 || divisor >= 1048576)
81 /* Find the best (N+1,M) pair. */
82 for (m = 1; m < 15; m++) {
87 act_baud = rclk / (act_div << 4);
89 /* 10 times error in percent: */
90 error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1;
92 /* 3.0% maximum error tolerance: */
93 if (error < -30 || error > 30)
97 return ((n - 1) | (m << 6));
104 sab82532_flush(struct uart_bas *bas, int what)
107 if (what & UART_FLUSH_TRANSMITTER) {
108 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
110 uart_setreg(bas, SAB_CMDR, SAB_CMDR_XRES);
113 if (what & UART_FLUSH_RECEIVER) {
114 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
116 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RRES);
122 sab82532_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
129 dafo = SAB_DAFO_CHL_CS8;
130 else if (databits == 7)
131 dafo = SAB_DAFO_CHL_CS7;
132 else if (databits == 6)
133 dafo = SAB_DAFO_CHL_CS6;
135 dafo = SAB_DAFO_CHL_CS5;
137 dafo |= SAB_DAFO_STOP;
139 case UART_PARITY_EVEN: dafo |= SAB_DAFO_PAR_EVEN; break;
140 case UART_PARITY_MARK: dafo |= SAB_DAFO_PAR_MARK; break;
141 case UART_PARITY_NONE: dafo |= SAB_DAFO_PAR_NONE; break;
142 case UART_PARITY_ODD: dafo |= SAB_DAFO_PAR_ODD; break;
143 case UART_PARITY_SPACE: dafo |= SAB_DAFO_PAR_SPACE; break;
144 default: return (EINVAL);
149 divisor = sab82532_divisor(bas->rclk, baudrate);
152 uart_setreg(bas, SAB_BGR, divisor & 0xff);
154 /* Allow reading the (n-1,m) tuple from the chip. */
155 uart_setreg(bas, SAB_TCR, divisor & 0xff);
157 ccr2 = uart_getreg(bas, SAB_CCR2);
158 ccr2 &= ~(SAB_CCR2_BR9 | SAB_CCR2_BR8);
159 ccr2 |= (divisor >> 2) & (SAB_CCR2_BR9 | SAB_CCR2_BR8);
160 uart_setreg(bas, SAB_CCR2, ccr2);
164 uart_setreg(bas, SAB_DAFO, dafo);
170 * Low-level UART interface.
172 static int sab82532_probe(struct uart_bas *bas);
173 static void sab82532_init(struct uart_bas *bas, int, int, int, int);
174 static void sab82532_term(struct uart_bas *bas);
175 static void sab82532_putc(struct uart_bas *bas, int);
176 static int sab82532_poll(struct uart_bas *bas);
177 static int sab82532_getc(struct uart_bas *bas);
179 struct uart_ops uart_sab82532_ops = {
180 .probe = sab82532_probe,
181 .init = sab82532_init,
182 .term = sab82532_term,
183 .putc = sab82532_putc,
184 .poll = sab82532_poll,
185 .getc = sab82532_getc,
189 sab82532_probe(struct uart_bas *bas)
196 sab82532_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
202 bas->rclk = DEFAULT_RCLK;
205 * Set all pins, except the DTR pins (pin 1 and 2) to be inputs.
206 * Pin 4 is magical, meaning that I don't know what it does, but
207 * it too has to be set to output.
209 uart_setreg(bas, SAB_PCR,
210 ~(SAB_PVR_DTR_A|SAB_PVR_DTR_B|SAB_PVR_MAGIC));
212 /* Disable port interrupts. */
213 uart_setreg(bas, SAB_PIM, 0xff);
215 /* Interrupts are active low. */
216 uart_setreg(bas, SAB_IPC, SAB_IPC_ICPL);
219 pvr = uart_getreg(bas, SAB_PVR);
222 pvr &= ~SAB_PVR_DTR_A;
225 pvr &= ~SAB_PVR_DTR_B;
228 uart_setreg(bas, SAB_PVR, pvr | SAB_PVR_MAGIC);
232 uart_setreg(bas, SAB_CCR0, 0);
235 /* set basic configuration */
236 ccr0 = SAB_CCR0_MCE|SAB_CCR0_SC_NRZ|SAB_CCR0_SM_ASYNC;
237 uart_setreg(bas, SAB_CCR0, ccr0);
239 uart_setreg(bas, SAB_CCR1, SAB_CCR1_ODS|SAB_CCR1_BCR|SAB_CCR1_CM_7);
241 uart_setreg(bas, SAB_CCR2, SAB_CCR2_BDF|SAB_CCR2_SSEL|SAB_CCR2_TOE);
243 uart_setreg(bas, SAB_CCR3, 0);
245 uart_setreg(bas, SAB_CCR4, SAB_CCR4_MCK4|SAB_CCR4_EBRG|SAB_CCR4_ICD);
247 uart_setreg(bas, SAB_MODE, SAB_MODE_FCTS|SAB_MODE_RTS|SAB_MODE_RAC);
249 uart_setreg(bas, SAB_RFC, SAB_RFC_DPS|SAB_RFC_RFDF|
250 SAB_RFC_RFTH_32CHAR);
253 sab82532_param(bas, baudrate, databits, stopbits, parity);
255 /* Clear interrupts. */
256 uart_setreg(bas, SAB_IMR0, (unsigned char)~SAB_IMR0_TCD);
257 uart_setreg(bas, SAB_IMR1, 0xff);
259 uart_getreg(bas, SAB_ISR0);
260 uart_getreg(bas, SAB_ISR1);
263 sab82532_flush(bas, UART_FLUSH_TRANSMITTER|UART_FLUSH_RECEIVER);
266 uart_setreg(bas, SAB_CCR0, ccr0|SAB_CCR0_PU);
271 sab82532_term(struct uart_bas *bas)
275 pvr = uart_getreg(bas, SAB_PVR);
278 pvr |= SAB_PVR_DTR_A;
281 pvr |= SAB_PVR_DTR_B;
284 uart_setreg(bas, SAB_PVR, pvr);
289 sab82532_putc(struct uart_bas *bas, int c)
293 /* 1/10th the time to transmit 1 character (estimate). */
294 delay = sab82532_delay(bas);
297 while ((uart_getreg(bas, SAB_STAR) & SAB_STAR_TEC) && --limit)
299 uart_setreg(bas, SAB_TIC, c);
301 while ((uart_getreg(bas, SAB_STAR) & SAB_STAR_TEC) && --limit)
306 sab82532_poll(struct uart_bas *bas)
309 if (uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE)
310 return (sab82532_getc(bas));
315 sab82532_getc(struct uart_bas *bas)
319 /* 1/10th the time to transmit 1 character (estimate). */
320 delay = sab82532_delay(bas);
322 while (!(uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE))
325 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
327 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RFRD);
330 while (!(uart_getreg(bas, SAB_ISR0) & SAB_ISR0_TCD))
333 c = uart_getreg(bas, SAB_RFIFO);
336 /* Blow away everything left in the FIFO... */
337 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
339 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RMC);
345 * High-level UART interface.
347 struct sab82532_softc {
348 struct uart_softc base;
351 static int sab82532_bus_attach(struct uart_softc *);
352 static int sab82532_bus_detach(struct uart_softc *);
353 static int sab82532_bus_flush(struct uart_softc *, int);
354 static int sab82532_bus_getsig(struct uart_softc *);
355 static int sab82532_bus_ioctl(struct uart_softc *, int, intptr_t);
356 static int sab82532_bus_ipend(struct uart_softc *);
357 static int sab82532_bus_param(struct uart_softc *, int, int, int, int);
358 static int sab82532_bus_probe(struct uart_softc *);
359 static int sab82532_bus_receive(struct uart_softc *);
360 static int sab82532_bus_setsig(struct uart_softc *, int);
361 static int sab82532_bus_transmit(struct uart_softc *);
363 static kobj_method_t sab82532_methods[] = {
364 KOBJMETHOD(uart_attach, sab82532_bus_attach),
365 KOBJMETHOD(uart_detach, sab82532_bus_detach),
366 KOBJMETHOD(uart_flush, sab82532_bus_flush),
367 KOBJMETHOD(uart_getsig, sab82532_bus_getsig),
368 KOBJMETHOD(uart_ioctl, sab82532_bus_ioctl),
369 KOBJMETHOD(uart_ipend, sab82532_bus_ipend),
370 KOBJMETHOD(uart_param, sab82532_bus_param),
371 KOBJMETHOD(uart_probe, sab82532_bus_probe),
372 KOBJMETHOD(uart_receive, sab82532_bus_receive),
373 KOBJMETHOD(uart_setsig, sab82532_bus_setsig),
374 KOBJMETHOD(uart_transmit, sab82532_bus_transmit),
378 struct uart_class uart_sab82532_class = {
381 sizeof(struct sab82532_softc),
383 .uc_rclk = DEFAULT_RCLK
386 #define SIGCHG(c, i, s, d) \
388 i |= (i & s) ? s : s | d; \
390 i = (i & s) ? (i & ~s) | d : i; \
394 sab82532_bus_attach(struct uart_softc *sc)
396 struct uart_bas *bas;
400 if (sc->sc_sysdev == NULL)
401 sab82532_init(bas, 9600, 8, 1, UART_PARITY_NONE);
403 sc->sc_rxfifosz = 32;
404 sc->sc_txfifosz = 32;
406 imr0 = SAB_IMR0_TCD|SAB_IMR0_TIME|SAB_IMR0_CDSC|SAB_IMR0_RFO|
408 uart_setreg(bas, SAB_IMR0, 0xff & ~imr0);
409 imr1 = SAB_IMR1_BRKT|SAB_IMR1_ALLS|SAB_IMR1_CSC;
410 uart_setreg(bas, SAB_IMR1, 0xff & ~imr1);
413 if (sc->sc_sysdev == NULL)
414 sab82532_bus_setsig(sc, SER_DDTR|SER_DRTS);
415 (void)sab82532_bus_getsig(sc);
420 sab82532_bus_detach(struct uart_softc *sc)
422 struct uart_bas *bas;
425 uart_setreg(bas, SAB_IMR0, 0xff);
426 uart_setreg(bas, SAB_IMR1, 0xff);
428 uart_getreg(bas, SAB_ISR0);
429 uart_getreg(bas, SAB_ISR1);
431 uart_setreg(bas, SAB_CCR0, 0);
437 sab82532_bus_flush(struct uart_softc *sc, int what)
440 mtx_lock_spin(&sc->sc_hwmtx);
441 sab82532_flush(&sc->sc_bas, what);
442 mtx_unlock_spin(&sc->sc_hwmtx);
447 sab82532_bus_getsig(struct uart_softc *sc)
449 struct uart_bas *bas;
450 uint32_t new, old, sig;
451 uint8_t pvr, star, vstr;
457 mtx_lock_spin(&sc->sc_hwmtx);
458 star = uart_getreg(bas, SAB_STAR);
459 SIGCHG(star & SAB_STAR_CTS, sig, SER_CTS, SER_DCTS);
460 vstr = uart_getreg(bas, SAB_VSTR);
461 SIGCHG(vstr & SAB_VSTR_CD, sig, SER_DCD, SER_DDCD);
462 pvr = ~uart_getreg(bas, SAB_PVR);
465 pvr &= SAB_PVR_DSR_A;
468 pvr &= SAB_PVR_DSR_B;
471 SIGCHG(pvr, sig, SER_DSR, SER_DDSR);
472 mtx_unlock_spin(&sc->sc_hwmtx);
473 new = sig & ~UART_SIGMASK_DELTA;
474 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
479 sab82532_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
481 struct uart_bas *bas;
487 mtx_lock_spin(&sc->sc_hwmtx);
489 case UART_IOCTL_BREAK:
490 dafo = uart_getreg(bas, SAB_DAFO);
492 dafo |= SAB_DAFO_XBRK;
494 dafo &= ~SAB_DAFO_XBRK;
495 uart_setreg(bas, SAB_DAFO, dafo);
498 case UART_IOCTL_IFLOW:
499 mode = uart_getreg(bas, SAB_MODE);
501 mode &= ~SAB_MODE_RTS;
502 mode |= SAB_MODE_FRTS;
504 mode |= SAB_MODE_RTS;
505 mode &= ~SAB_MODE_FRTS;
507 uart_setreg(bas, SAB_MODE, mode);
510 case UART_IOCTL_OFLOW:
511 mode = uart_getreg(bas, SAB_MODE);
513 mode &= ~SAB_MODE_FCTS;
515 mode |= SAB_MODE_FCTS;
516 uart_setreg(bas, SAB_MODE, mode);
523 mtx_unlock_spin(&sc->sc_hwmtx);
528 sab82532_bus_ipend(struct uart_softc *sc)
530 struct uart_bas *bas;
535 mtx_lock_spin(&sc->sc_hwmtx);
536 isr0 = uart_getreg(bas, SAB_ISR0);
537 isr1 = uart_getreg(bas, SAB_ISR1);
539 if (isr0 & SAB_ISR0_TIME) {
540 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
542 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RFRD);
545 mtx_unlock_spin(&sc->sc_hwmtx);
548 if (isr1 & SAB_ISR1_BRKT)
549 ipend |= UART_IPEND_BREAK;
550 if (isr0 & SAB_ISR0_RFO)
551 ipend |= UART_IPEND_OVERRUN;
552 if (isr0 & (SAB_ISR0_TCD|SAB_ISR0_RPF))
553 ipend |= UART_IPEND_RXREADY;
554 if ((isr0 & SAB_ISR0_CDSC) || (isr1 & SAB_ISR1_CSC))
555 ipend |= UART_IPEND_SIGCHG;
556 if (isr1 & SAB_ISR1_ALLS)
557 ipend |= UART_IPEND_TXIDLE;
563 sab82532_bus_param(struct uart_softc *sc, int baudrate, int databits,
564 int stopbits, int parity)
566 struct uart_bas *bas;
570 mtx_lock_spin(&sc->sc_hwmtx);
571 error = sab82532_param(bas, baudrate, databits, stopbits, parity);
572 mtx_unlock_spin(&sc->sc_hwmtx);
577 sab82532_bus_probe(struct uart_softc *sc)
584 error = sab82532_probe(&sc->sc_bas);
588 ch = sc->sc_bas.chan - 1 + 'A';
590 switch (uart_getreg(&sc->sc_bas, SAB_VSTR) & SAB_VSTR_VMASK) {
599 sc->sc_hwiflow = 0; /* CTS doesn't work with RFC:RFDF. */
607 snprintf(buf, sizeof(buf), "SAB 82532 %s, channel %c", vstr, ch);
608 device_set_desc_copy(sc->sc_dev, buf);
613 sab82532_bus_receive(struct uart_softc *sc)
615 struct uart_bas *bas;
620 mtx_lock_spin(&sc->sc_hwmtx);
621 if (uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE) {
622 rbcl = uart_getreg(bas, SAB_RBCL) & 31;
625 for (i = 0; i < rbcl; i += 2) {
626 if (uart_rx_full(sc)) {
627 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
630 xc = uart_getreg(bas, SAB_RFIFO);
631 s = uart_getreg(bas, SAB_RFIFO + 1);
632 if (s & SAB_RSTAT_FE)
633 xc |= UART_STAT_FRAMERR;
634 if (s & SAB_RSTAT_PE)
635 xc |= UART_STAT_PARERR;
640 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
642 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RMC);
644 mtx_unlock_spin(&sc->sc_hwmtx);
649 sab82532_bus_setsig(struct uart_softc *sc, int sig)
651 struct uart_bas *bas;
659 if (sig & SER_DDTR) {
660 SIGCHG(sig & SER_DTR, new, SER_DTR,
663 if (sig & SER_DRTS) {
664 SIGCHG(sig & SER_RTS, new, SER_RTS,
667 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
669 mtx_lock_spin(&sc->sc_hwmtx);
671 pvr = uart_getreg(bas, SAB_PVR);
675 pvr &= ~SAB_PVR_DTR_A;
677 pvr |= SAB_PVR_DTR_A;
681 pvr &= ~SAB_PVR_DTR_B;
683 pvr |= SAB_PVR_DTR_B;
686 uart_setreg(bas, SAB_PVR, pvr);
689 mode = uart_getreg(bas, SAB_MODE);
691 mode &= ~SAB_MODE_FRTS;
693 mode |= SAB_MODE_FRTS;
694 uart_setreg(bas, SAB_MODE, mode);
696 mtx_unlock_spin(&sc->sc_hwmtx);
701 sab82532_bus_transmit(struct uart_softc *sc)
703 struct uart_bas *bas;
707 mtx_lock_spin(&sc->sc_hwmtx);
708 while (!(uart_getreg(bas, SAB_STAR) & SAB_STAR_XFW))
710 for (i = 0; i < sc->sc_txdatasz; i++)
711 uart_setreg(bas, SAB_XFIFO + i, sc->sc_txbuf[i]);
713 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
715 uart_setreg(bas, SAB_CMDR, SAB_CMDR_XF);
717 mtx_unlock_spin(&sc->sc_hwmtx);