2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #ifdef HAVE_KERNEL_OPTION_HEADERS
37 #include "opt_device_polling.h"
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/sockio.h>
44 #include <sys/malloc.h>
45 #include <sys/kernel.h>
46 #include <sys/module.h>
47 #include <sys/socket.h>
48 #include <sys/sysctl.h>
51 #include <net/if_arp.h>
52 #include <net/ethernet.h>
53 #include <net/if_dl.h>
54 #include <net/if_media.h>
55 #include <net/if_types.h>
56 #include <net/if_vlan_var.h>
60 #include <vm/vm.h> /* for vtophys */
61 #include <vm/pmap.h> /* for vtophys */
62 #include <machine/bus.h>
63 #include <machine/resource.h>
67 #include <dev/mii/mii.h>
68 #include <dev/mii/miivar.h>
70 #include <dev/pci/pcireg.h>
71 #include <dev/pci/pcivar.h>
73 /* "controller miibus0" required. See GENERIC if you get errors here. */
74 #include "miibus_if.h"
76 #define STE_USEIOSPACE
78 #include <pci/if_stereg.h>
80 MODULE_DEPEND(ste, pci, 1, 1, 1);
81 MODULE_DEPEND(ste, ether, 1, 1, 1);
82 MODULE_DEPEND(ste, miibus, 1, 1, 1);
85 * Various supported device vendors/types and their names.
87 static struct ste_type ste_devs[] = {
88 { ST_VENDORID, ST_DEVICEID_ST201_1, "Sundance ST201 10/100BaseTX" },
89 { ST_VENDORID, ST_DEVICEID_ST201_2, "Sundance ST201 10/100BaseTX" },
90 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" },
94 static int ste_probe(device_t);
95 static int ste_attach(device_t);
96 static int ste_detach(device_t);
97 static void ste_init(void *);
98 static void ste_init_locked(struct ste_softc *);
99 static void ste_intr(void *);
100 static void ste_rxeoc(struct ste_softc *);
101 static void ste_rxeof(struct ste_softc *);
102 static void ste_txeoc(struct ste_softc *);
103 static void ste_txeof(struct ste_softc *);
104 static void ste_stats_update(void *);
105 static void ste_stop(struct ste_softc *);
106 static void ste_reset(struct ste_softc *);
107 static int ste_ioctl(struct ifnet *, u_long, caddr_t);
108 static int ste_encap(struct ste_softc *, struct ste_chain *, struct mbuf *);
109 static void ste_start(struct ifnet *);
110 static void ste_start_locked(struct ifnet *);
111 static void ste_watchdog(struct ifnet *);
112 static void ste_shutdown(device_t);
113 static int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *,
115 static int ste_ifmedia_upd(struct ifnet *);
116 static void ste_ifmedia_upd_locked(struct ifnet *);
117 static void ste_ifmedia_sts(struct ifnet *, struct ifmediareq *);
119 static void ste_mii_sync(struct ste_softc *);
120 static void ste_mii_send(struct ste_softc *, u_int32_t, int);
121 static int ste_mii_readreg(struct ste_softc *, struct ste_mii_frame *);
122 static int ste_mii_writereg(struct ste_softc *, struct ste_mii_frame *);
123 static int ste_miibus_readreg(device_t, int, int);
124 static int ste_miibus_writereg(device_t, int, int, int);
125 static void ste_miibus_statchg(device_t);
127 static int ste_eeprom_wait(struct ste_softc *);
128 static int ste_read_eeprom(struct ste_softc *, caddr_t, int, int, int);
129 static void ste_wait(struct ste_softc *);
130 static void ste_setmulti(struct ste_softc *);
131 static int ste_init_rx_list(struct ste_softc *);
132 static void ste_init_tx_list(struct ste_softc *);
134 #ifdef STE_USEIOSPACE
135 #define STE_RES SYS_RES_IOPORT
136 #define STE_RID STE_PCI_LOIO
138 #define STE_RES SYS_RES_MEMORY
139 #define STE_RID STE_PCI_LOMEM
142 static device_method_t ste_methods[] = {
143 /* Device interface */
144 DEVMETHOD(device_probe, ste_probe),
145 DEVMETHOD(device_attach, ste_attach),
146 DEVMETHOD(device_detach, ste_detach),
147 DEVMETHOD(device_shutdown, ste_shutdown),
150 DEVMETHOD(bus_print_child, bus_generic_print_child),
151 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
154 DEVMETHOD(miibus_readreg, ste_miibus_readreg),
155 DEVMETHOD(miibus_writereg, ste_miibus_writereg),
156 DEVMETHOD(miibus_statchg, ste_miibus_statchg),
161 static driver_t ste_driver = {
164 sizeof(struct ste_softc)
167 static devclass_t ste_devclass;
169 DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0);
170 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0);
172 SYSCTL_NODE(_hw, OID_AUTO, ste, CTLFLAG_RD, 0, "if_ste parameters");
174 static int ste_rxsyncs;
175 SYSCTL_INT(_hw_ste, OID_AUTO, rxsyncs, CTLFLAG_RW, &ste_rxsyncs, 0, "");
177 #define STE_SETBIT4(sc, reg, x) \
178 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
180 #define STE_CLRBIT4(sc, reg, x) \
181 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
183 #define STE_SETBIT2(sc, reg, x) \
184 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
186 #define STE_CLRBIT2(sc, reg, x) \
187 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
189 #define STE_SETBIT1(sc, reg, x) \
190 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
192 #define STE_CLRBIT1(sc, reg, x) \
193 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
196 #define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x)
197 #define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x)
200 * Sync the PHYs by setting data bit and strobing the clock 32 times.
204 struct ste_softc *sc;
208 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA);
210 for (i = 0; i < 32; i++) {
211 MII_SET(STE_PHYCTL_MCLK);
213 MII_CLR(STE_PHYCTL_MCLK);
221 * Clock a series of bits through the MII.
224 ste_mii_send(sc, bits, cnt)
225 struct ste_softc *sc;
231 MII_CLR(STE_PHYCTL_MCLK);
233 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
235 MII_SET(STE_PHYCTL_MDATA);
237 MII_CLR(STE_PHYCTL_MDATA);
240 MII_CLR(STE_PHYCTL_MCLK);
242 MII_SET(STE_PHYCTL_MCLK);
247 * Read an PHY register through the MII.
250 ste_mii_readreg(sc, frame)
251 struct ste_softc *sc;
252 struct ste_mii_frame *frame;
258 * Set up frame for RX.
260 frame->mii_stdelim = STE_MII_STARTDELIM;
261 frame->mii_opcode = STE_MII_READOP;
262 frame->mii_turnaround = 0;
265 CSR_WRITE_2(sc, STE_PHYCTL, 0);
269 MII_SET(STE_PHYCTL_MDIR);
274 * Send command/address info.
276 ste_mii_send(sc, frame->mii_stdelim, 2);
277 ste_mii_send(sc, frame->mii_opcode, 2);
278 ste_mii_send(sc, frame->mii_phyaddr, 5);
279 ste_mii_send(sc, frame->mii_regaddr, 5);
282 MII_CLR(STE_PHYCTL_MDIR);
285 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA));
287 MII_SET(STE_PHYCTL_MCLK);
291 MII_CLR(STE_PHYCTL_MCLK);
293 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA;
294 MII_SET(STE_PHYCTL_MCLK);
298 * Now try reading data bits. If the ack failed, we still
299 * need to clock through 16 cycles to keep the PHY(s) in sync.
302 for(i = 0; i < 16; i++) {
303 MII_CLR(STE_PHYCTL_MCLK);
305 MII_SET(STE_PHYCTL_MCLK);
311 for (i = 0x8000; i; i >>= 1) {
312 MII_CLR(STE_PHYCTL_MCLK);
315 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA)
316 frame->mii_data |= i;
319 MII_SET(STE_PHYCTL_MCLK);
325 MII_CLR(STE_PHYCTL_MCLK);
327 MII_SET(STE_PHYCTL_MCLK);
336 * Write to a PHY register through the MII.
339 ste_mii_writereg(sc, frame)
340 struct ste_softc *sc;
341 struct ste_mii_frame *frame;
346 * Set up frame for TX.
349 frame->mii_stdelim = STE_MII_STARTDELIM;
350 frame->mii_opcode = STE_MII_WRITEOP;
351 frame->mii_turnaround = STE_MII_TURNAROUND;
354 * Turn on data output.
356 MII_SET(STE_PHYCTL_MDIR);
360 ste_mii_send(sc, frame->mii_stdelim, 2);
361 ste_mii_send(sc, frame->mii_opcode, 2);
362 ste_mii_send(sc, frame->mii_phyaddr, 5);
363 ste_mii_send(sc, frame->mii_regaddr, 5);
364 ste_mii_send(sc, frame->mii_turnaround, 2);
365 ste_mii_send(sc, frame->mii_data, 16);
368 MII_SET(STE_PHYCTL_MCLK);
370 MII_CLR(STE_PHYCTL_MCLK);
376 MII_CLR(STE_PHYCTL_MDIR);
382 ste_miibus_readreg(dev, phy, reg)
386 struct ste_softc *sc;
387 struct ste_mii_frame frame;
389 sc = device_get_softc(dev);
391 if ( sc->ste_one_phy && phy != 0 )
394 bzero((char *)&frame, sizeof(frame));
396 frame.mii_phyaddr = phy;
397 frame.mii_regaddr = reg;
398 ste_mii_readreg(sc, &frame);
400 return(frame.mii_data);
404 ste_miibus_writereg(dev, phy, reg, data)
408 struct ste_softc *sc;
409 struct ste_mii_frame frame;
411 sc = device_get_softc(dev);
412 bzero((char *)&frame, sizeof(frame));
414 frame.mii_phyaddr = phy;
415 frame.mii_regaddr = reg;
416 frame.mii_data = data;
418 ste_mii_writereg(sc, &frame);
424 ste_miibus_statchg(dev)
427 struct ste_softc *sc;
428 struct mii_data *mii;
430 sc = device_get_softc(dev);
432 mii = device_get_softc(sc->ste_miibus);
434 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
435 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX);
437 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX);
447 struct ste_softc *sc;
451 ste_ifmedia_upd_locked(ifp);
458 ste_ifmedia_upd_locked(ifp)
461 struct ste_softc *sc;
462 struct mii_data *mii;
466 mii = device_get_softc(sc->ste_miibus);
468 if (mii->mii_instance) {
469 struct mii_softc *miisc;
470 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
471 mii_phy_reset(miisc);
477 ste_ifmedia_sts(ifp, ifmr)
479 struct ifmediareq *ifmr;
481 struct ste_softc *sc;
482 struct mii_data *mii;
485 mii = device_get_softc(sc->ste_miibus);
489 ifmr->ifm_active = mii->mii_media_active;
490 ifmr->ifm_status = mii->mii_media_status;
498 struct ste_softc *sc;
502 for (i = 0; i < STE_TIMEOUT; i++) {
503 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG))
507 if (i == STE_TIMEOUT)
508 if_printf(sc->ste_ifp, "command never completed!\n");
514 * The EEPROM is slow: give it time to come ready after issuing
519 struct ste_softc *sc;
525 for (i = 0; i < 100; i++) {
526 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY)
533 if_printf(sc->ste_ifp, "eeprom failed to come ready\n");
541 * Read a sequence of words from the EEPROM. Note that ethernet address
542 * data is stored in the EEPROM in network byte order.
545 ste_read_eeprom(sc, dest, off, cnt, swap)
546 struct ste_softc *sc;
553 u_int16_t word = 0, *ptr;
555 if (ste_eeprom_wait(sc))
558 for (i = 0; i < cnt; i++) {
559 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i));
560 err = ste_eeprom_wait(sc);
563 word = CSR_READ_2(sc, STE_EEPROM_DATA);
564 ptr = (u_int16_t *)(dest + (i * 2));
576 struct ste_softc *sc;
580 u_int32_t hashes[2] = { 0, 0 };
581 struct ifmultiaddr *ifma;
584 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
585 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
586 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
590 /* first, zot all the existing hash bits */
591 CSR_WRITE_2(sc, STE_MAR0, 0);
592 CSR_WRITE_2(sc, STE_MAR1, 0);
593 CSR_WRITE_2(sc, STE_MAR2, 0);
594 CSR_WRITE_2(sc, STE_MAR3, 0);
596 /* now program new ones */
598 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
599 if (ifma->ifma_addr->sa_family != AF_LINK)
601 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
602 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3F;
604 hashes[0] |= (1 << h);
606 hashes[1] |= (1 << (h - 32));
610 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);
611 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);
612 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);
613 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);
614 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
615 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
620 #ifdef DEVICE_POLLING
621 static poll_handler_t ste_poll, ste_poll_locked;
624 ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
626 struct ste_softc *sc = ifp->if_softc;
629 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
630 ste_poll_locked(ifp, cmd, count);
635 ste_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
637 struct ste_softc *sc = ifp->if_softc;
641 sc->rxcycles = count;
642 if (cmd == POLL_AND_CHECK_STATUS)
646 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
647 ste_start_locked(ifp);
649 if (cmd == POLL_AND_CHECK_STATUS) {
652 status = CSR_READ_2(sc, STE_ISR_ACK);
654 if (status & STE_ISR_TX_DONE)
657 if (status & STE_ISR_STATS_OFLOW) {
658 callout_stop(&sc->ste_stat_callout);
659 ste_stats_update(sc);
662 if (status & STE_ISR_LINKEVENT)
663 mii_pollstat(device_get_softc(sc->ste_miibus));
665 if (status & STE_ISR_HOSTERR) {
671 #endif /* DEVICE_POLLING */
677 struct ste_softc *sc;
685 #ifdef DEVICE_POLLING
686 if (ifp->if_capenable & IFCAP_POLLING) {
692 /* See if this is really our interrupt. */
693 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) {
699 status = CSR_READ_2(sc, STE_ISR_ACK);
701 if (!(status & STE_INTRS))
704 if (status & STE_ISR_RX_DMADONE) {
709 if (status & STE_ISR_TX_DMADONE)
712 if (status & STE_ISR_TX_DONE)
715 if (status & STE_ISR_STATS_OFLOW) {
716 callout_stop(&sc->ste_stat_callout);
717 ste_stats_update(sc);
720 if (status & STE_ISR_LINKEVENT)
721 mii_pollstat(device_get_softc(sc->ste_miibus));
724 if (status & STE_ISR_HOSTERR) {
730 /* Re-enable interrupts */
731 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
733 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
734 ste_start_locked(ifp);
742 ste_rxeoc(struct ste_softc *sc)
744 struct ste_chain_onefrag *cur_rx;
748 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) {
749 cur_rx = sc->ste_cdata.ste_rx_head;
751 cur_rx = cur_rx->ste_next;
752 /* If the ring is empty, just return. */
753 if (cur_rx == sc->ste_cdata.ste_rx_head)
755 } while (cur_rx->ste_ptr->ste_status == 0);
756 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) {
757 /* We've fallen behind the chip: catch it. */
758 sc->ste_cdata.ste_rx_head = cur_rx;
765 * A frame has been uploaded: pass the resulting mbuf chain up to
766 * the higher level protocols.
770 struct ste_softc *sc;
774 struct ste_chain_onefrag *cur_rx;
775 int total_len = 0, count=0;
782 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status)
783 & STE_RXSTAT_DMADONE) {
784 #ifdef DEVICE_POLLING
785 if (ifp->if_capenable & IFCAP_POLLING) {
786 if (sc->rxcycles <= 0)
791 if ((STE_RX_LIST_CNT - count) < 3) {
795 cur_rx = sc->ste_cdata.ste_rx_head;
796 sc->ste_cdata.ste_rx_head = cur_rx->ste_next;
799 * If an error occurs, update stats, clear the
800 * status word and leave the mbuf cluster in place:
801 * it should simply get re-used next time this descriptor
802 * comes up in the ring.
804 if (rxstat & STE_RXSTAT_FRAME_ERR) {
806 cur_rx->ste_ptr->ste_status = 0;
811 * If there error bit was not set, the upload complete
812 * bit should be set which means we have a valid packet.
813 * If not, something truly strange has happened.
815 if (!(rxstat & STE_RXSTAT_DMADONE)) {
817 "bad receive status -- packet dropped\n");
819 cur_rx->ste_ptr->ste_status = 0;
823 /* No errors; receive the packet. */
824 m = cur_rx->ste_mbuf;
825 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN;
828 * Try to conjure up a new mbuf cluster. If that
829 * fails, it means we have an out of memory condition and
830 * should leave the buffer in place and continue. This will
831 * result in a lost packet, but there's little else we
832 * can do in this situation.
834 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) {
836 cur_rx->ste_ptr->ste_status = 0;
840 m->m_pkthdr.rcvif = ifp;
841 m->m_pkthdr.len = m->m_len = total_len;
845 (*ifp->if_input)(ifp, m);
848 cur_rx->ste_ptr->ste_status = 0;
857 struct ste_softc *sc;
864 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) &
865 STE_TXSTATUS_TXDONE) {
866 if (txstat & STE_TXSTATUS_UNDERRUN ||
867 txstat & STE_TXSTATUS_EXCESSCOLLS ||
868 txstat & STE_TXSTATUS_RECLAIMERR) {
870 if_printf(ifp, "transmission error: %x\n", txstat);
875 if (txstat & STE_TXSTATUS_UNDERRUN &&
876 sc->ste_tx_thresh < STE_PACKET_SIZE) {
877 sc->ste_tx_thresh += STE_MIN_FRAMELEN;
878 if_printf(ifp, "tx underrun, increasing tx"
879 " start threshold to %d bytes\n",
882 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
883 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH,
884 (STE_PACKET_SIZE >> 4));
887 CSR_WRITE_2(sc, STE_TX_STATUS, txstat);
895 struct ste_softc *sc;
897 struct ste_chain *cur_tx;
903 idx = sc->ste_cdata.ste_tx_cons;
904 while(idx != sc->ste_cdata.ste_tx_prod) {
905 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
907 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE))
910 m_freem(cur_tx->ste_mbuf);
911 cur_tx->ste_mbuf = NULL;
912 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
915 STE_INC(idx, STE_TX_LIST_CNT);
918 sc->ste_cdata.ste_tx_cons = idx;
919 if (idx == sc->ste_cdata.ste_tx_prod)
924 ste_stats_update(xsc)
927 struct ste_softc *sc;
929 struct mii_data *mii;
935 mii = device_get_softc(sc->ste_miibus);
937 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS)
938 + CSR_READ_1(sc, STE_MULTI_COLLS)
939 + CSR_READ_1(sc, STE_SINGLE_COLLS);
943 if (mii->mii_media_status & IFM_ACTIVE &&
944 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
947 * we don't get a call-back on re-init so do it
948 * otherwise we get stuck in the wrong link state
950 ste_miibus_statchg(sc->ste_dev);
951 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
952 ste_start_locked(ifp);
956 callout_reset(&sc->ste_stat_callout, hz, ste_stats_update, sc);
963 * Probe for a Sundance ST201 chip. Check the PCI vendor and device
964 * IDs against our list and return a device name if we find a match.
974 while(t->ste_name != NULL) {
975 if ((pci_get_vendor(dev) == t->ste_vid) &&
976 (pci_get_device(dev) == t->ste_did)) {
977 device_set_desc(dev, t->ste_name);
978 return (BUS_PROBE_DEFAULT);
987 * Attach the interface. Allocate softc structures, do ifmedia
988 * setup and ethernet/BPF attach.
994 struct ste_softc *sc;
999 sc = device_get_softc(dev);
1003 * Only use one PHY since this chip reports multiple
1004 * Note on the DFE-550 the PHY is at 1 on the DFE-580
1005 * it is at 0 & 1. It is rev 0x12.
1007 if (pci_get_vendor(dev) == DL_VENDORID &&
1008 pci_get_device(dev) == DL_DEVICEID_DL10050 &&
1009 pci_get_revid(dev) == 0x12 )
1010 sc->ste_one_phy = 1;
1012 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1015 * Map control/status registers.
1017 pci_enable_busmaster(dev);
1020 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE);
1022 if (sc->ste_res == NULL) {
1023 device_printf(dev, "couldn't map ports/memory\n");
1028 sc->ste_btag = rman_get_bustag(sc->ste_res);
1029 sc->ste_bhandle = rman_get_bushandle(sc->ste_res);
1031 /* Allocate interrupt */
1033 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1034 RF_SHAREABLE | RF_ACTIVE);
1036 if (sc->ste_irq == NULL) {
1037 device_printf(dev, "couldn't map interrupt\n");
1042 callout_init_mtx(&sc->ste_stat_callout, &sc->ste_mtx, 0);
1044 /* Reset the adapter. */
1048 * Get station address from the EEPROM.
1050 if (ste_read_eeprom(sc, eaddr,
1051 STE_EEADDR_NODE0, 3, 0)) {
1052 device_printf(dev, "failed to read station address\n");
1057 /* Allocate the descriptor queues. */
1058 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF,
1059 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1061 if (sc->ste_ldata == NULL) {
1062 device_printf(dev, "no memory for list buffers!\n");
1067 bzero(sc->ste_ldata, sizeof(struct ste_list_data));
1069 ifp = sc->ste_ifp = if_alloc(IFT_ETHER);
1071 device_printf(dev, "can not if_alloc()\n");
1077 if (mii_phy_probe(dev, &sc->ste_miibus,
1078 ste_ifmedia_upd, ste_ifmedia_sts)) {
1079 device_printf(dev, "MII without any phy!\n");
1085 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1086 ifp->if_mtu = ETHERMTU;
1087 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1088 ifp->if_ioctl = ste_ioctl;
1089 ifp->if_start = ste_start;
1090 ifp->if_watchdog = ste_watchdog;
1091 ifp->if_init = ste_init;
1092 IFQ_SET_MAXLEN(&ifp->if_snd, STE_TX_LIST_CNT - 1);
1093 ifp->if_snd.ifq_drv_maxlen = STE_TX_LIST_CNT - 1;
1094 IFQ_SET_READY(&ifp->if_snd);
1096 sc->ste_tx_thresh = STE_TXSTART_THRESH;
1099 * Call MI attach routine.
1101 ether_ifattach(ifp, eaddr);
1104 * Tell the upper layer(s) we support long frames.
1106 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1107 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1108 ifp->if_capenable = ifp->if_capabilities;
1109 #ifdef DEVICE_POLLING
1110 ifp->if_capabilities |= IFCAP_POLLING;
1113 /* Hook interrupt last to avoid having to lock softc */
1114 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET | INTR_MPSAFE,
1115 ste_intr, sc, &sc->ste_intrhand);
1118 device_printf(dev, "couldn't set up irq\n");
1119 ether_ifdetach(ifp);
1131 * Shutdown hardware and free up resources. This can be called any
1132 * time after the mutex has been initialized. It is called in both
1133 * the error case in attach and the normal detach case so it needs
1134 * to be careful about only freeing resources that have actually been
1141 struct ste_softc *sc;
1144 sc = device_get_softc(dev);
1145 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized"));
1148 #ifdef DEVICE_POLLING
1149 if (ifp->if_capenable & IFCAP_POLLING)
1150 ether_poll_deregister(ifp);
1153 /* These should only be active if attach succeeded */
1154 if (device_is_attached(dev)) {
1158 callout_drain(&sc->ste_stat_callout);
1159 ether_ifdetach(ifp);
1164 device_delete_child(dev, sc->ste_miibus);
1165 bus_generic_detach(dev);
1167 if (sc->ste_intrhand)
1168 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1170 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1172 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1174 if (sc->ste_ldata) {
1175 contigfree(sc->ste_ldata, sizeof(struct ste_list_data),
1179 mtx_destroy(&sc->ste_mtx);
1185 ste_newbuf(sc, c, m)
1186 struct ste_softc *sc;
1187 struct ste_chain_onefrag *c;
1190 struct mbuf *m_new = NULL;
1193 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1196 MCLGET(m_new, M_DONTWAIT);
1197 if (!(m_new->m_flags & M_EXT)) {
1201 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1204 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1205 m_new->m_data = m_new->m_ext.ext_buf;
1208 m_adj(m_new, ETHER_ALIGN);
1210 c->ste_mbuf = m_new;
1211 c->ste_ptr->ste_status = 0;
1212 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t));
1213 c->ste_ptr->ste_frag.ste_len = (1536 + ETHER_VLAN_ENCAP_LEN) | STE_FRAG_LAST;
1219 ste_init_rx_list(sc)
1220 struct ste_softc *sc;
1222 struct ste_chain_data *cd;
1223 struct ste_list_data *ld;
1226 cd = &sc->ste_cdata;
1229 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1230 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i];
1231 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS)
1233 if (i == (STE_RX_LIST_CNT - 1)) {
1234 cd->ste_rx_chain[i].ste_next =
1235 &cd->ste_rx_chain[0];
1236 ld->ste_rx_list[i].ste_next =
1237 vtophys(&ld->ste_rx_list[0]);
1239 cd->ste_rx_chain[i].ste_next =
1240 &cd->ste_rx_chain[i + 1];
1241 ld->ste_rx_list[i].ste_next =
1242 vtophys(&ld->ste_rx_list[i + 1]);
1244 ld->ste_rx_list[i].ste_status = 0;
1247 cd->ste_rx_head = &cd->ste_rx_chain[0];
1253 ste_init_tx_list(sc)
1254 struct ste_softc *sc;
1256 struct ste_chain_data *cd;
1257 struct ste_list_data *ld;
1260 cd = &sc->ste_cdata;
1262 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1263 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i];
1264 cd->ste_tx_chain[i].ste_ptr->ste_next = 0;
1265 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0;
1266 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]);
1267 if (i == (STE_TX_LIST_CNT - 1))
1268 cd->ste_tx_chain[i].ste_next =
1269 &cd->ste_tx_chain[0];
1271 cd->ste_tx_chain[i].ste_next =
1272 &cd->ste_tx_chain[i + 1];
1275 cd->ste_tx_prod = 0;
1276 cd->ste_tx_cons = 0;
1285 struct ste_softc *sc;
1289 ste_init_locked(sc);
1295 struct ste_softc *sc;
1300 STE_LOCK_ASSERT(sc);
1305 /* Init our MAC address */
1306 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
1307 CSR_WRITE_2(sc, STE_PAR0 + i,
1308 ((IFP2ENADDR(sc->ste_ifp)[i] & 0xff) |
1309 IFP2ENADDR(sc->ste_ifp)[i + 1] << 8));
1313 if (ste_init_rx_list(sc) == ENOBUFS) {
1315 "initialization failed: no memory for RX buffers\n");
1320 /* Set RX polling interval */
1321 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64);
1323 /* Init TX descriptors */
1324 ste_init_tx_list(sc);
1326 /* Set the TX freethresh value */
1327 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8);
1329 /* Set the TX start threshold for best performance. */
1330 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
1332 /* Set the TX reclaim threshold. */
1333 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4));
1335 /* Set up the RX filter. */
1336 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST);
1338 /* If we want promiscuous mode, set the allframes bit. */
1339 if (ifp->if_flags & IFF_PROMISC) {
1340 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC);
1342 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC);
1345 /* Set capture broadcast bit to accept broadcast frames. */
1346 if (ifp->if_flags & IFF_BROADCAST) {
1347 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST);
1349 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST);
1354 /* Load the address of the RX list. */
1355 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1357 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR,
1358 vtophys(&sc->ste_ldata->ste_rx_list[0]));
1359 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1360 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1362 /* Set TX polling interval (defer until we TX first packet */
1363 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
1365 /* Load address of the TX list */
1366 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1368 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0);
1369 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1370 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1372 sc->ste_tx_prev = NULL;
1374 /* Enable receiver and transmitter */
1375 CSR_WRITE_2(sc, STE_MACCTL0, 0);
1376 CSR_WRITE_2(sc, STE_MACCTL1, 0);
1377 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE);
1378 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE);
1380 /* Enable stats counters. */
1381 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE);
1383 CSR_WRITE_2(sc, STE_ISR, 0xFFFF);
1384 #ifdef DEVICE_POLLING
1385 /* Disable interrupts if we are polling. */
1386 if (ifp->if_capenable & IFCAP_POLLING)
1387 CSR_WRITE_2(sc, STE_IMR, 0);
1390 /* Enable interrupts. */
1391 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
1393 /* Accept VLAN length packets */
1394 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN);
1396 ste_ifmedia_upd_locked(ifp);
1398 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1399 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1401 callout_reset(&sc->ste_stat_callout, hz, ste_stats_update, sc);
1408 struct ste_softc *sc;
1413 STE_LOCK_ASSERT(sc);
1416 callout_stop(&sc->ste_stat_callout);
1417 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE);
1419 CSR_WRITE_2(sc, STE_IMR, 0);
1420 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE);
1421 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE);
1422 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE);
1423 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1424 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1427 * Try really hard to stop the RX engine or under heavy RX
1428 * data chip will write into de-allocated memory.
1434 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1435 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) {
1436 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf);
1437 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL;
1441 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1442 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) {
1443 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf);
1444 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL;
1448 bzero(sc->ste_ldata, sizeof(struct ste_list_data));
1455 struct ste_softc *sc;
1459 STE_SETBIT4(sc, STE_ASICCTL,
1460 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET|
1461 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET|
1462 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET|
1463 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET|
1464 STE_ASICCTL_EXTRESET_RESET);
1468 for (i = 0; i < STE_TIMEOUT; i++) {
1469 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))
1473 if (i == STE_TIMEOUT)
1474 if_printf(sc->ste_ifp, "global reset never completed\n");
1480 ste_ioctl(ifp, command, data)
1485 struct ste_softc *sc;
1487 struct mii_data *mii;
1491 ifr = (struct ifreq *)data;
1496 if (ifp->if_flags & IFF_UP) {
1497 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1498 ifp->if_flags & IFF_PROMISC &&
1499 !(sc->ste_if_flags & IFF_PROMISC)) {
1500 STE_SETBIT1(sc, STE_RX_MODE,
1501 STE_RXMODE_PROMISC);
1502 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1503 !(ifp->if_flags & IFF_PROMISC) &&
1504 sc->ste_if_flags & IFF_PROMISC) {
1505 STE_CLRBIT1(sc, STE_RX_MODE,
1506 STE_RXMODE_PROMISC);
1508 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1509 (ifp->if_flags ^ sc->ste_if_flags) & IFF_ALLMULTI)
1511 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1512 sc->ste_tx_thresh = STE_TXSTART_THRESH;
1513 ste_init_locked(sc);
1516 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1519 sc->ste_if_flags = ifp->if_flags;
1532 mii = device_get_softc(sc->ste_miibus);
1533 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1536 #ifdef DEVICE_POLLING
1537 if (ifr->ifr_reqcap & IFCAP_POLLING &&
1538 !(ifp->if_capenable & IFCAP_POLLING)) {
1539 error = ether_poll_register(ste_poll, ifp);
1543 /* Disable interrupts */
1544 CSR_WRITE_2(sc, STE_IMR, 0);
1545 ifp->if_capenable |= IFCAP_POLLING;
1550 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
1551 ifp->if_capenable & IFCAP_POLLING) {
1552 error = ether_poll_deregister(ifp);
1553 /* Enable interrupts. */
1555 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
1556 ifp->if_capenable &= ~IFCAP_POLLING;
1560 #endif /* DEVICE_POLLING */
1563 error = ether_ioctl(ifp, command, data);
1571 ste_encap(sc, c, m_head)
1572 struct ste_softc *sc;
1573 struct ste_chain *c;
1574 struct mbuf *m_head;
1577 struct ste_frag *f = NULL;
1585 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1586 if (m->m_len != 0) {
1587 if (frag == STE_MAXFRAGS)
1589 f = &d->ste_frags[frag];
1590 f->ste_addr = vtophys(mtod(m, vm_offset_t));
1591 f->ste_len = m->m_len;
1600 * We ran out of segments. We have to recopy this
1601 * mbuf chain first. Bail out if we can't get the
1604 mn = m_defrag(m_head, M_DONTWAIT);
1613 c->ste_mbuf = m_head;
1614 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST;
1624 struct ste_softc *sc;
1628 ste_start_locked(ifp);
1633 ste_start_locked(ifp)
1636 struct ste_softc *sc;
1637 struct mbuf *m_head = NULL;
1638 struct ste_chain *cur_tx;
1642 STE_LOCK_ASSERT(sc);
1647 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
1650 idx = sc->ste_cdata.ste_tx_prod;
1652 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) {
1654 * We cannot re-use the last (free) descriptor;
1655 * the chip may not have read its ste_next yet.
1657 if (STE_NEXT(idx, STE_TX_LIST_CNT) ==
1658 sc->ste_cdata.ste_tx_cons) {
1659 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1663 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1667 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
1669 if (ste_encap(sc, cur_tx, m_head) != 0)
1672 cur_tx->ste_ptr->ste_next = 0;
1674 if (sc->ste_tx_prev == NULL) {
1675 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1;
1676 /* Load address of the TX list */
1677 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1680 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR,
1681 vtophys(&sc->ste_ldata->ste_tx_list[0]));
1683 /* Set TX polling interval to start TX engine */
1684 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64);
1686 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1689 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1;
1690 sc->ste_tx_prev->ste_ptr->ste_next
1694 sc->ste_tx_prev = cur_tx;
1697 * If there's a BPF listener, bounce a copy of this frame
1700 BPF_MTAP(ifp, cur_tx->ste_mbuf);
1702 STE_INC(idx, STE_TX_LIST_CNT);
1705 sc->ste_cdata.ste_tx_prod = idx;
1714 struct ste_softc *sc;
1720 if_printf(ifp, "watchdog timeout\n");
1727 ste_init_locked(sc);
1729 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1730 ste_start_locked(ifp);
1740 struct ste_softc *sc;
1742 sc = device_get_softc(dev);