1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sc8280xp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on SC8280xp
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
13 Qualcomm global clock control module provides the clocks, resets and
14 power domains on SC8280xp.
16 See also:: include/dt-bindings/clock/qcom,gcc-sc8280xp.h
20 const: qcom,gcc-sc8280xp
24 - description: XO reference clock
25 - description: Sleep clock
26 - description: UFS memory first RX symbol clock
27 - description: UFS memory second RX symbol clock
28 - description: UFS memory first TX symbol clock
29 - description: UFS card first RX symbol clock
30 - description: UFS card second RX symbol clock
31 - description: UFS card first TX symbol clock
32 - description: Primary USB SuperSpeed pipe clock
33 - description: USB4 PHY pipegmux clock source
34 - description: USB4 PHY DP gmux clock source
35 - description: USB4 PHY sys pipegmux clock source
36 - description: USB4 PHY PCIe pipe clock
37 - description: USB4 PHY router max pipe clock
38 - description: Primary USB4 RX0 clock
39 - description: Primary USB4 RX1 clock
40 - description: Secondary USB SuperSpeed pipe clock
41 - description: Second USB4 PHY pipegmux clock source
42 - description: Second USB4 PHY DP gmux clock source
43 - description: Second USB4 PHY sys pipegmux clock source
44 - description: Second USB4 PHY PCIe pipe clock
45 - description: Second USB4 PHY router max pipe clock
46 - description: Secondary USB4 RX0 clock
47 - description: Secondary USB4 RX1 clock
48 - description: Multiport USB first SuperSpeed pipe clock
49 - description: Multiport USB second SuperSpeed pipe clock
50 - description: PCIe 2a pipe clock
51 - description: PCIe 2b pipe clock
52 - description: PCIe 3a pipe clock
53 - description: PCIe 3b pipe clock
54 - description: PCIe 4 pipe clock
55 - description: First EMAC controller reference clock
56 - description: Second EMAC controller reference clock
66 - $ref: qcom,gcc.yaml#
68 unevaluatedProperties: false
72 #include <dt-bindings/clock/qcom,rpmh.h>
73 clock-controller@100000 {
74 compatible = "qcom,gcc-sc8280xp";
75 reg = <0x00100000 0x1f0000>;
76 clocks = <&rpmhcc RPMH_CXO_CLK>,
78 <&ufs_phy_rx_symbol_0_clk>,
79 <&ufs_phy_rx_symbol_1_clk>,
80 <&ufs_phy_tx_symbol_0_clk>,
81 <&ufs_card_rx_symbol_0_clk>,
82 <&ufs_card_rx_symbol_1_clk>,
83 <&ufs_card_tx_symbol_0_clk>,
85 <&gcc_usb4_phy_pipegmux_clk_src>,
86 <&gcc_usb4_phy_dp_gmux_clk_src>,
87 <&gcc_usb4_phy_sys_pipegmux_clk_src>,
88 <&usb4_phy_gcc_usb4_pcie_pipe_clk>,
89 <&usb4_phy_gcc_usb4rtr_max_pipe_clk>,
90 <&qusb4phy_gcc_usb4_rx0_clk>,
91 <&qusb4phy_gcc_usb4_rx1_clk>,
93 <&gcc_usb4_1_phy_pipegmux_clk_src>,
94 <&gcc_usb4_1_phy_dp_gmux_clk_src>,
95 <&gcc_usb4_1_phy_sys_pipegmux_clk_src>,
96 <&usb4_1_phy_gcc_usb4_pcie_pipe_clk>,
97 <&usb4_1_phy_gcc_usb4rtr_max_pipe_clk>,
98 <&qusb4phy_1_gcc_usb4_rx0_clk>,
99 <&qusb4phy_1_gcc_usb4_rx1_clk>,
112 #power-domain-cells = <1>;