Bindings/clock/qcom,gpucc-sm8350.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/clock/qcom,gpucc-sm8350.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Graphics Clock & Reset Controller on SM8350
   8
   9 maintainers:
  10   - Robert Foss <robert.foss@linaro.org>
  11
  12 description: |
  13   Qualcomm graphics clock control module provides the clocks, resets and power
  14   domains on Qualcomm SoCs.
  15
  16   See also:: include/dt-bindings/clock/qcom,gpucc-sm8350.h
  17
  18 properties:
  19   compatible:
  20     enum:
  21       - qcom,sm8350-gpucc
  22
  23   clocks:
  24     items:
  25       - description: Board XO source
  26       - description: GPLL0 main branch source
  27       - description: GPLL0 div branch source
  28
  29   '#clock-cells':
  30     const: 1
  31
  32   '#reset-cells':
  33     const: 1
  34
  35   '#power-domain-cells':
  36     const: 1
  37
  38   reg:
  39     maxItems: 1
  40
  41 required:
  42   - compatible
  43   - reg
  44   - clocks
  45   - '#clock-cells'
  46   - '#reset-cells'
  47   - '#power-domain-cells'
  48
  49 additionalProperties: false
  50
  51 examples:
  52   - |
  53     #include <dt-bindings/clock/qcom,gcc-sm8350.h>
  54     #include <dt-bindings/clock/qcom,rpmh.h>
  55
  56     soc {
  57         #address-cells = <2>;
  58         #size-cells = <2>;
  59
  60         clock-controller@3d90000 {
  61             compatible = "qcom,sm8350-gpucc";
  62             reg = <0 0x03d90000 0 0x9000>;
  63             clocks = <&rpmhcc RPMH_CXO_CLK>,
  64                      <&gcc GCC_GPU_GPLL0_CLK_SRC>,
  65                      <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
  66             #clock-cells = <1>;
  67             #reset-cells = <1>;
  68             #power-domain-cells = <1>;
  69         };
  70     };
  71 ...