1 # SPDX-License-Identifier: GPL-2.0-only
4 $id: http://devicetree.org/schemas/clock/qcom,sc7180-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller Binding for SC7180
10 - Taniya Das <tdas@codeaurora.org>
13 Qualcomm display clock control module which supports the clocks, resets and
14 power domains on SC7180.
16 See also dt-bindings/clock/qcom,dispcc-sc7180.h.
20 const: qcom,sc7180-dispcc
24 - description: Board XO source
25 - description: GPLL0 source from GCC
26 - description: Byte clock from DSI PHY
27 - description: Pixel clock from DSI PHY
28 - description: Link clock from DP PHY
29 - description: VCO DIV clock from DP PHY
34 - const: gcc_disp_gpll0_clk_src
35 - const: dsi0_phy_pll_out_byteclk
36 - const: dsi0_phy_pll_out_dsiclk
37 - const: dp_phy_pll_link_clk
38 - const: dp_phy_pll_vco_div_clk
46 '#power-domain-cells':
59 - '#power-domain-cells'
63 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
64 #include <dt-bindings/clock/qcom,rpmh.h>
65 clock-controller@af00000 {
66 compatible = "qcom,sc7180-dispcc";
67 reg = <0 0x0af00000 0 0x200000>;
68 clocks = <&rpmhcc RPMH_CXO_CLK>,
69 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
74 clock-names = "bi_tcxo",
75 "gcc_disp_gpll0_clk_src",
76 "dsi0_phy_pll_out_byteclk",
77 "dsi0_phy_pll_out_dsiclk",
78 "dp_phy_pll_link_clk",
79 "dp_phy_pll_vco_div_clk";
82 #power-domain-cells = <1>;