Bindings/display/msm/gpu.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4
   5 $id: "http://devicetree.org/schemas/display/msm/gpu.yaml#"
   6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
   7
   8 title: Devicetree bindings for the Adreno or Snapdragon GPUs
   9
  10 maintainers:
  11   - Rob Clark <robdclark@gmail.com>
  12
  13 properties:
  14   compatible:
  15     oneOf:
  16       - description: |
  17           The driver is parsing the compat string for Adreno to
  18           figure out the gpu-id and patch level.
  19         items:
  20           - pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$'
  21           - const: qcom,adreno
  22       - description: |
  23           The driver is parsing the compat string for Imageon to
  24           figure out the gpu-id and patch level.
  25         items:
  26           - pattern: '^amd,imageon-200\.[0-1]$'
  27           - const: amd,imageon
  28
  29   clocks: true
  30
  31   clock-names: true
  32
  33   reg:
  34     minItems: 1
  35     maxItems: 3
  36
  37   reg-names:
  38     minItems: 1
  39     items:
  40       - const: kgsl_3d0_reg_memory
  41       - const: cx_mem
  42       - const: cx_dbgc
  43
  44   interrupts:
  45     maxItems: 1
  46
  47   interrupt-names:
  48     maxItems: 1
  49
  50   interconnects:
  51     minItems: 1
  52     maxItems: 2
  53
  54   interconnect-names:
  55     minItems: 1
  56     items:
  57       - const: gfx-mem
  58       - const: ocmem
  59
  60   iommus:
  61     maxItems: 1
  62
  63   sram:
  64     $ref: /schemas/types.yaml#/definitions/phandle-array
  65     minItems: 1
  66     maxItems: 4
  67     description: |
  68       phandles to one or more reserved on-chip SRAM regions.
  69       phandle to the On Chip Memory (OCMEM) that's present on some a3xx and
  70       a4xx Snapdragon SoCs. See
  71       Documentation/devicetree/bindings/sram/qcom,ocmem.yaml
  72
  73   operating-points-v2: true
  74   opp-table:
  75     type: object
  76
  77   power-domains:
  78     maxItems: 1
  79
  80   zap-shader:
  81     type: object
  82     description: |
  83       For a5xx and a6xx devices this node contains a memory-region that
  84       points to reserved memory to store the zap shader that can be used to
  85       help bring the GPU out of secure mode.
  86     properties:
  87       memory-region:
  88         $ref: /schemas/types.yaml#/definitions/phandle
  89
  90       firmware-name:
  91         description: |
  92           Default name of the firmware to load to the remote processor.
  93
  94   "#cooling-cells":
  95     const: 2
  96
  97   nvmem-cell-names:
  98     maxItems: 1
  99
 100   nvmem-cells:
 101     description: efuse registers
 102     maxItems: 1
 103
 104   qcom,gmu:
 105     $ref: /schemas/types.yaml#/definitions/phandle
 106     description: |
 107       For GMU attached devices a phandle to the GMU device that will
 108       control the power for the GPU.
 109
 110
 111 required:
 112   - compatible
 113   - reg
 114   - interrupts
 115
 116 additionalProperties: false
 117
 118 allOf:
 119   - if:
 120       properties:
 121         compatible:
 122           contains:
 123             pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]$'
 124
 125     then:
 126       properties:
 127         clocks:
 128           minItems: 2
 129           maxItems: 7
 130
 131         clock-names:
 132           items:
 133             anyOf:
 134               - const: core
 135                 description: GPU Core clock
 136               - const: iface
 137                 description: GPU Interface clock
 138               - const: mem
 139                 description: GPU Memory clock
 140               - const: mem_iface
 141                 description: GPU Memory Interface clock
 142               - const: alt_mem_iface
 143                 description: GPU Alternative Memory Interface clock
 144               - const: gfx3d
 145                 description: GPU 3D engine clock
 146               - const: rbbmtimer
 147                 description: GPU RBBM Timer for Adreno 5xx series
 148           minItems: 2
 149           maxItems: 7
 150
 151       required:
 152         - clocks
 153         - clock-names
 154   - if:
 155       properties:
 156         compatible:
 157           contains:
 158             pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$'
 159
 160     then: # Since Adreno 6xx series clocks should be defined in GMU
 161       properties:
 162         clocks: false
 163         clock-names: false
 164
 165 examples:
 166   - |
 167
 168     // Example a3xx/4xx:
 169
 170     #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
 171     #include <dt-bindings/clock/qcom,rpmcc.h>
 172     #include <dt-bindings/interrupt-controller/irq.h>
 173     #include <dt-bindings/interrupt-controller/arm-gic.h>
 174
 175     gpu: gpu@fdb00000 {
 176         compatible = "qcom,adreno-330.2", "qcom,adreno";
 177
 178         reg = <0xfdb00000 0x10000>;
 179         reg-names = "kgsl_3d0_reg_memory";
 180
 181         clock-names = "core", "iface", "mem_iface";
 182         clocks = <&mmcc OXILI_GFX3D_CLK>,
 183                  <&mmcc OXILICX_AHB_CLK>,
 184                  <&mmcc OXILICX_AXI_CLK>;
 185
 186         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 187         interrupt-names = "kgsl_3d0_irq";
 188
 189         sram = <&gpu_sram>;
 190         power-domains = <&mmcc OXILICX_GDSC>;
 191         operating-points-v2 = <&gpu_opp_table>;
 192         iommus = <&gpu_iommu 0>;
 193         #cooling-cells = <2>;
 194     };
 195
 196     ocmem@fdd00000 {
 197         compatible = "qcom,msm8974-ocmem";
 198
 199         reg = <0xfdd00000 0x2000>,
 200               <0xfec00000 0x180000>;
 201         reg-names = "ctrl", "mem";
 202
 203         clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
 204                  <&mmcc OCMEMCX_OCMEMNOC_CLK>;
 205         clock-names = "core", "iface";
 206
 207         #address-cells = <1>;
 208         #size-cells = <1>;
 209         ranges = <0 0xfec00000 0x100000>;
 210
 211         gpu_sram: gpu-sram@0 {
 212             reg = <0x0 0x100000>;
 213         };
 214     };
 215   - |
 216
 217     // Example a6xx (with GMU):
 218
 219     #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
 220     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
 221     #include <dt-bindings/power/qcom-rpmpd.h>
 222     #include <dt-bindings/interrupt-controller/irq.h>
 223     #include <dt-bindings/interrupt-controller/arm-gic.h>
 224     #include <dt-bindings/interconnect/qcom,sdm845.h>
 225
 226     reserved-memory {
 227         #address-cells = <2>;
 228         #size-cells = <2>;
 229
 230         zap_shader_region: gpu@8f200000 {
 231             compatible = "shared-dma-pool";
 232             reg = <0x0 0x90b00000 0x0 0xa00000>;
 233             no-map;
 234         };
 235     };
 236
 237     gpu@5000000 {
 238         compatible = "qcom,adreno-630.2", "qcom,adreno";
 239
 240         reg = <0x5000000 0x40000>, <0x509e000 0x10>;
 241         reg-names = "kgsl_3d0_reg_memory", "cx_mem";
 242
 243         #cooling-cells = <2>;
 244
 245         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
 246
 247         iommus = <&adreno_smmu 0>;
 248
 249         operating-points-v2 = <&gpu_opp_table>;
 250
 251         interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>;
 252         interconnect-names = "gfx-mem";
 253
 254         qcom,gmu = <&gmu>;
 255
 256         gpu_opp_table: opp-table {
 257             compatible = "operating-points-v2";
 258
 259             opp-430000000 {
 260                 opp-hz = /bits/ 64 <430000000>;
 261                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
 262                 opp-peak-kBps = <5412000>;
 263             };
 264
 265             opp-355000000 {
 266                 opp-hz = /bits/ 64 <355000000>;
 267                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
 268                 opp-peak-kBps = <3072000>;
 269             };
 270
 271             opp-267000000 {
 272                 opp-hz = /bits/ 64 <267000000>;
 273                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
 274                 opp-peak-kBps = <3072000>;
 275             };
 276
 277             opp-180000000 {
 278                 opp-hz = /bits/ 64 <180000000>;
 279                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
 280                 opp-peak-kBps = <1804000>;
 281             };
 282         };
 283
 284         zap-shader {
 285             memory-region = <&zap_shader_region>;
 286             firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn";
 287         };
 288     };