Bindings/display/msm/qcom,mdp5.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/msm/qcom,mdp5.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Adreno/Snapdragon Mobile Display controller (MDP5)
   8
   9 description:
  10   MDP5 display controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994
  11   and MSM8996.
  12
  13 maintainers:
  14   - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
  15   - Rob Clark <robdclark@gmail.com>
  16
  17 properties:
  18   compatible:
  19     oneOf:
  20       - const: qcom,mdp5
  21         deprecated: true
  22       - items:
  23           - enum:
  24               - qcom,apq8084-mdp5
  25               - qcom,msm8916-mdp5
  26               - qcom,msm8917-mdp5
  27               - qcom,msm8953-mdp5
  28               - qcom,msm8974-mdp5
  29               - qcom,msm8976-mdp5
  30               - qcom,msm8994-mdp5
  31               - qcom,msm8996-mdp5
  32               - qcom,sdm630-mdp5
  33               - qcom,sdm660-mdp5
  34           - const: qcom,mdp5
  35
  36   $nodename:
  37     pattern: '^display-controller@[0-9a-f]+$'
  38
  39   reg:
  40     maxItems: 1
  41
  42   reg-names:
  43     items:
  44       - const: mdp_phys
  45
  46   interrupts:
  47     maxItems: 1
  48
  49   clocks:
  50     minItems: 4
  51     maxItems: 7
  52
  53   clock-names:
  54     oneOf:
  55       - minItems: 4
  56         items:
  57           - const: iface
  58           - const: bus
  59           - const: core
  60           - const: vsync
  61           - const: lut
  62           - const: tbu
  63           - const: tbu_rt
  64         # MSM8996 has additional iommu clock
  65       - items:
  66           - const: iface
  67           - const: bus
  68           - const: core
  69           - const: iommu
  70           - const: vsync
  71
  72   interconnects:
  73     minItems: 1
  74     items:
  75       - description: Interconnect path from mdp0 (or a single mdp) port to the data bus
  76       - description: Interconnect path from mdp1 port to the data bus
  77       - description: Interconnect path from rotator port to the data bus
  78
  79   interconnect-names:
  80     minItems: 1
  81     items:
  82       - const: mdp0-mem
  83       - const: mdp1-mem
  84       - const: rotator-mem
  85
  86   iommus:
  87     items:
  88       - description: apps SMMU with the Stream-ID mask for Hard-Fail port0
  89
  90   power-domains:
  91     maxItems: 1
  92
  93   operating-points-v2: true
  94   opp-table:
  95     type: object
  96
  97   ports:
  98     $ref: /schemas/graph.yaml#/properties/ports
  99     description: >
 100       Contains the list of output ports from DPU device. These ports
 101       connect to interfaces that are external to the DPU hardware,
 102       such as DSI, DP etc. MDP5 devices support up to 4 ports:
 103       one or two DSI ports, HDMI and eDP.
 104
 105     patternProperties:
 106       "^port@[0-3]+$":
 107         $ref: /schemas/graph.yaml#/properties/port
 108
 109     # at least one port is required
 110     required:
 111       - port@0
 112
 113 required:
 114   - compatible
 115   - reg
 116   - reg-names
 117   - clocks
 118   - clock-names
 119   - ports
 120
 121 additionalProperties: false
 122
 123 examples:
 124   - |
 125     #include <dt-bindings/clock/qcom,gcc-msm8916.h>
 126     #include <dt-bindings/interrupt-controller/arm-gic.h>
 127     display-controller@1a01000 {
 128         compatible = "qcom,mdp5";
 129         reg = <0x1a01000 0x90000>;
 130         reg-names = "mdp_phys";
 131
 132         interrupt-parent = <&mdss>;
 133         interrupts = <0>;
 134
 135         clocks = <&gcc GCC_MDSS_AHB_CLK>,
 136                  <&gcc GCC_MDSS_AXI_CLK>,
 137                  <&gcc GCC_MDSS_MDP_CLK>,
 138                  <&gcc GCC_MDSS_VSYNC_CLK>;
 139         clock-names = "iface",
 140                       "bus",
 141                       "core",
 142                       "vsync";
 143
 144         ports {
 145             #address-cells = <1>;
 146             #size-cells = <0>;
 147
 148             port@0 {
 149                 reg = <0>;
 150                 endpoint {
 151                     remote-endpoint = <&dsi0_in>;
 152                 };
 153             };
 154         };
 155     };
 156 ...